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    • 2. 发明授权
    • Data processor and method of processing data in parallel
    • 数据处理器和并行处理数据的方法
    • US5634107A
    • 1997-05-27
    • US540029
    • 1995-10-06
    • Masahiro YumotoKenichi Kobayashi
    • Masahiro YumotoKenichi Kobayashi
    • G06T1/20G06F15/16G06F15/80G06F15/00
    • G06F15/8007
    • A plurality of data processing units each having a first controller for computing design data assigned in advance so as to generate graphic data and a first storage device for receiving transfer of the design data and storing the design data temporarily, and a second controller, for when a data storage allowable value of the first storage device which has received transfer of the design data is exceeded, recognizing a data excess flag rising on that occasion, and transferring excessive data in the design data assigned to the one data processing unit to another data processing unit, thereby controlling computation share among data processing units. The design data are converted in parallel into graphic data while monitoring is performed of the data processing units. By adopting such a structure, it is no longer required to increase the number of fields for reassigning design data more than necessary, and it is possible to achieve high-speed processing of parallel data, such as mask data, of the LSI within the capacity of the field memory given to the data processing units.
    • 多个数据处理单元,每个数据处理单元具有用于计算预先分配以便生成图形数据的设计数据的第一控制器和用于接收设计数据的传送并临时存储设计数据的第一存储装置,以及第二控制器,用于何时 超过已经接收到设计数据的传送的第一存储装置的数据存储容许值,识别当时的数据过量标志上升,并且将分配给一个数据处理单元的设计数据中的过多数据传送到另一数据处理 从而控制数据处理单元之间的计算共享。 将设计数据并行转换为图形数据,同时对数据处理单元进行监视。 通过采用这样的结构,不再需要增加用于重新分配设计数据的字段的数量,并且可以在LSI的容量内实现LSI的并行数据(诸如屏蔽数据)的高速处理 提供给数据处理单元的现场存储器。
    • 6. 发明授权
    • Signal processing apparatus, signal processing method, and reception system
    • 信号处理装置,信号处理方法和接收系统
    • US08358722B2
    • 2013-01-22
    • US12833409
    • 2010-07-09
    • Tadaaki YubaTakuya OkamotoYuken GotoKenichi Kobayashi
    • Tadaaki YubaTakuya OkamotoYuken GotoKenichi Kobayashi
    • H04L27/06
    • H04L27/2675H04L27/2613H04L27/2659H04L27/2666H04L27/2672H04L27/2682H04L27/2685
    • Disclosed herein is a signal processing apparatus including a processing block configured to perform a carrier shift amount detection process for detecting a carrier shift amount constituting a carrier error used for demodulating an orthogonal frequency division multiplexing signal known as the OFDM signal; and a correction block configured to correct the OFDM signal in accordance with the carrier shift amount. The OFDM signal includes a first preamble signal including subcarriers, and a second preamble signal including subcarriers of which the spacing is narrower than the spacing of the subcarriers included in the first preamble signal. The second preamble signal includes pilot signals which are known signals located at intervals of a predetermined number of subcarriers. The processing block detects the carrier shift amount using a correlation of the subcarriers included in one such second preamble signal.
    • 这里公开了一种信号处理装置,包括:处理块,被配置为执行用于检测构成用于解调称为OFDM信号的正交频分复用信号的载波误差的载波移位量的载波移位量检测处理; 以及校正块,被配置为根据载波移位量校正OFDM信号。 OFDM信号包括包括子载波的第一前导码信号和包括间隔窄于包括在第一前导信号中的子载波的间隔的子载波的第二前导码信号。 第二前导信号包括作为以预定数量的副载波间隔设置的已知信号的导频信号。 处理块使用包括在一个这样的第二前导信号中的子载波的相关性来检测载波移位量。