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1. 发明授权

US06433607B1 Input circuit and semiconductor integrated circuit having the input circuit 有权
公开(公告)号：US06433607B1
公开(公告)日：2002-08-13
申请号：US09344810
申请日：1999-06-25
申请人： Kenichi Kawasaki , Yasuharu Sato , Yasurou Matsuzaki , Takaaki Suzuki
发明人： Kenichi Kawasaki , Yasuharu Sato , Yasurou Matsuzaki , Takaaki Suzuki
IPC分类号： H03K300
摘要： An input circuit has an input buffer and a detection circuit. The input buffer receives an external signal and outputs an internal signal. The detection circuit detects whether or not the external signal is provided. The input buffer outputs the internal signal when an output of the detection circuit indicates that the external signal is provided. This arrangement shortens the lock-on time of an internal circuit (synchronous circuit).

2. 发明授权

US06771108B2 Input circuit and semiconductor integrated circuit having the input circuit 有权
标题翻译：具有输入电路的输入电路和半导体集成电路
公开(公告)号：US06771108B2
公开(公告)日：2004-08-03
申请号：US10152614
申请日：2002-05-23
申请人： Kenichi Kawasaki , Yasuharu Sato , Yasurou Matsuzaki , Takaaki Suzuki
发明人： Kenichi Kawasaki , Yasuharu Sato , Yasurou Matsuzaki , Takaaki Suzuki
IPC分类号： H03K300
CPC分类号： G11C7/109 , G11C7/1078 , G11C7/222 , G11C7/225 , G11C7/227 , G11C11/406 , G11C11/40615 , H03L7/0814
摘要： An input circuit has an input buffer and a detection circuit. The input buffer receives an external signal and outputs an internal signal. The detection circuit detects whether or not the external signal is provided. The input buffer outputs the internal signal when an output of the detection circuit indicates that the external signal is provided. This arrangement shortens the lock-on time of an internal circuit (synchronous circuit).
摘要翻译：输入电路具有输入缓冲器和检测电路。输入缓冲器接收外部信号并输出内部信号。检测电路检测外部信号是否被提供。当检测电路的输出指示提供外部信号时，输入缓冲器输出内部信号。这种布置缩短了内部电路（同步电路）的锁定时间。

3. 发明授权

US06498524B1 Input/output data synchronizing device 有权
标题翻译：输入/输出数据同步装置
公开(公告)号：US06498524B1
公开(公告)日：2002-12-24
申请号：US09706731
申请日：2000-11-07
申请人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
发明人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
IPC分类号： H03L708
CPC分类号： G11C7/106 , G06F13/4243 , G11C7/1006 , G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C2207/002 , G11C2207/108 , H03K5/133 , H03K2005/00058 , H03L7/0805 , H03L7/0814
摘要： Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.
摘要翻译：公开了一种用于输出具有相对于外部时钟保持的给定相位的输出信号的半导体器件，尽管特性差，温度变化和电源电压波动。该半导体器件包括用于输入外部时钟并输出参考信号的输入电路，用于接收输出定时信号并根据输出定时信号的定时输出输出信号的输出电路和用于控制的输出定时控制电路输出定时，使得输出信号相对于外部时钟呈现给定的相位。输出定时控制电路包括用于将参考信号延迟指定幅度并产生输出定时信号的延迟电路，用于将输出定时信号的相位与参考信号的相位进行比较的相位比较电路和延迟控制电路，用于根据由相位比较电路执行的比较结果来指定由延迟电路产生的延迟的大小。

4. 发明授权

US06298004B1 Semiconductor device, semiconductor system, and digital delay circuit 失效
标题翻译：半导体器件，半导体系统和数字延迟电路
公开(公告)号：US06298004B1
公开(公告)日：2001-10-02
申请号：US08892790
申请日：1997-07-15
申请人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
发明人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
IPC分类号： G11C800
CPC分类号： G11C7/106 , G06F13/4243 , G11C7/1006 , G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C2207/002 , G11C2207/108 , H03K5/133 , H03K2005/00058 , H03L7/0805 , H03L7/0814
摘要： Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.
摘要翻译：公开了一种用于输出具有相对于外部时钟保持的给定相位的输出信号的半导体器件，尽管特性差，温度变化和电源电压波动。该半导体器件包括用于输入外部时钟并输出参考信号的输入电路，用于接收输出定时信号并根据输出定时信号的定时输出输出信号的输出电路和用于控制的输出定时控制电路输出定时，使得输出信号相对于外部时钟呈现给定的相位。输出定时控制电路包括用于将参考信号延迟指定幅度并产生输出定时信号的延迟电路，用于将输出定时信号的相位与参考信号的相位进行比较的相位比较电路和延迟控制电路，用于根据由相位比较电路执行的比较结果来指定由延迟电路产生的延迟的大小。

5. 发明申请

US20050242864A1 Semiconductor device, semiconductor system, and digital delay circuit 审中-公开
标题翻译：半导体器件，半导体系统和数字延迟电路
公开(公告)号：US20050242864A1
公开(公告)日：2005-11-03
申请号：US11055784
申请日：2005-02-11
申请人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
发明人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
IPC分类号： G06F13/42 , G11C7/10 , G11C7/22 , H03H11/26 , H03K5/00 , H03K5/13 , H03L7/081
CPC分类号： G11C7/106 , G06F13/4243 , G11C7/1006 , G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C2207/002 , G11C2207/108 , H03K5/133 , H03K2005/00058 , H03L7/0805 , H03L7/0814
摘要： Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.
摘要翻译：公开了一种用于输出具有相对于外部时钟保持的给定相位的输出信号的半导体器件，尽管特性差，温度变化和电源电压波动。该半导体器件包括用于输入外部时钟并输出参考信号的输入电路，用于接收输出定时信号并根据输出定时信号的定时输出输出信号的输出电路和用于控制的输出定时控制电路输出定时，使得输出信号相对于外部时钟呈现给定的相位。输出定时控制电路包括用于将参考信号延迟指定幅度并产生输出定时信号的延迟电路，用于将输出定时信号的相位与参考信号的相位进行比较的相位比较电路和延迟控制电路，用于根据由相位比较电路执行的比较结果来指定由延迟电路产生的延迟的大小。

6. 发明授权

US07120761B2 Multi-port memory based on DRAM core 有权
公开(公告)号：US07120761B2
公开(公告)日：2006-10-10
申请号：US10284092
申请日：2002-10-31
申请人： Yasurou Matsuzaki , Takaaki Suzuki , Masafumi Yamazaki , Kenichi Kawasaki , Shinnosuke Kamata , Ayako Sato , Masato Matsumiya
发明人： Yasurou Matsuzaki , Takaaki Suzuki , Masafumi Yamazaki , Kenichi Kawasaki , Shinnosuke Kamata , Ayako Sato , Masato Matsumiya
IPC分类号： G06F12/00
CPC分类号： G11C8/16 , G06F13/1605 , G11C7/1039 , G11C7/1075 , G11C7/1078 , G11C7/22 , G11C8/18 , G11C11/24 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/409 , G11C11/4093 , G11C2207/107 , G11C2207/108
摘要： A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.

7. 发明申请

US20060294322A1 Multi-port memory based on DRAM core 有权
公开(公告)号：US20060294322A1
公开(公告)日：2006-12-28
申请号：US11512319
申请日：2006-08-30
申请人： Yasurou Matsuzaki , Takaaki Suzuki , Masafumi Yamazaki , Kenichi Kawasaki , Shinnosuke Kamata , Ayako Sato , Masato Matsumiya
发明人： Yasurou Matsuzaki , Takaaki Suzuki , Masafumi Yamazaki , Kenichi Kawasaki , Shinnosuke Kamata , Ayako Sato , Masato Matsumiya
IPC分类号： G06F13/28
CPC分类号： G11C8/16 , G06F13/1605 , G11C7/1039 , G11C7/1075 , G11C7/1078 , G11C7/22 , G11C8/18 , G11C11/24 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/409 , G11C11/4093 , G11C2207/107 , G11C2207/108
摘要： A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.

8. 发明授权

US07911825B2 Multi-port memory based on DRAM core 有权
标题翻译：基于DRAM内核的多端口存储器
公开(公告)号：US07911825B2
公开(公告)日：2011-03-22
申请号：US11512319
申请日：2006-08-30
申请人： Yasurou Matsuzaki , Takaaki Suzuki , Masafumi Yamazaki , Kenichi Kawasaki , Shinnosuke Kamata , Ayako Sato , Masato Matsumiya
发明人： Yasurou Matsuzaki , Takaaki Suzuki , Masafumi Yamazaki , Kenichi Kawasaki , Shinnosuke Kamata , Ayako Sato , Masato Matsumiya
IPC分类号： G11C11/24
CPC分类号： G11C8/16 , G06F13/1605 , G11C7/1039 , G11C7/1075 , G11C7/1078 , G11C7/22 , G11C8/18 , G11C11/24 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/409 , G11C11/4093 , G11C2207/107 , G11C2207/108
摘要： A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.
摘要翻译：半导体存储器件包括多个N个外部端口，每个N个外部端口接收命令;以及内部电路，其在输入到一个外部端口的命令的最小间隔期间执行至少N次访问操作。

9. 发明授权

US06774655B2 Semiconductor device, method of testing the semiconductor device, and semiconductor integrated circuit 有权
标题翻译：半导体器件，半导体器件的测试方法以及半导体集成电路
公开(公告)号：US06774655B2
公开(公告)日：2004-08-10
申请号：US10622472
申请日：2003-07-21
申请人： Yasurou Matsuzaki , Masao Nakano , Toshiya Uchida , Atsushi Hatakeyama , Kenichi Kawasaki , Yasuhiro Fujii
发明人： Yasurou Matsuzaki , Masao Nakano , Toshiya Uchida , Atsushi Hatakeyama , Kenichi Kawasaki , Yasuhiro Fujii
IPC分类号： G01R3102
CPC分类号： G11C29/022 , G11C29/02
摘要： A semiconductor device mounted on a board or the like and having a test circuit, having the function of carrying out a contact test at a low cost on the terminals of the semiconductor, is disclosed. The semiconductor device comprises a terminal test circuit for testing a state of a contact of an external terminal and a test mode control circuit unit. The test mode control circuit unit outputs a signal indicating a first operation mode upon application of a power supply voltage thereto, outputs a test mode signal to the terminal test circuit in response to a control signal input to a specific terminal such as a chip select terminal, and outputs a signal indicating a second operation mode in response to the number of times in which the level of the control signal input to the specific terminal changes. Preferably, the first operation mode is a terminal test mode, and the second operation mode is a normal operation mode. A method of testing the semiconductor device and a semiconductor integrated circuit, having the test circuit, are also disclosed.
摘要翻译：公开了一种安装在板等上并具有测试电路的半导体器件，具有在半导体端子上以低成本进行接触测试的功能。半导体器件包括用于测试外部端子和测试模式控制电路单元的接触状态的端子测试电路。测试模式控制电路单元在施加电源电压时输出指示第一操作模式的信号，响应于输入到诸如芯片选择端子的特定终端的控制信号，向终端测试电路输出测试模式信号并且响应于输入到特定终端的控制信号的电平改变的次数而输出指示第二操作模式的信号。优选地，第一操作模式是终端测试模式，并且第二操作模式是正常操作模式。还公开了一种测试半导体器件的方法和具有测试电路的半导体集成电路。

10. 发明授权

US06621283B1 Semiconductor device, method of testing the semiconductor device, and semiconductor integrated circuit 有权
标题翻译：半导体器件，半导体器件的测试方法以及半导体集成电路
公开(公告)号：US06621283B1
公开(公告)日：2003-09-16
申请号：US09437221
申请日：1999-11-10
申请人： Yasurou Matsuzaki , Masao Nakano , Toshiya Uchida , Atsushi Hatakeyama , Kenichi Kawasaki , Yasuhiro Fujii
发明人： Yasurou Matsuzaki , Masao Nakano , Toshiya Uchida , Atsushi Hatakeyama , Kenichi Kawasaki , Yasuhiro Fujii
IPC分类号： G01R3102
CPC分类号： G11C29/022 , G11C29/02
摘要： A semiconductor device mounted on a board or the like and having a test circuit, having the function of carrying out a contact test at a low cost on the terminals of the semiconductor, is disclosed. The semiconductor device comprises a terminal test circuit for testing a state of a contact of an external terminal and a test mode control circuit unit. The test mode control circuit unit outputs a signal indicating a first operation mode upon application of a power supply voltage thereto, outputs a test mode signal to the terminal test circuit in response to a control signal input to a specific terminal such as a chip select terminal, and outputs a signal indicating a second operation mode in response to the number of times in which the level of the control signal input to the specific terminal changes. Preferably, the first operation mode is a terminal test mode, and the second operation mode is a normal operation mode. A method of testing the semiconductor device and a semiconductor integrated circuit, having the test circuit, are also disclosed.
摘要翻译：公开了一种安装在板等上并具有测试电路的半导体器件，具有在半导体端子上以低成本进行接触测试的功能。半导体器件包括用于测试外部端子和测试模式控制电路单元的接触状态的端子测试电路。测试模式控制电路单元在施加电源电压时输出指示第一操作模式的信号，响应于输入到诸如芯片选择端子的特定终端的控制信号，向终端测试电路输出测试模式信号并且响应于输入到特定终端的控制信号的电平改变的次数而输出指示第二操作模式的信号。优选地，第一操作模式是终端测试模式，并且第二操作模式是正常操作模式。还公开了一种测试半导体器件的方法和具有测试电路的半导体集成电路。

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