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1. 发明申请

US20070103962A1 Programmable memory cell and operation method 失效
标题翻译：可编程存储单元和操作方法
公开(公告)号：US20070103962A1
公开(公告)日：2007-05-10
申请号：US11271550
申请日：2005-11-09
申请人： Keng-Li Su , Shyh-Shyuan Sheu , Jan-Ruei Lin , Wei-Jen Chang , Chen-Pang Kung
发明人： Keng-Li Su , Shyh-Shyuan Sheu , Jan-Ruei Lin , Wei-Jen Chang , Chen-Pang Kung
IPC分类号： G11C11/00
CPC分类号： G11C13/00 , B82Y10/00 , G11C13/0014 , G11C2213/79
摘要： A memory array including a plurality of programmable memory cells, a plurality of column lines and a plurality of row lines is introduced. Each of the programmable memory cells is coupled to corresponding one of the column lines and corresponding one of the row lines. Each of the programmable memory cells includes an organic memory cell and an active switching element. The active switching element is controlled by the column line and interposed between the row line and the organic memory cell. Under controlling of the column line, the active switching element is turned on to coupling the row line and the organic memory cell to connect to each other.
摘要翻译：引入包括多个可编程存储器单元，多个列线和多个行线的存储器阵列。每个可编程存储器单元耦合到对应的列线和对应的一行行。每个可编程存储器单元包括有机存储单元和有源开关元件。有源开关元件由列线控制并插入在行线和有机存储单元之间。在列线的控制下，有源开关元件被接通以将行线和有机存储器单元耦合以彼此连接。

2. 发明授权

US07369424B2 Programmable memory cell and operation method 失效
标题翻译：可编程存储单元和操作方法
公开(公告)号：US07369424B2
公开(公告)日：2008-05-06
申请号：US11271550
申请日：2005-11-09
申请人： Keng-Li Su , Shyh-Shyuan Sheu , Jan-Ruel Lin , Wei-Jen Chang , Chen-Pang Kung
发明人： Keng-Li Su , Shyh-Shyuan Sheu , Jan-Ruel Lin , Wei-Jen Chang , Chen-Pang Kung
IPC分类号： G11C11/00 , G11C11/14
CPC分类号： G11C13/00 , B82Y10/00 , G11C13/0014 , G11C2213/79
摘要： A memory array including a plurality of programmable memory cells, a plurality of column lines and a plurality of row lines is introduced. Each of the programmable memory cells is coupled to corresponding one of the column lines and corresponding one of the row lines. Each of the programmable memory cells includes an organic memory cell and an active switching element. The active switching element is controlled by the column line and interposed between the row line and the organic memory cell. Under controlling of the column line, the active switching element is turned on to coupling the row line and the organic memory cell to connect to each other.
摘要翻译：引入包括多个可编程存储器单元，多个列线和多个行线的存储器阵列。每个可编程存储器单元耦合到对应的列线和对应的一行行。每个可编程存储器单元包括有机存储单元和有源开关元件。有源开关元件由列线控制并插入在行线和有机存储单元之间。在列线的控制下，有源开关元件被接通以将行线和有机存储器单元耦合以彼此连接。

3. 发明申请

US20060243974A1 Thin-film transistor 审中-公开
标题翻译：薄膜晶体管
公开(公告)号：US20060243974A1
公开(公告)日：2006-11-02
申请号：US11175440
申请日：2005-07-07
申请人： Keng-Li Su , Chen-Pang Kung , Jan-Ruei Lin , Chia-Pao Chang , Yi-Hsun Huang
发明人： Keng-Li Su , Chen-Pang Kung , Jan-Ruei Lin , Chia-Pao Chang , Yi-Hsun Huang
IPC分类号： H01L29/04
CPC分类号： H01L29/78603 , H01L27/1296 , H01L29/41733
摘要： A thin-film transistor (TFT) is described to have a gate layer, an insulating layer, a semiconductor layer, and a source/drain layer formed on a flexible substrate. The source and the drain layers are separated by a channel with a special shape. This does not only increase the aspect ratio of the channel per unit area, the source and the drain also have multiple directions for transmitting carriers. The carrier mobility of the TFT is thus enhanced with uniform and stable circuit properties.
摘要翻译：薄膜晶体管（TFT）被描述为具有形成在柔性基板上的栅极层，绝缘层，半导体层和源极/漏极层。源极和漏极层由具有特殊形状的通道分开。这不仅增加了每单位面积通道的纵横比，而且源和漏还具有用于传输载体的多个方向。因此，TFT的载流子迁移率增强，具有均匀且稳定的电路特性。

4. 发明申请

US20080157826A1 VOLTAGE DRIVING CIRCUIT 审中-公开
标题翻译：电压驱动电路
公开(公告)号：US20080157826A1
公开(公告)日：2008-07-03
申请号：US11739114
申请日：2007-04-24
申请人： Ming-Daw Chen , Shyh-Shyuan Sheu , Wei-Chun Chang , Keng-Li Su
发明人： Ming-Daw Chen , Shyh-Shyuan Sheu , Wei-Chun Chang , Keng-Li Su
IPC分类号： H03K3/00
CPC分类号： G09G3/3648 , G09G2300/0465 , G09G2300/0809 , G09G2300/0823 , G09G2300/0857
摘要： A voltage driving circuit, suitable for being used in a pixel driving circuit, includes a storage unit for receiving a single-end data input signal and outputting a first voltage signal and a second voltage signal according to a content of the data input signal. The first voltage signal and the second voltage signal have different voltage levels, and the voltage levels are a high voltage level and a low voltage level, which have been adjusted to a driving-voltage requirement satisfying subsequent operations. A switch control unit receives the first voltage signal and the second voltage signal and outputs an output-voltage signal at an output terminal based on a determination from at least one control signal. The output-voltage signal is the high voltage level or the low voltage level.
摘要翻译：适用于像素驱动电路的电压驱动电路包括：存储单元，用于接收单端数据输入信号，并根据数据输入信号的内容输出第一电压信号和第二电压信号。第一电压信号和第二电压信号具有不同的电压电平，并且电压电平是已经被调整到满足后续操作的驱动电压要求的高电压电平和低电压电平。开关控制单元接收第一电压信号和第二电压信号，并且基于来自至少一个控制信号的确定在输出端输出输出电压信号。输出电压信号为高电平或低电平。

5. 发明申请

US20120139092A1 MULTI-CHIP STACK STRUCTURE 有权
标题翻译：多芯片堆叠结构
公开(公告)号：US20120139092A1
公开(公告)日：2012-06-07
申请号：US12968285
申请日：2010-12-15
申请人： Keng-Li Su , Hsin-Chi Lai , Chih-Sheng Lin , Zhe-Hui Lin
发明人： Keng-Li Su , Hsin-Chi Lai , Chih-Sheng Lin , Zhe-Hui Lin
IPC分类号： H01L23/552
CPC分类号： H01L25/0657 , H01L23/642 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06537 , H01L2225/06541
摘要： A multi-chip stack structure including a first chip, a second chip, a shielding layer, and a plurality of conductive bumps is provided. The second chip is stacked on the first chip. The second chip has a plurality of through silicon via (TSV) structures to conduct a reference voltage. The shielding layer and the plurality of conductive bumps are disposed between the first chip and the second chip, and are electrically connected to the plurality of TSV structures. The shielding layer can isolate noises and improve signal coupling between two adjacent chips.
摘要翻译：提供了包括第一芯片，第二芯片，屏蔽层和多个导电凸块的多芯片堆叠结构。第二芯片堆叠在第一芯片上。第二芯片具有多个贯穿硅通孔（TSV）结构以导通参考电压。屏蔽层和多个导电凸块设置在第一芯片和第二芯片之间，并且电连接到多个TSV结构。屏蔽层可以隔离噪声并改善两个相邻芯片之间的信号耦合。

6. 发明授权

US08219340B2 Monitoring method for through-silicon vias of three-dimensional intergrated circuit (3D IC) and apparatus using the same 有权
标题翻译：三维集成电路（3D IC）的硅通孔监视方法及使用该通孔的设备
公开(公告)号：US08219340B2
公开(公告)日：2012-07-10
申请号：US12435311
申请日：2009-05-04
申请人： Keng-Li Su , Chih Sheng Lin , Chih-Wen Hsiao
发明人： Keng-Li Su , Chih Sheng Lin , Chih-Wen Hsiao
IPC分类号： G01R13/00 , G01R29/26
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A monitoring method for Through-Silicon Vias (TSVs) of a three-dimensional integrated circuit (3D IC) is provided, wherein the 3D IC includes a plurality of TSVs, and the method includes: providing a plurality of inverters; connecting the inverters with the TSVs as a circuit; enabling the circuit to oscillate; measuring an output signal on an output end of one of the inverters; and determining the characteristic of TSVs of the 3D IC based on the output signal.
摘要翻译：提供了一种三维集成电路（3D IC）的通硅通孔（TSV）的监视方法，其中3D IC包括多个TSV，并且该方法包括：提供多个逆变器; 将变频器与TSV连接作为电路; 使电路振荡; 测量其中一个逆变器的输出端的输出信号; 以及基于输出信号确定3D IC的TSV的特性。

7. 发明授权

US06980780B2 Power controller 有权
标题翻译：电源控制器
公开(公告)号：US06980780B2
公开(公告)日：2005-12-27
申请号：US09855511
申请日：2001-05-16
申请人： Chieh-Sheng Chen , Keng-Li Su
发明人： Chieh-Sheng Chen , Keng-Li Su
IPC分类号： H03F3/19 , H03G3/30 , H04B1/04
CPC分类号： H03G3/3042 , H03F3/19 , H04B2001/0416
摘要： An apparatus for power controlling in a transmitter for detecting the output power without using a power coupler includes a plurality of stage amplifiers, a plurality of matching circuits, at least one power detector, and a bias control circuit. The stage amplifiers receive an emission signal and amplify the power thereof. The matching circuits are connected between the stage amplifiers for matching with the stage amplifiers, respectively. The power detector detects the power of the stage amplifiers and generates detection signals, respectively. The bias control circuit receives the detection signals of the power detector, thereby generating a bias of each of the stage amplifiers in order to optimize the efficiency of each of the stage amplifiers according to the magnitude of the power of each of the stage amplifiers.
摘要翻译：一种用于在不使用功率耦合器的情况下检测输出功率的发射机中的功率控制的装置包括多个级放大器，多个匹配电路，至少一个功率检测器和偏置控制电路。舞台放大器接收发射信号并放大其功率。匹配电路分别连接在级放大器之间，以与舞台放大器匹配。功率检测器检测级放大器的功率，分别产生检测信号。偏置控制电路接收功率检测器的检测信号，从而产生每个级放大器的偏置，以便根据每个级放大器的功率的大小优化每个级放大器的效率。

8. 发明授权

US07539068B2 Memory and multi-state sense amplifier thereof 有权
标题翻译：存储器和多状态读出放大器
公开(公告)号：US07539068B2
公开(公告)日：2009-05-26
申请号：US11797725
申请日：2007-05-07
申请人： Min-Chuan Wang , Ching-Sheng Lin , Chia-Pao Chang , Keng-Li Su
发明人： Min-Chuan Wang , Ching-Sheng Lin , Chia-Pao Chang , Keng-Li Su
IPC分类号： G11C7/10
CPC分类号： G11C7/14 , G11C7/06 , G11C7/062 , G11C11/5642 , G11C2207/063 , G11C2211/5634 , G11C2211/5645
摘要： The invention provides a multi-state sense amplifier, coupled to at least one memory cell and a plurality of reference cells. The source follower, coupled between a first node and the output terminal of the memory cell, clamps the voltage drop across the memory cell to generate a memory cell current flowing through the first node. The source follower circuit, coupled between a plurality of second nodes and the output terminals of the reference cells, clamps the voltage drops across the reference cells to generate a plurality of reference currents respectively flowing through the second nodes. The current mirror circuit, coupled to the first node and the second nodes, duplicates the memory cell current of the first node to affect the reference currents on the second nodes, thereby generating a memory cell voltage on the first node and a plurality of reference voltages on the second nodes.
摘要翻译：本发明提供一种耦合到至少一个存储单元和多个参考单元的多状态读出放大器。耦合在第一节点和存储器单元的输出端之间的源极跟随器钳位在存储器单元两端的电压降，以产生流经第一节点的存储单元电流。耦合在多个第二节点和参考单元的输出端子之间的源极跟随器电路钳位参考单元上的电压降，以产生分别流过第二节点的多个参考电流。耦合到第一节点和第二节点的电流镜像电路复制第一节点的存储器单元电流，以影响第二节点上的参考电流，从而在第一节点上产生存储单元电压，并产生多个参考电压在第二个节点上。

9. 发明授权

US07486546B2 Multi-state sense amplifier 有权
标题翻译：多状态读出放大器
公开(公告)号：US07486546B2
公开(公告)日：2009-02-03
申请号：US11806636
申请日：2007-06-01
申请人： Min-Chuan Wang , Chih-Sheng Lin , Chia-Pao Chang , Keng-Li Su
发明人： Min-Chuan Wang , Chih-Sheng Lin , Chia-Pao Chang , Keng-Li Su
IPC分类号： G11C11/00
CPC分类号： G11C7/062 , G11C7/06 , G11C11/1673 , G11C11/5607 , G11C2207/063 , G11C2211/5634 , G11C2211/5645
摘要： The invention provides a multi-state sense amplifier, coupled to at least one memory cell with changeable resistance and a plurality of reference cells. The first current mirror circuit, coupled to the output terminal of the memory cell, generates a second memory cell current at a first node according to a first memory cell current through the memory cell. The second current mirror circuit, coupled to the output terminal of the reference cells, generates a plurality of second reference currents at a plurality of second nodes according to a plurality of first reference currents through the reference cells. The load circuit, coupled to the first node, the second nodes, and a ground, provides equal loads for the second memory cell current and the second reference currents to respectively generate a memory cell voltage at the first node and a plurality of reference voltages at the second nodes.
摘要翻译：本发明提供一种多状态读出放大器，耦合到具有可变电阻的至少一个存储单元和多个参考单元。耦合到存储器单元的输出端的第一电流镜电路根据通过存储单元的第一存储单元电流在第一节点产生第二存储单元电流。耦合到参考单元的输出端的第二电流镜电路根据通过参考单元的多个第一参考电流在多个第二节点处产生多个第二参考电流。耦合到第一节点，第二节点和地的负载电路为第二存储器单元电流和第二参考电流提供相等的负载，以分别在第一节点处产生存储单元电压和多个参考电压第二个节点。

10. 发明申请

US20080007992A1 Multi-state sense amplifier 有权
标题翻译：多状态读出放大器
公开(公告)号：US20080007992A1
公开(公告)日：2008-01-10
申请号：US11806636
申请日：2007-06-01
申请人： Min-Chuan Wang , Chih-Sheng Lin , Chia-Pao Chang , Keng-Li Su
发明人： Min-Chuan Wang , Chih-Sheng Lin , Chia-Pao Chang , Keng-Li Su
IPC分类号： G11C11/02 , G11C7/06
CPC分类号： G11C7/062 , G11C7/06 , G11C11/1673 , G11C11/5607 , G11C2207/063 , G11C2211/5634 , G11C2211/5645
摘要： The invention provides a multi-state sense amplifier, coupled to at least one memory cell with changeable resistance and a plurality of reference cells. The first current mirror circuit, coupled to the output terminal of the memory cell, generates a second memory cell current at a first node according to a first memory cell current through the memory cell. The second current mirror circuit, coupled to the output terminal of the reference cells, generates a plurality of second reference currents at a plurality of second nodes according to a plurality of first reference currents through the reference cells. The load circuit, coupled to the first node, the second nodes, and a ground, provides equal loads for the second memory cell current and the second reference currents to respectively generate a memory cell voltage at the first node and a plurality of reference voltages at the second nodes.
摘要翻译：本发明提供一种多状态读出放大器，耦合到具有可变电阻的至少一个存储单元和多个参考单元。耦合到存储器单元的输出端的第一电流镜电路根据通过存储单元的第一存储单元电流在第一节点产生第二存储单元电流。耦合到参考单元的输出端的第二电流镜电路根据通过参考单元的多个第一参考电流在多个第二节点处产生多个第二参考电流。耦合到第一节点，第二节点和接地的负载电路为第二存储器单元电流和第二参考电流提供相等的负载，以分别在第一节点处产生存储器单元电压和多个参考电压第二个节点。

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