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1. 发明授权

US07544552B2 Method for manufacturing junction semiconductor device 有权
标题翻译：结半导体器件的制造方法
公开(公告)号：US07544552B2
公开(公告)日：2009-06-09
申请号：US11386661
申请日：2006-03-23
申请人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Kensuke Iwanaga , Yoshimitsu Saito , Hiroaki Iwakuro , Masaaki Shimizu , Yusuke Fukuda , Koichi Nishikawa , Yusuke Maeyama
发明人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Kensuke Iwanaga , Yoshimitsu Saito , Hiroaki Iwakuro , Masaaki Shimizu , Yusuke Fukuda , Koichi Nishikawa , Yusuke Maeyama
IPC分类号： H01L21/337 , H01L29/772 , H01L21/339 , H01L21/338 , H01L29/768 , H01L29/78
CPC分类号： H01L29/7722
摘要： A method for manufacturing a junction semiconductor device, having a step for forming a first high-resistance layer, a step for forming a channel-doped layer, a step for forming a second high-resistance layer, a step for forming a low-resistance layer of a first conductive type that acts as a source region, a step for performing partial etching to a midway depth of the second high-resistance layer and the low-resistance layer, a step for forming a gate region below the portion etched in the etching step, and a step for forming a protective film on the surface of the region between the gate region and the source region. A gate region is formed using relatively low energy ion implantation in the surface that has been etched in advance to a height that is between the lower surface of the source area and the upper surface of the channel-doped layer.
摘要翻译：一种用于制造具有形成第一高电阻层的步骤的接合半导体器件的制造方法，形成沟道掺杂层的步骤，用于形成第二高电阻层的步骤，形成低电阻的步骤作为源极区域的第一导电类型的层，用于对第二高电阻层和低电阻层的中间深度进行部分蚀刻的步骤，用于在第二高电阻层和低电阻层的蚀刻部分的下方形成栅极区域的步骤蚀刻步骤，以及在栅极区域和源极区域之间的区域的表面上形成保护膜的步骤。在表面中使用相对较低能量的离子注入，预先将蚀刻的源极区域的下表面和沟道掺杂层的上表面之间的高度形成为栅极区域。

2. 发明申请

US20060216879A1 Method for manufacturing junction semiconductor device 有权
公开(公告)号：US20060216879A1
公开(公告)日：2006-09-28
申请号：US11386661
申请日：2006-03-23
申请人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Kensuke Iwanaga , Yoshimitsu Saito , Hiroaki Iwakuro , Masaaki Shimizu , Yusuke Fukuda , Koichi Nishikawa , Yusuke Maeyama
发明人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Kensuke Iwanaga , Yoshimitsu Saito , Hiroaki Iwakuro , Masaaki Shimizu , Yusuke Fukuda , Koichi Nishikawa , Yusuke Maeyama
IPC分类号： H01L21/337
CPC分类号： H01L29/7722
摘要： A method for manufacturing a junction semiconductor device, having a step for forming a first high-resistance layer, a step for forming a channel-doped layer, a step for forming a second high-resistance layer, a step for forming a low-resistance layer of a first conductive type that acts as a source region, a step for performing partial etching to a midway depth of the second high-resistance layer and the low-resistance layer, a step for forming a gate region below the portion etched in the etching step, and a step for forming a protective film on the surface of the region between the gate region and the source region. A gate region is formed using relatively low energy ion implantation in the surface that has been etched in advance to a height that is between the lower surface of the source area and the upper surface of the channel-doped layer.

3. 发明申请

US20060214200A1 Junction semiconductor device and method for manufacturing the same 失效
标题翻译：结半导体器件及其制造方法
公开(公告)号：US20060214200A1
公开(公告)日：2006-09-28
申请号：US11386850
申请日：2006-03-23
申请人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Kensuke Iwanaga , Yoshimitsu Saito
发明人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Kensuke Iwanaga , Yoshimitsu Saito
IPC分类号： H01L31/113
CPC分类号： H01L29/7722 , Y10S438/931
摘要： A junction semiconductor device having a drain region comprising a low-resistance layer of a first conductive type formed on one surface of a semiconductor crystal, a source region comprising a low-resistance layer of a first conductive type formed on the other surface of the semiconductor crystal, a gate region of a second conductive type formed on the periphery of the source region, a high-resistance layer of a first conductive type between the source region and the drain region, and a recombination-inhibiting semiconductor layer of a second conductive type provided in the vicinity of the surface of the semiconductor crystal between the gate region and the source region.
摘要翻译：一种结半导体器件，具有包括形成在半导体晶体的一个表面上的第一导电类型的低电阻层的漏极区域，包括形成在半导体的另一个表面上的第一导电类型的低电阻层的源极区域晶体，形成在源极区域周围的第二导电类型的栅极区域，在源极区域和漏极区域之间的第一导电类型的高电阻层，以及第二导电类型的复合抑制半导体层设置在栅极区域和源极区域之间的半导体晶体的表面附近。

4. 发明授权

US07867836B2 Method for manufacturing junction semiconductor device 失效
标题翻译：结半导体器件的制造方法
公开(公告)号：US07867836B2
公开(公告)日：2011-01-11
申请号：US12203660
申请日：2008-09-03
申请人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Kensuke Iwanaga , Yoshimitsu Saito
发明人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Kensuke Iwanaga , Yoshimitsu Saito
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/7722 , Y10S438/931
摘要： A method for manufacturing a junction semiconductor device having a drain region including a low-resistance layer of a first conductive type formed on one surface of a semiconductor crystal, a source region including a low-resistance layer of a first conductive type formed on the other surface of the semiconductor crystal, a gate region of a second conductive type formed on the periphery of the source region, a high-resistance layer of a first conductive type between the source region and the drain region, and a recombination-inhibiting semiconductor layer of a second conductive type provided in the vicinity of the surface of the semiconductor crystal between the gate region and the source region.
摘要翻译：一种用于制造具有形成在半导体晶体的一个表面上的具有第一导电类型的低电阻层的漏极区域的结半导体器件的方法，包括形成在另一个上的第一导电类型的低电阻层的源极区域半导体晶体的表面，形成在源极区域周围的第二导电类型的栅极区域，在源极区域和漏极区域之间的第一导电类型的高电阻层，以及复合抑制半导体层设置在栅极区域和源极区域之间的半导体晶体的表面附近的第二导电类型。

5. 发明授权

US07449734B2 Junction semiconductor device and method for manufacturing the same 失效
标题翻译：结半导体器件及其制造方法
公开(公告)号：US07449734B2
公开(公告)日：2008-11-11
申请号：US11386850
申请日：2006-03-23
申请人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Kensuke Iwanaga , Yoshimitsu Saito
发明人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Kensuke Iwanaga , Yoshimitsu Saito
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/119
CPC分类号： H01L29/7722 , Y10S438/931
摘要： A junction semiconductor device having a drain region including a low-resistance layer of a first conductive type formed on one surface of a semiconductor crystal, a source region including a low-resistance layer of a first conductive type formed on the other surface of the semiconductor crystal, a gate region of a second conductive type formed on the periphery of the source region, a high-resistance layer of a first conductive type between the source region and the drain region, and a recombination-inhibiting semiconductor layer of a second conductive type provided in the vicinity of the surface of the semiconductor crystal between the gate region and the source region.
摘要翻译：具有形成在半导体晶体的一个表面上的具有第一导电类型的低电阻层的漏极区的结半导体器件，包括形成在半导体的另一个表面上的第一导电类型的低电阻层的源极区域晶体，形成在源极区域周围的第二导电类型的栅极区域，在源极区域和漏极区域之间的第一导电类型的高电阻层，以及第二导电类型的复合抑制半导体层设置在栅极区域和源极区域之间的半导体晶体的表面附近。

6. 发明申请

US20090004790A1 METHOD FOR MANUFACTURING JUNCTION SEMICONDUCTOR DEVICE 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20090004790A1
公开(公告)日：2009-01-01
申请号：US12203660
申请日：2008-09-03
申请人： Ken-ichi NONAKA , Hideki Hashimoto , Seiichi Yokoyama , Kensuke Iwanaga , Yoshimitsu Saito
发明人： Ken-ichi NONAKA , Hideki Hashimoto , Seiichi Yokoyama , Kensuke Iwanaga , Yoshimitsu Saito
IPC分类号： H01L21/337
CPC分类号： H01L29/7722 , Y10S438/931
摘要： A method for manufacturing a junction semiconductor device having a drain region including a low-resistance layer of a first conductive type formed on one surface of a semiconductor crystal, a source region including a low-resistance layer of a first conductive type formed on the other surface of the semiconductor crystal, a gate region of a second conductive type formed on the periphery of the source region, a high-resistance layer of a first conductive type between the source region and the drain region, and a recombination-inhibiting semiconductor layer of a second conductive type provided in the vicinity of the surface of the semiconductor crystal between the gate region and the source region.
摘要翻译：一种用于制造具有形成在半导体晶体的一个表面上的具有第一导电类型的低电阻层的漏极区域的结半导体器件的方法，包括形成在另一个上的第一导电类型的低电阻层的源极区域半导体晶体的表面，形成在源极区域周围的第二导电类型的栅极区域，在源极区域和漏极区域之间的第一导电类型的高电阻层，以及复合抑制半导体层设置在栅极区域和源极区域之间的半导体晶体的表面附近的第二导电类型。

7. 发明授权

US07671467B2 Power semiconductor module 有权
标题翻译：功率半导体模块
公开(公告)号：US07671467B2
公开(公告)日：2010-03-02
申请号：US11798152
申请日：2007-05-10
申请人： Kenichi Nonaka , Takeshi Kato , Kenji Oogushi , Yoshihiko Higashidani , Yoshimitsu Saito , Kenji Okamoto
发明人： Kenichi Nonaka , Takeshi Kato , Kenji Oogushi , Yoshihiko Higashidani , Yoshimitsu Saito , Kenji Okamoto
IPC分类号： H01L23/12 , H01L21/50 , H01L21/44
CPC分类号： H01L23/057 , H01L23/3735 , H01L24/45 , H01L24/48 , H01L25/072 , H01L2224/32225 , H01L2224/45124 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/73265 , H01L2924/01079 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/16195 , H01L2924/19107 , H01L2924/3011 , H05K1/0271 , H05K1/0306 , H05K3/0061 , H05K3/38 , H05K2201/0355 , H05K2201/068 , H01L2924/00014 , H01L2924/00 , H01L2924/00015
摘要： A power semiconductor module having an integral circuit board with a metal substrate electrode, an insulation substrate and a heat sink joined is disclosed. A SiC semiconductor power device is joined to a top of the metal substrate electrode of the circuit board. A difference in average coefficients of thermal expansion between constituent materials of the circuit board in a temperature range from room to joining time temperatures is 2.0 ppm/° C. or less, and a difference in expansion, produced by a difference between a lowest operating temperature and a joining temperature, of the circuit-board constituent materials is 2,000 ppm or less.
摘要翻译：公开了具有金属基板电极，绝缘基板和散热片接合的集成电路板的功率半导体模块。 SiC半导体功率器件接合到电路板的金属衬底电极的顶部。在从室温到接合时间温度的温度范围内，电路板的构成材料的平均热膨胀系数的差异为2.0ppm /℃以下，膨胀差由最低工作温度并且电路板构成材料的接合温度为2000ppm以下。

8. 发明授权

US5770803A Semiconductor stress sensor 失效
标题翻译：半导体应力传感器
公开(公告)号：US5770803A
公开(公告)日：1998-06-23
申请号：US707461
申请日：1996-09-04
申请人： Yoshimitsu Saito
发明人： Yoshimitsu Saito
IPC分类号： G01L1/00 , G01P15/12 , H01L29/84
CPC分类号： G01P15/124 , Y10S73/04
摘要： A semiconductor substrate has a surface layer disposed underneath a gate electrode of a field-effect transistor and having a resistance higher than the resistance of an inner layer which is formed in the semiconductor substrate below the surface layer. The surface layer is formed when a donor doped in the surface layer and an acceptor generated based on a compressive stress which is developed in the surface layer when the gate electrode is formed substantially cancel out each other. The field-effect transistor operates alternatively as a junction field-effect transistor when the surface layer is turned into a p-type structure when a compressive stress is generated in the surface layer and a metal semiconductor field-effect transistor when the surface layer is turned into an n-type structure when a tensile stress is generated in the surface layer.
摘要翻译：半导体衬底具有设置在场效应晶体管的栅电极下方的表面层，并且具有比形成在表面层下方的半导体衬底中的内层的电阻高的电阻。当形成表面层的施主和基于在形成栅极的表面层中形成的压缩应力产生的受主时，表面层形成为基本相互抵消。当在表面层产生压缩应力时，当表面层转变成p型结构时，场效应晶体管作为结型场效应晶体管工作，当表面层转动时，场效应晶体管和金属半导体场效应晶体管在表面层产生拉伸应力时成为n型结构。

9. 发明申请

US20070262387A1 Power semiconductor module 有权
标题翻译：功率半导体模块
公开(公告)号：US20070262387A1
公开(公告)日：2007-11-15
申请号：US11798152
申请日：2007-05-10
申请人： Kenichi Nonaka , Takeshi Kato , Kenji Oogushi , Yoshihiko Higashidani , Yoshimitsu Saito , Kenji Okamoto
发明人： Kenichi Nonaka , Takeshi Kato , Kenji Oogushi , Yoshihiko Higashidani , Yoshimitsu Saito , Kenji Okamoto
IPC分类号： H01L23/62
CPC分类号： H01L23/057 , H01L23/3735 , H01L24/45 , H01L24/48 , H01L25/072 , H01L2224/32225 , H01L2224/45124 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/73265 , H01L2924/01079 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/16195 , H01L2924/19107 , H01L2924/3011 , H05K1/0271 , H05K1/0306 , H05K3/0061 , H05K3/38 , H05K2201/0355 , H05K2201/068 , H01L2924/00014 , H01L2924/00 , H01L2924/00015
摘要： A power semiconductor module having an integral circuit board with a metal substrate electrode, an insulation substrate and a heat sink joined is disclosed. A SiC semiconductor power device is joined to a top of the metal substrate electrode of the circuit board. A difference in average coefficients of thermal expansion between constituent materials of the circuit board in a temperature range from room to joining time temperatures is 2.0 ppm/° C. or less, and a difference in expansion, produced by a difference between a lowest operating temperature and a joining temperature, of the circuit-board constituent materials is 2,000 ppm or less.
摘要翻译：公开了具有金属基板电极，绝缘基板和散热片接合的集成电路板的功率半导体模块。 SiC半导体功率器件接合到电路板的金属衬底电极的顶部。在从室温到接合时间温度的温度范围内，电路板的构成材料的平均热膨胀系数的差异为2.0ppm /℃以下，膨胀差由最低工作温度并且电路板构成材料的接合温度为2000ppm以下。

10. 发明授权

US5372878A Slackened or creased fibrous sheet 失效
标题翻译：松弛或褶皱纤维片
公开(公告)号：US5372878A
公开(公告)日：1994-12-13
申请号：US921847
申请日：1992-06-23
申请人： Yoshimitsu Saito
发明人： Yoshimitsu Saito
IPC分类号： B44C5/04 , D06M11/45 , D06M11/76 , D06M15/263 , D06M15/564 , D06M17/04 , D06M17/10 , D21H19/38 , D21H19/62 , D21H19/66 , D21H19/74 , D21H21/28 , B32B5/16
CPC分类号： D21H19/385 , B44C5/0469 , D06M11/45 , D06M11/76 , D06M15/263 , D06M15/564 , D06M17/04 , D06M17/10 , D21H19/62 , D21H19/66 , D21H19/74 , D21H21/285 , Y10T428/25 , Y10T428/273 , Y10T428/2996 , Y10T442/2164 , Y10T442/2352 , Y10T442/2369
摘要： Paper having a relatively high rigidity including Japanese paper and fibrous sheet such as vegetable fibrous sheet and nonwoven fabric are used as base materials for finishing without subjected to any processing while fibrous sheets including some sorts of Japanese paper and spunbonded nonwoven fabric being high in softness and flexibility and bulky, and machine-made paper being lightweight and thin, and moreover having a relatively high rigidity are incapable of or nondurable to physical processing such as beating, bending and crumpling, so that the pretreatment or preliminary processing (primary processing) is applied to these sheets for use as base materials in such a manner that they are resin-treated or have plastic material, elastomer film, woven cloth or one selected from a group of fibrous sheets similar to the above attached thereto so as to convert them into composite sheets. The obtained base materials are subjected to the physical processing, whereby the fibrous texture of the base materials for finishing is slackened, and resin-treated for strengthening, whereby the base materials for finishing are improved in strength and provided with the resilience, water repellency, bulkiness, decorative effect and so forth, so that they can be utilized for daily goods, personal belongings, clothing, interior decoration and so forth when finished. The present invention relates to the raw materials thereof.
摘要翻译：除了日本纸，纺粘纤维片，无纺布等纤维片以外，具有比较高刚性的纸作为基材，而不进行任何加工，其中包括各种日本纸和纺粘非织造织物的柔软度高的纤维片和弹性和体积大，机械制造的纸张轻巧而薄，而且具有较高的刚度，不能或不能对物理加工如打浆，弯曲和皱褶进行处理，从而应用预处理或初步处理（初级处理）以这些片材为基础材料，以使它们被树脂处理或具有塑料材料，弹性体膜，织布或选自与上述相似的一组纤维片材中的一种，以便将它们转化为复合材料床单。所获得的基材进行物理加工，由此用于精加工的基材的纤维织构松弛，并进行树脂处理以进行加强，由此精加工用基材的强度提高，具有回弹性，防水性，蓬松性，装饰效果等，完成后可用于日用品，个人物品，服装，室内装饰等。本发明涉及其原料。

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