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1. 发明授权

US08347274B2 Debugging support device, debugging support method, and program thereof 有权
标题翻译：调试支持设备，调试支持方法及其程序
公开(公告)号：US08347274B2
公开(公告)日：2013-01-01
申请号：US12558716
申请日：2009-09-14
申请人： Ken Tanabe , Takahiro Tokuyoshi
发明人： Ken Tanabe , Takahiro Tokuyoshi
IPC分类号： G06F9/44
CPC分类号： G06F11/261 , G06F11/362
摘要： A debugging support device includes: a plurality of CPU simulating units which simulates the operations of a plurality of CPUs which executes programs in parallel; a memory simulating unit of a memory to be shared by the plurality of CPUs; an event monitoring unit that detects a predetermined event occurring between each CPU simulating unit and the memory simulating unit; and a state judging unit that judges whether the state of the occurred predetermined event matches a predetermined condition and, if the predetermined condition is matched, records history information related to the state of the memory simulating unit.
摘要翻译：调试支持装置包括：多个CPU模拟单元，其模拟并行执行程序的多个CPU的操作; 由所述多个CPU共享的存储器的存储器模拟单元; 事件监视单元，其检测在每个CPU模拟单元和所述存储器模拟单元之间发生的预定事件; 以及状态判断单元，判断所发生的预定事件的状态是否符合预定条件，并且如果所述预定条件匹配，则记录与所述存储器模拟单元的状态相关的历史信息。

2. 发明申请

US20100175051A1 DEBUGGING SUPPORT DEVICE, DEBUGGING SUPPORT METHOD, AND PROGRAM THEREOF 有权
标题翻译：调试支持设备，调试支持方法及其程序
公开(公告)号：US20100175051A1
公开(公告)日：2010-07-08
申请号：US12558716
申请日：2009-09-14
申请人： Ken Tanabe , Takahiro Tokuyoshi
发明人： Ken Tanabe , Takahiro Tokuyoshi
IPC分类号： G06F9/44
CPC分类号： G06F11/261 , G06F11/362
摘要： A debugging support device includes: a plurality of CPU simulating units which simulates the operations of a plurality of CPUs which executes programs in parallel; a memory simulating unit of a memory to be shared by the plurality of CPUs; an event monitoring unit that detects a predetermined event occurring between each CPU simulating unit and the memory simulating unit; and a state judging unit that judges whether the state of the occurred predetermined event matches a predetermined condition and, if the predetermined condition is matched, records history information related to the state of the memory simulating unit.
摘要翻译：调试支持装置包括：多个CPU模拟单元，其模拟并行执行程序的多个CPU的操作; 由所述多个CPU共享的存储器的存储器模拟单元; 事件监视单元，其检测在每个CPU模拟单元和所述存储器模拟单元之间发生的预定事件; 以及状态判断单元，判断所发生的预定事件的状态是否符合预定条件，并且如果所述预定条件匹配，则记录与所述存储器模拟单元的状态相关的历史信息。

3. 发明申请

US20130019230A1 Program Generating Apparatus, Method of Generating Program, and Medium 审中-公开
标题翻译：程序生成装置，程序生成方法和介质
公开(公告)号：US20130019230A1
公开(公告)日：2013-01-17
申请号：US13423641
申请日：2012-03-19
申请人： Yu Nakanishi , Toshiki Kizu , Shunsuke Sasaki , Takahiro Tokuyoshi
发明人： Yu Nakanishi , Toshiki Kizu , Shunsuke Sasaki , Takahiro Tokuyoshi
IPC分类号： G06F9/45
CPC分类号： G06F11/3419 , G06F8/47 , G06F11/3447 , G06F11/3466 , G06F2201/865
摘要： According to an embodiment, a program generating apparatus includes a cross-compiling unit, a processing time calculating unit, a source code converting unit, and a self-compiling unit. The cross-compiling unit generates sin instruction string for each basic block based on a source code and specifies instructions performing a memory access. The processing time calculating unit calculates a processing time of the instruction string for each basic block. The source code converting unit inserts a first code, which adds the processing time of the basic block to an accumulated processing time variable of an executed thread of the basic block, and a second code, which calculates the processing time for the specified memory access and adds the calculated processing time to the accumulated processing time variable, into the source code. The self-compiling unit generates a performance estimating program outputting the accumulated processing time variable of the thread executed.
摘要翻译：根据实施例，程序生成装置包括交叉编译单元，处理时间计算单元，源代码转换单元和自编译单元。交叉编译单元基于源代码为每个基本块生成sin指令串，并指定执行存储器访问的指令。处理时间计算单元计算每个基本块的指令串的处理时间。源代码转换单元插入将基本块的处理时间添加到基本块的执行线程的累积处理时间变量的第一代码和计算指定存储器访问的处理时间的第二代码，将计算出的处理时间添加到累积处理时间变量中，加入到源代码中。自编译单元生成输出执行的线程的累积处理时间变量的性能估计程序。

4. 发明授权

US5838953A Information processing apparatus 失效
标题翻译：信息处理装置
公开(公告)号：US5838953A
公开(公告)日：1998-11-17
申请号：US800172
申请日：1997-02-13
申请人： Takahiro Tokuyoshi
发明人： Takahiro Tokuyoshi
IPC分类号： G06F9/30 , G06F9/38 , G06F9/455 , G06F9/48 , G06F11/28
CPC分类号： G06F9/3861 , G06F9/45533
摘要： The present invention has the following arrangement. That is, an instruction stream for performing an instruction simulation is analyzed before the instruction simulation is started to predict a timing at which interruption occurs, an interrupt generating unit generates a predictive interrupt signal one instruction cycle before interruption occurs on the basis of the prediction result, and, when an instruction which is executed immediately after the predictive interrupt signal is generated has a flag-less instruction identifier, an execution process of the instruction which is executed immediately after the predictive interrupt signal is generated is performed according to not a flag-less instruction code but a flag instruction code.
摘要翻译：本发明具有以下结构。也就是说，在开始指令模拟以预测发生中断的定时之前分析用于执行指令模拟的指令流，中断产生单元根据预测结果产生中断发生之前的一个指令周期的预测中断信号并且当在产生预测中断信号之后立即执行的指令具有无标志指令标识符时，在产生预测中断信号之后立即执行的指令的执行处理根据标志位执行，较少的指令代码，而是一个标志指令代码。

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