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1. 发明申请

US20140326952A1 SILICON AND SILICON GERMANIUM NANOWIRE STRUCTURES 审中-公开
标题翻译：硅和硅锗纳米结构
公开(公告)号：US20140326952A1
公开(公告)日：2014-11-06
申请号：US14274592
申请日：2014-05-09
申请人： Kelin J. KUHN , Seiyon KIM , Rafael RIOS , Stephen M. Cea , Martin D. GILES , Annalisa CAPPELLANI , Titash RAKSHIT , Peter CHANG , Willy RACHMADY
发明人： Kelin J. KUHN , Seiyon KIM , Rafael RIOS , Stephen M. Cea , Martin D. GILES , Annalisa CAPPELLANI , Titash RAKSHIT , Peter CHANG , Willy RACHMADY
IPC分类号： H01L29/06 , H01L29/66 , H01L29/165 , H01L29/78
CPC分类号： H01L29/0673 , B82Y10/00 , H01L21/76224 , H01L27/0922 , H01L27/1203 , H01L29/0676 , H01L29/1033 , H01L29/16 , H01L29/165 , H01L29/41733 , H01L29/42392 , H01L29/66439 , H01L29/66742 , H01L29/66795 , H01L29/775 , H01L29/7848 , H01L29/785 , H01L29/78618 , H01L29/78654 , H01L29/78684 , H01L29/78696
摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.
摘要翻译：描述形成微电子结构的方法。这些方法的实施例包括形成纳米线装置，其包括基板，该基板包括与间隔物相邻的源极/漏极结构，以及设置在间隔物之间的纳米线通道结构，其中纳米线通道结构在彼此之上垂直堆叠。

2. 发明申请

US20130185540A1 PROCESSOR WITH MULTI-LEVEL LOOPING VECTOR COPROCESSOR 审中-公开
标题翻译：具有多级循环向量协处理器的处理器
公开(公告)号：US20130185540A1
公开(公告)日：2013-07-18
申请号：US13548924
申请日：2012-07-13
申请人： Ching-Yu HUNG , Shinri INAMORI , Jagadeesh SANKARAN , Peter CHANG
发明人： Ching-Yu HUNG , Shinri INAMORI , Jagadeesh SANKARAN , Peter CHANG
IPC分类号： G06F15/80
CPC分类号： G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30065 , G06F9/30087 , G06F9/30098 , G06F9/3012 , G06F9/3013 , G06F9/345 , G06F9/3887 , G06F15/76 , G06F15/8007
摘要： A processor includes a scalar processor core and a vector coprocessor core coupled to the scalar processor core. The scalar processor core includes a program memory interface through which the scalar processor retrieves instructions from a program memory. The instructions include scalar instructions executable by the scalar processor and vector instructions executable by the vector coprocessor core. The vector coprocessor core includes a plurality of execution units and a vector command buffer. The vector command buffer is configured to decode vector instructions passed by the scalar processor core, to determine whether vector instructions defining an instruction loop have been decoded, and to initiate execution of the instruction loop by one or more of the execution units based on a determination that all of the vector instructions of the instruction loop have been decoded.
摘要翻译：处理器包括标量处理器核心和耦合到标量处理器核心的向量协处理器核心。标量处理器核心包括程序存储器接口，标量处理器通过该存储器接口从程序存储器检索指令。指令包括可由标量处理器执行的标量指令和由矢量协处理器核心执行的向量指令。向量协处理器核心包括多个执行单元和向量命令缓冲器。矢量命令缓冲器被配置为对由标量处理器核心传递的矢量指令进行解码，以确定定义指令循环的矢量指令是否已被解码，并且基于确定执行单元中的一个或多个执行指令循环指令循环的所有向量指令都被解码。

3. 发明申请

US20130185544A1 PROCESSOR WITH INSTRUCTION VARIABLE DATA DISTRIBUTION 有权
标题翻译：具有可变数据分配的处理器
公开(公告)号：US20130185544A1
公开(公告)日：2013-07-18
申请号：US13548933
申请日：2012-07-13
申请人： Ching-Yu HUNG , Shinri INAMORI , Jagadeesh SANKARAN , Peter CHANG
发明人： Ching-Yu HUNG , Shinri INAMORI , Jagadeesh SANKARAN , Peter CHANG
IPC分类号： G06F9/30
CPC分类号： G06F15/8053 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30065 , G06F9/30087 , G06F9/30098 , G06F9/3012 , G06F9/3013 , G06F9/3887 , G06F15/76 , G06F15/8007
摘要： A vector processor includes a plurality of execution units arranged in parallel, a register file, and a plurality of load units. The register file includes a plurality of registers coupled to the execution units. Each of the load units is configured to load, in a single transaction, a plurality of the registers with data retrieved from memory. The loaded registers corresponding to different execution units. Each of the load units is configured to distribute the data to the registers in accordance with an instruction selectable distribution. The instruction selectable distribution specifies one of plurality of distributions. Each of the distributions specifies a data sequence that differs from the sequence in which the data is stored in memory.
摘要翻译：矢量处理器包括并行排列的多个执行单元，寄存器堆和多个负载单元。寄存器文件包括耦合到执行单元的多个寄存器。每个负载单元被配置为在单个事务中加载具有从存储器检索的数据的多个寄存器。加载的寄存器对应于不同的执行单元。每个负载单元被配置为根据指令可选择分布将数据分配给寄存器。指令可选择分布指定多个分布中的一个。每个分布都指定与数据存储在存储器中的序列不同的数据序列。

4. 发明申请

US20130150219A1 VERTICAL AUXILIARY APPARATUS FOR BOTH BODY INVERSION AND REHABILITATION 审中-公开
标题翻译：用于身体反射和康复的垂直辅助装置
公开(公告)号：US20130150219A1
公开(公告)日：2013-06-13
申请号：US13547394
申请日：2012-07-12
申请人： Peter CHANG
发明人： Peter CHANG
IPC分类号： A63B26/00
CPC分类号： A61H1/0229 , A61G7/005 , A61H2201/123 , A61H2201/1623 , A61H2201/1642 , A61H2203/0493
摘要： The present invention is to provide a vertical auxiliary apparatus for both body inversion and rehabilitation, which includes a base positioned on the ground and having first and second pivotal connecting portions at positions adjacent to one end thereof, a motor pivotally connected to the first pivotal connecting portion, a telescoping rod having a first end movably connected to the motor, a supporting frame pivotally connected to the second pivotal connecting portion at a position adjacent to a first end thereof and a second end of the telescoping rod at a position adjacent to a second end thereof respectively, and a foot frame fastened to one end of the supporting frame. Thus, when the motor is activated, the second end of the telescoping rod drives the supporting frame to rotate about a fulcrum defined by the second pivotal connecting portion and change the tilt angle relative to the ground.
摘要翻译：本发明提供一种用于车身反转和恢复的立式辅助装置，其包括位于地面上的基座，并且在与其一端相邻的位置处具有第一和第二枢转连接部分，枢转地连接到第一枢转连接伸缩杆，其具有可移动地连接到所述马达的第一端;支撑框架，其在与其第一端相邻的位置处枢转地连接到所述第二枢转连接部分，并且所述伸缩杆的第二端在与所述第二枢转连接部分的第二端并且固定到支撑框架的一端的脚架。因此，当电动机被启动时，伸缩杆的第二端驱动支撑框架围绕由第二枢转连接部分限定的支点旋转，并相对于地面改变倾斜角度。

5. 发明申请

US20130185539A1 PROCESSOR WITH TABLE LOOKUP AND HISTOGRAM PROCESSING UNITS 审中-公开
标题翻译：具有表查询和组织处理单元的处理器
公开(公告)号：US20130185539A1
公开(公告)日：2013-07-18
申请号：US13548955
申请日：2012-07-13
申请人： Ching-Yu HUNG , Shinri INAMORI , Jagadeesh SANKARAN , Peter CHANG
发明人： Ching-Yu HUNG , Shinri INAMORI , Jagadeesh SANKARAN , Peter CHANG
IPC分类号： G06F15/76
摘要： A processor includes a scalar processor core and a vector coprocessor core coupled to the scalar processor core. The scalar processor core is configured to retrieve an instruction stream from program storage, and pass vector instructions in the instruction stream to the vector coprocessor core. The vector coprocessor core includes a register file, a plurality of execution units, and a table lookup unit. The register file includes a plurality of registers. The execution units are arranged in parallel to process a plurality of data values. The execution units are coupled to the register file. The table lookup unit is coupled to the register file in parallel with the execution units. The table lookup unit is configured to retrieve table values from one or more lookup tables stored in memory by executing table lookup vector instructions in a table lookup loop.
摘要翻译：处理器包括标量处理器核心和耦合到标量处理器核心的向量协处理器核心。标量处理器核心被配置为从程序存储检索指令流，并将指令流中的向量指令传递给向量协处理器核心。向量协处理器核心包括寄存器文件，多个执行单元和表查找单元。寄存器文件包括多个寄存器。执行单元并行布置以处理多个数据值。执行单元耦合到寄存器文件。表查找单元与执行单元并行地耦合到寄存器文件。表查找单元被配置为通过在表查找循环中执行表查找向量指令来从存储在存储器中的一个或多个查找表中检索表值。

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