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1. 发明授权

US08619866B2 Reducing memory bandwidth for processing digital image data 有权
标题翻译：减少处理数字图像数据的内存带宽
公开(公告)号：US08619866B2
公开(公告)日：2013-12-31
申请号：US12572768
申请日：2009-10-02
申请人： Minhua Zhou , Ching-Yu Hung
发明人： Minhua Zhou , Ching-Yu Hung
IPC分类号： H04N7/12 , H04N11/02 , H04N11/04
CPC分类号： H04N19/426 , H04N19/61
摘要： A method for processing digital image data is provided that includes compressing a block of the digital image data to generate a compressed block, storing the compressed block in an external memory when a number of bits in the compressed block does not exceed a first compression threshold, and storing the block in the external memory when the number of bits in the compressed block exceeds the first compression threshold.
摘要翻译：提供一种处理数字图像数据的方法，包括：压缩数字图像数据块以产生压缩块，当压缩块中的位数不超过第一压缩阈值时，将压缩块存储在外部存储器中，以及当所述压缩块中的比特数超过所述第一压缩阈值时，将所述块存储在所述外部存储器中。

2. 发明申请

US20130185540A1 PROCESSOR WITH MULTI-LEVEL LOOPING VECTOR COPROCESSOR 审中-公开
标题翻译：具有多级循环向量协处理器的处理器
公开(公告)号：US20130185540A1
公开(公告)日：2013-07-18
申请号：US13548924
申请日：2012-07-13
申请人： Ching-Yu HUNG , Shinri INAMORI , Jagadeesh SANKARAN , Peter CHANG
发明人： Ching-Yu HUNG , Shinri INAMORI , Jagadeesh SANKARAN , Peter CHANG
IPC分类号： G06F15/80
CPC分类号： G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30065 , G06F9/30087 , G06F9/30098 , G06F9/3012 , G06F9/3013 , G06F9/345 , G06F9/3887 , G06F15/76 , G06F15/8007
摘要： A processor includes a scalar processor core and a vector coprocessor core coupled to the scalar processor core. The scalar processor core includes a program memory interface through which the scalar processor retrieves instructions from a program memory. The instructions include scalar instructions executable by the scalar processor and vector instructions executable by the vector coprocessor core. The vector coprocessor core includes a plurality of execution units and a vector command buffer. The vector command buffer is configured to decode vector instructions passed by the scalar processor core, to determine whether vector instructions defining an instruction loop have been decoded, and to initiate execution of the instruction loop by one or more of the execution units based on a determination that all of the vector instructions of the instruction loop have been decoded.
摘要翻译：处理器包括标量处理器核心和耦合到标量处理器核心的向量协处理器核心。标量处理器核心包括程序存储器接口，标量处理器通过该存储器接口从程序存储器检索指令。指令包括可由标量处理器执行的标量指令和由矢量协处理器核心执行的向量指令。向量协处理器核心包括多个执行单元和向量命令缓冲器。矢量命令缓冲器被配置为对由标量处理器核心传递的矢量指令进行解码，以确定定义指令循环的矢量指令是否已被解码，并且基于确定执行单元中的一个或多个执行指令循环指令循环的所有向量指令都被解码。

3. 发明授权

US08111760B2 Deblocking filters 有权
标题翻译：去块过滤器
公开(公告)号：US08111760B2
公开(公告)日：2012-02-07
申请号：US11560367
申请日：2006-11-16
申请人： Ching-Yu Hung , Ngai-Man Cheung
发明人： Ching-Yu Hung , Ngai-Man Cheung
IPC分类号： H04N7/12
CPC分类号： H04N19/86 , H04N19/117 , H04N19/14 , H04N19/176 , H04N19/182 , H04N19/61 , H04N19/82
摘要： Deblock filtering for Microsoft WMV video decoders partitions the computation so that the deblock filtering operations can be performed on horizontal or vertical stripes or in one pass on oversized macroblocks.
摘要翻译：用于Microsoft WMV视频解码器的去块过滤器对计算进行分块，使得可以在水平或垂直条纹上执行去块滤波操作，或者在超大宏块上进行一次通过。

4. 发明授权

US07797362B2 Parallel architecture for matrix transposition 有权
标题翻译：矩阵转置的并行架构
公开(公告)号：US07797362B2
公开(公告)日：2010-09-14
申请号：US11678130
申请日：2007-02-23
申请人： Nara Won , Ching-Yu Hung
发明人： Nara Won , Ching-Yu Hung
IPC分类号： G06F7/78
CPC分类号： G06F17/18 , G06F9/30032 , G06F9/3004 , G06F9/30098
摘要： An extension to current multiple memory bank video processing architecture is presented. A more powerful memory controller is incorporated, allowing computation of multiple memory addresses at both the input and the output data paths making possible new combinations of reads and writes at the input and output ports. Matrix transposition computations required by the algorithms used in image and video processing are implemented in MAC modules and memory banks. The technique described here can be applied to other parallel processors including future VLIW DSP processors.
摘要翻译：介绍了当前多存储器视频处理架构的扩展。结合了更强大的存储器控制器，允许在输入和输出数据路径上计算多个存储器地址，使输入和输出端口处的读取和写入的新组合成为可能。在图像和视频处理中使用的算法所需的矩阵转置计算在MAC模块和存储器中实现。这里描述的技术可以应用于其他并行处理器，包括将来的VLIW DSP处理器。

5. 发明授权

US07593580B2 Video encoding using parallel processors 有权
标题翻译：使用并行处理器的视频编码
公开(公告)号：US07593580B2
公开(公告)日：2009-09-22
申请号：US10890509
申请日：2004-07-13
申请人： Damon Domke , Youngjun Yoo , Deependra Talla , Ching-Yu Hung
发明人： Damon Domke , Youngjun Yoo , Deependra Talla , Ching-Yu Hung
IPC分类号： G06K9/36
CPC分类号： H04N19/42 , H04N19/436
摘要： A digital video acquisition system including a plurality of image processors (30A; 30B) is disclosed. A CCD imager (22) presents video image data on a bus (video_in) in the form of digital video data, arranged in a sequence of frames. A master image processor (30A) captures and encodes a first group of frames, and instructs a slave image processor (30B) to capture and encode a second group of frames presented by the CCD imager (22) before the encoding of the first group of frames is completed by the master image processor. The master image processor (30A) completes its encoding, and is then available to capture and encode another group of frames in the sequence. Video frames that are encoded by the slave image processor (30B) are transferred to the master image processor (30A), which sequences and stores the transferred encoded frames and also those frames that it encodes in a memory (36A; 38). The parameters of the encoding operation can be dynamically adjusted, for example in response to the nature of the video sequences being captured.
摘要翻译：公开了一种包括多个图像处理器（30A; 30B）的数字视频采集系统。 CCD成像器（22）以数字视频数据的形式在总线（video_in）上呈现以帧序列排列的视频图像数据。主图像处理器（30A）捕获并编码第一组帧，并且指示从属图像处理器（30B）在第一组编码之前捕获并编码由CCD成像器（22）呈现的第二组帧帧由主图像处理器完成。主图像处理器（30A）完成其编码，然后可用于捕获并编码序列中的另一组帧。由从属图像处理器（30B）编码的视频帧被传送到主图像处理器（30A），该主图像处理器将传送的编码帧和其编码的那些帧序列并存储在存储器（36A; 38）中。编码操作的参数可以被动态地调整，例如响应被捕获的视频序列的性质。

6. 发明授权

US07176815B1 Video coding with CABAC 有权
标题翻译：视频编码与CABAC
公开(公告)号：US07176815B1
公开(公告)日：2007-02-13
申请号：US11235586
申请日：2005-09-26
申请人： Ching-Yu Hung , Shraddha Gondkar , Jagadeesh Sankaran
发明人： Ching-Yu Hung , Shraddha Gondkar , Jagadeesh Sankaran
IPC分类号： H03M7/30 , G06K9/36
CPC分类号： H03M7/4006 , H04N19/91
摘要： Context-based adapative binary arithmetic coding (CABAC), as used in video standards such as H.264/AVC, with a renormalization of the interval low value plus range that includes partitioning of the bits of the low value to provide output bits plus low value update without bit-level iterations or aggregation of output bits until a full byte can be output.
摘要翻译：基于上下文的自适应二进制算术编码（CABAC），如H.264 / AVC等视频标准中所使用的，具有区间低值加上范围的重新归一化，其包括低位值的分配以提供输出位加低值更新而不进行位级迭代或输出位的聚合，直到可以输出全字节。

7. 发明申请

US20050053131A1 Video encoding using parallel processors 有权
标题翻译：使用并行处理器的视频编码
公开(公告)号：US20050053131A1
公开(公告)日：2005-03-10
申请号：US10890509
申请日：2004-07-13
申请人： Damon Domke , Youngjun Yoo , Deependra Talla , Ching-Yu Hung
发明人： Damon Domke , Youngjun Yoo , Deependra Talla , Ching-Yu Hung
IPC分类号： G10L19/00 , H04N7/26 , H04N7/12
CPC分类号： H04N19/42 , H04N19/436
摘要： A digital video acquisition system including a plurality of image processors (30A; 30B) is disclosed. A CCD imager (22) presents video image data on a bus (video_in) in the form of digital video data, arranged in a sequence of frames. A master image processor (30A) captures and encodes a first group of frames, and instructs a slave image processor (30B) to capture and encode a second group of frames presented by the CCD imager (22) before the encoding of the first group of frames is completed by the master image processor. The master image processor (30A) completes its encoding, and is then available to capture and encode another group of frames in the sequence. Video frames that are encoded by the slave image processor (30B) are transferred to the master image processor (30A), which sequences and stores the transferred encoded frames and also those frames that it encodes in a memory (36A; 38). The parameters of the encoding operation can be dynamically adjusted, for example in response to the nature of the video sequences being captured.
摘要翻译：公开了一种包括多个图像处理器（30A; 30B）的数字视频采集系统。 CCD成像器（22）以数字视频数据的形式在总线（video_in）上呈现以帧序列排列的视频图像数据。主图像处理器（30A）捕获并编码第一组帧，并且指示从属图像处理器（30B）在第一组编码之前捕获并编码由CCD成像器（22）呈现的第二组帧帧由主图像处理器完成。主图像处理器（30A）完成其编码，然后可用于捕获并编码序列中的另一组帧。由从属图像处理器（30B）编码的视频帧被传送到主图像处理器（30A），该主图像处理器将传送的编码帧和其编码的那些帧序列并存储在存储器（36A; 38）中。编码操作的参数可以被动态地调整，例如响应被捕获的视频序列的性质。

8. 发明申请

US20050052463A1 Sliding data buffering for image processing 有权
标题翻译：滑动数据缓冲用于图像处理
公开(公告)号：US20050052463A1
公开(公告)日：2005-03-10
申请号：US10936342
申请日：2004-09-07
申请人： Ching-Yu Hung
发明人： Ching-Yu Hung
IPC分类号： G06T1/60 , G09G5/39
CPC分类号： G06T1/60
摘要： A method for managing image processing data buffers for processes having overlap input data between iterations includes loading a data buffer with an initial input data array and performing an image data array operation on the input data array. The method repeats the following steps for plural iterations including loading the data buffer with new input data forming a new input data array for a next iteration and performing the input data array operation on the new input data array. The overlap data consists of pixels at an end of each scan line. Loading new input data includes loading pixels following the overlap data for each scan line.
摘要翻译：用于管理具有迭代之间的重叠输入数据的处理的图像处理数据缓冲器的方法包括：使用初始输入数据阵列加载数据缓冲器，并对输入数据阵列执行图像数据阵列操作。该方法重复以下步骤进行多次迭代，包括使用新的输入数据加载数据缓冲器，形成新的输入数据阵列用于下一次迭代，并对新的输入数据阵列执行输入数据阵列操作。重叠数据由每条扫描线末端的像素组成。加载新的输入数据包括在每个扫描线的重叠数据之后加载像素。

9. 发明申请

US20130185544A1 PROCESSOR WITH INSTRUCTION VARIABLE DATA DISTRIBUTION 有权
标题翻译：具有可变数据分配的处理器
公开(公告)号：US20130185544A1
公开(公告)日：2013-07-18
申请号：US13548933
申请日：2012-07-13
申请人： Ching-Yu HUNG , Shinri INAMORI , Jagadeesh SANKARAN , Peter CHANG
发明人： Ching-Yu HUNG , Shinri INAMORI , Jagadeesh SANKARAN , Peter CHANG
IPC分类号： G06F9/30
CPC分类号： G06F15/8053 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30065 , G06F9/30087 , G06F9/30098 , G06F9/3012 , G06F9/3013 , G06F9/3887 , G06F15/76 , G06F15/8007
摘要： A vector processor includes a plurality of execution units arranged in parallel, a register file, and a plurality of load units. The register file includes a plurality of registers coupled to the execution units. Each of the load units is configured to load, in a single transaction, a plurality of the registers with data retrieved from memory. The loaded registers corresponding to different execution units. Each of the load units is configured to distribute the data to the registers in accordance with an instruction selectable distribution. The instruction selectable distribution specifies one of plurality of distributions. Each of the distributions specifies a data sequence that differs from the sequence in which the data is stored in memory.
摘要翻译：矢量处理器包括并行排列的多个执行单元，寄存器堆和多个负载单元。寄存器文件包括耦合到执行单元的多个寄存器。每个负载单元被配置为在单个事务中加载具有从存储器检索的数据的多个寄存器。加载的寄存器对应于不同的执行单元。每个负载单元被配置为根据指令可选择分布将数据分配给寄存器。指令可选择分布指定多个分布中的一个。每个分布都指定与数据存储在存储器中的序列不同的数据序列。

10. 发明申请

US20100168261A1 FOAM AND FABRICATION METHOD THEREOF AND BUFFER MATERIALS COMPRISING THE SAME 审中-公开
标题翻译：泡沫及其制造方法和缓冲材料包括它们
公开(公告)号：US20100168261A1
公开(公告)日：2010-07-01
申请号：US12388472
申请日：2009-02-18
申请人： Ching-Yu Hung , Li-Sheng Teng
发明人： Ching-Yu Hung , Li-Sheng Teng
IPC分类号： C08L3/02 , C08J9/35
CPC分类号： C08J9/102 , C08J9/0061 , C08J9/0085 , C08J2323/16 , C08J2403/00 , C08J2497/00 , C08K3/016 , C08K5/0066 , C08L3/02 , C08L9/10 , C08L23/16 , C08L97/02 , C08L2203/14 , C08L2666/26 , C08L2666/02
摘要： Foam is provided. The foam includes starch, wood flour, a chemical auxiliary and resin, wherein the resin has a weight ratio exceeding 50%. The invention also provides a method for fabricating the foam. The method includes providing a foam raw material including starch, wood flour, a chemical auxiliary and resin, wherein the resin has a weight ratio exceeding 50%, blending the foam raw material and a foaming fluid to form a blend, and performing a foaming process to form foam.
摘要翻译：提供泡沫。泡沫包括淀粉，木粉，化学助剂和树脂，其中树脂的重量比超过50％。本发明还提供一种制造泡沫的方法。该方法包括提供包括淀粉，木粉，化学助剂和树脂的泡沫原料，其中树脂的重量比超过50％，将泡沫原料和发泡流体混合以形成共混物，并进行发泡过程以形成泡沫。

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