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1. 发明申请

US20070210448A1 ELECTROLESS COBALT-CONTAINING LINER FOR MIDDLE-OF-THE-LINE (MOL) APPLICATIONS 审中-公开
标题翻译：用于中间线（MOL）应用的电镀含钴包装线
公开(公告)号：US20070210448A1
公开(公告)日：2007-09-13
申请号：US11308186
申请日：2006-03-10
申请人： Keith Wong , Yun-Yu Wang , Horatio Wildman , Christopher Parks , Chih-Chao Yang
发明人： Keith Wong , Yun-Yu Wang , Horatio Wildman , Christopher Parks , Chih-Chao Yang
IPC分类号： H01L23/48
CPC分类号： H01L23/485 , H01L21/288 , H01L21/76843 , H01L21/76846 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure that includes a Co-containing liner disposed between an oxygen-getter layer and a metal-containing conductive material is provided. The Co-containing liner, the oxygen-getter layer and the metal-containing conductive material form MOL metallurgy where the Co-containing liner replaces a traditional TiN liner. By “Co-containing” is meant that the liner includes elemental Co alone or elemental Co and at least one of P or B. In order to provide better step coverage of the inventive Co-containing liner within a high aspect ratio contact opening, the Co-containing liner is formed via an electroless deposition process.
摘要翻译：提供了包括设置在吸氧剂层和含金属的导电材料之间的含Co衬里的半导体结构。含Co的内衬，吸氧剂层和含金属的导电材料形成MOL冶金，其中含Co衬垫代替了传统的TiN衬里。 “含Co”是指衬垫包括元素Co单体或元素Co以及P或B中的至少一种。为了在高纵横比接触开口内提供本发明的含Co衬垫的更好的台阶覆盖，通过无电镀沉积工艺形成含钴内衬。

2. 发明授权

US07790599B2 Metal cap for interconnect structures 有权
标题翻译：用于互连结构的金属盖
公开(公告)号：US07790599B2
公开(公告)日：2010-09-07
申请号：US11734958
申请日：2007-04-13
申请人： Chih-Chao Yang , Ping-Chuan Wang , Yun-Yu Wang
发明人： Chih-Chao Yang , Ping-Chuan Wang , Yun-Yu Wang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76814 , H01L21/76805 , H01L21/76843 , H01L21/76849
摘要： A structure and method of forming an improved metal cap for interconnect structures is described. The method includes forming an interconnect feature in an upper portion of a first insulating layer; deposing a dielectric capping layer over the interconnect feature and the first insulating layer; depositing a second insulating layer over the dielectric capping layer; etching a portion of the second insulating layer to form a via opening, wherein the via opening exposes a portion of the interconnect feature; bombarding the portion of the interconnect feature for defining a gauging feature in a portion of the interconnect feature; etching the via gauging feature for forming an undercut area adjacent to the interconnect feature and the dielectric capping layer; depositing a noble metal layer, the noble metal layer filling the undercut area of the via gauging feature to form a metal cap; and depositing a metal layer over the metal cap.
摘要翻译：描述了形成用于互连结构的改进的金属帽的结构和方法。该方法包括在第一绝缘层的上部形成互连特征; 在所述互连特征和所述第一绝缘层上方覆盖介电覆盖层; 在所述电介质覆盖层上沉积第二绝缘层; 蚀刻所述第二绝缘层的一部分以形成通孔开口，其中所述通孔开口暴露所述互连特征的一部分; 轰击互连特征的部分以在互连特征的一部分中定义测量特征; 蚀刻通孔测量特征，用于形成邻近互连特征和电介质覆盖层的底切区域; 沉积贵金属层，所述贵金属层填充通孔测量特征的底切区域以形成金属盖; 以及在所述金属盖上沉积金属层。

3. 发明授权

US07569475B2 Interconnect structure having enhanced electromigration reliability and a method of fabricating same 有权
标题翻译：具有增强的电迁移可靠性的互连结构及其制造方法
公开(公告)号：US07569475B2
公开(公告)日：2009-08-04
申请号：US11560044
申请日：2006-11-15
申请人： Chih-Chao Yang , Ping-Chuan Wang , Yun-Yu Wang
发明人： Chih-Chao Yang , Ping-Chuan Wang , Yun-Yu Wang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76847 , H01L23/5226 , H01L23/5283 , H01L23/53223 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure having improved electromigration (EM) reliability is provided. The inventive interconnect structure avoids a circuit dead opening that is caused by EM failure by incorporating a EM preventing liner at least partially within a metal interconnect. In one embodiment, a “U-shaped” EM preventing liner is provided that abuts a diffusion barrier that separates conductive material from the dielectric material. In another embodiment, a space is located between the “U-shaped” EM preventing liner and the diffusion barrier. In yet another embodiment, a horizontal EM liner that abuts the diffusion barrier is provided. In yet a further embodiment, a space exists between the horizontal EM liner and the diffusion barrier.
摘要翻译：提供了具有改进的电迁移（EM）可靠性的互连结构。本发明的互连结构避免了通过将至少部分地在金属互连内部结合EM防止衬垫而由EM故障引起的电路死路。在一个实施例中，提供了一种“U形”防EM衬垫，其与导电材料与电介质材料分离的扩散屏障相邻。在另一个实施例中，空间位于“U形”EM防护衬垫和扩散阻挡层之间。在另一个实施例中，提供了一个与扩散阻挡件相邻的水平EM衬垫。在又一个实施例中，在水平EM衬垫和扩散阻挡层之间存在一个空间。

4. 发明授权

US07494915B2 Back end interconnect with a shaped interface 失效
标题翻译：后端互连与成形接口
公开(公告)号：US07494915B2
公开(公告)日：2009-02-24
申请号：US11463447
申请日：2006-08-09
申请人： Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Mark Hoinkis , Steffen K. Kaldor , Erdem Kaltalioglu , Kaushik A. Kumar , Douglas C. La Tulipe, Jr. , Jochen Schacht , Andrew H. Simon , Terry A. Spooner , Yun-Yu Wang , Clement H. Wann , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Mark Hoinkis , Steffen K. Kaldor , Erdem Kaltalioglu , Kaushik A. Kumar , Douglas C. La Tulipe, Jr. , Jochen Schacht , Andrew H. Simon , Terry A. Spooner , Yun-Yu Wang , Clement H. Wann , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76807 , H01L21/76814 , H01L21/76846 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.
摘要翻译：在集成电路的线的后端中的互连结构通过在锥形孔中去除下互连的顶表面中的材料而形成连续层之间的接触，该去除过程延伸穿过上孔的衬垫，以及沉积向下延伸到锥形孔中的第二衬垫，从而增加接触件的机械强度，从而提高集成电路的整体可靠性。

5. 发明申请

US20060292852A1 BACK END INTERCONNECT WITH A SHAPED INTERFACE 失效
标题翻译：后端互连与形状接口
公开(公告)号：US20060292852A1
公开(公告)日：2006-12-28
申请号：US11463447
申请日：2006-08-09
申请人： Lawrence Clevenger , Andrew Cowley , Timothy Dalton , Mark Hoinkis , Steffen Kaldor , Erdem Kaltalioglu , Kaushik Kumar , Douglas La Tulipe , Jochen Schacht , Andrew Simon , Terry Spooner , Yun-Yu Wang , Clement Wann , Chih-Chao Yang
发明人： Lawrence Clevenger , Andrew Cowley , Timothy Dalton , Mark Hoinkis , Steffen Kaldor , Erdem Kaltalioglu , Kaushik Kumar , Douglas La Tulipe , Jochen Schacht , Andrew Simon , Terry Spooner , Yun-Yu Wang , Clement Wann , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76807 , H01L21/76814 , H01L21/76846 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.
摘要翻译：在集成电路的线的后端中的互连结构通过在锥形孔中去除下互连的顶表面中的材料而形成连续层之间的接触，该去除过程延伸穿过上孔的衬垫，以及沉积向下延伸到锥形孔中的第二衬垫，从而增加接触件的机械强度，从而提高集成电路的整体可靠性。

6. 发明授权

US07122462B2 Back end interconnect with a shaped interface 有权
公开(公告)号：US07122462B2
公开(公告)日：2006-10-17
申请号：US10707122
申请日：2003-11-21
申请人： Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Mark Hoinkis , Steffen K. Kaldor , Erdem Kaltalioglu , Kaushik A. Kumar , Douglas C. La Tulipe, Jr. , Jochen Schacht , Andrew H. Simon , Terry A. Spooner , Yun-Yu Wang , Clement H. Wann , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Mark Hoinkis , Steffen K. Kaldor , Erdem Kaltalioglu , Kaushik A. Kumar , Douglas C. La Tulipe, Jr. , Jochen Schacht , Andrew H. Simon , Terry A. Spooner , Yun-Yu Wang , Clement H. Wann , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76807 , H01L21/76814 , H01L21/76846 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.

7. 发明授权

US07102232B2 Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer 有权
标题翻译：结构以改善顶部CVD低介电常数介电层和电介质顶盖层之间的附着力
公开(公告)号：US07102232B2
公开(公告)日：2006-09-05
申请号：US10827693
申请日：2004-04-19
申请人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Derren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Derren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
IPC分类号： H01L23/52
CPC分类号： H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/02362 , H01L21/31633 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.
摘要翻译：一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合通过在两个电介质层之间引入粘附过渡层来改善N和H。在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。还提供了形成这种结构，特别是粘附过渡层的方法。

8. 发明申请

US20050200024A1 Method to generate porous organic dielectric 失效
标题翻译：生成多孔有机电介质的方法
公开(公告)号：US20050200024A1
公开(公告)日：2005-09-15
申请号：US11125549
申请日：2005-05-10
申请人： Lawrence Clevenger , Stephen Greco , Keith Kwietniak , Soon-Cheon Seo , Chih-Chao Yang , Yun-Yu Wang , Kwong Wong
发明人： Lawrence Clevenger , Stephen Greco , Keith Kwietniak , Soon-Cheon Seo , Chih-Chao Yang , Yun-Yu Wang , Kwong Wong
IPC分类号： H01L21/312 , H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/52 , H01L23/522
CPC分类号： H01L21/76843 , H01L21/76807 , H01L21/76814 , H01L21/7682 , H01L21/76826 , H01L21/76835 , H01L21/76856 , H01L2221/1036
摘要： The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features. The insulator includes pores along surface areas of the insulator that are in contact with the liner and the pores exist only along the surface areas that are in contact with the liner (the liner is not within the pores).
摘要翻译：本发明提供一种形成集成电路结构中的布线层的方法，该集成电路结构形成有机绝缘体，图案化绝缘体，将衬垫沉积在绝缘体上，并将该结构暴露于等离子体，以在绝缘体旁边的区域中形成孔衬垫。衬垫形成得足够薄以允许等离子体穿过衬垫并在绝缘体中形成孔。在等离子体处理期间，等离子体通过衬垫而不影响衬垫。在等离子体处理之后，可以沉积另外的衬里材料。此后，导体被沉积，导体的多余部分从结构中移除，使得导体仅保留在绝缘体的图案化部分内。该方法产生集成电路结构，其具有具有图案化特征的有机绝缘体，衬里图案化特征的衬垫和填充图案化特征的导体。绝缘体包括与绝缘体的表面区域相接触的孔，该孔与衬垫接触，并且孔仅沿着与衬垫接触的表面区域（衬里不在孔内）存在。

9. 发明授权

US06921978B2 Method to generate porous organic dielectric 失效
公开(公告)号：US06921978B2
公开(公告)日：2005-07-26
申请号：US10249799
申请日：2003-05-08
申请人： Lawrence A. Clevenger , Stephen E. Greco , Keith T. Kwietniak , Soon-Cheon Seo , Chih-Chao Yang , Yun-Yu Wang , Kwong H. Wong
发明人： Lawrence A. Clevenger , Stephen E. Greco , Keith T. Kwietniak , Soon-Cheon Seo , Chih-Chao Yang , Yun-Yu Wang , Kwong H. Wong
IPC分类号： H01L21/312 , H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/52 , H01L23/522
CPC分类号： H01L21/76843 , H01L21/76807 , H01L21/76814 , H01L21/7682 , H01L21/76826 , H01L21/76835 , H01L21/76856 , H01L2221/1036
摘要： The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features. The insulator includes pores along surface areas of the insulator that are in contact with the liner and the pores exist only along the surface areas that are in contact with the liner (the liner is not within the pores).

10. 发明授权

US06661097B1 Ti liner for copper interconnect with low-k dielectric 失效
标题翻译：用于低k电介质的铜互连的Ti衬垫
公开(公告)号：US06661097B1
公开(公告)日：2003-12-09
申请号：US10287155
申请日：2002-11-01
申请人： Larry Clevenger , Stanley J. Klepeis , Hsiao-Ling Lu , Jeffrey R. Marino , Andrew Herbert Simon , Yun-Yu Wang , Kwong Hon Wong , Chih-Chao Yang
发明人： Larry Clevenger , Stanley J. Klepeis , Hsiao-Ling Lu , Jeffrey R. Marino , Andrew Herbert Simon , Yun-Yu Wang , Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , H01L21/76846 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： In copper backend integrated circuit technology, advanced technology using low-k organic-based interlayer dielectrics have a problem of carbon contamination that dos not occur in circuits using oxide as dielectric. A composite liner layer for the copper lines uses Ti as the bottom layer, which has the property of gettering carbon and other contaminants. The known problem with Ti of reacting with copper to form a high resistivity compound is avoided by adding a layer of TiN, which isolates the Ti and the copper.
摘要翻译：在铜后端集成电路技术中，使用低k有机基层间电介质的先进技术具有碳污染的问题，在使用氧化物作为电介质的电路中不会发生这种问题。用于铜线的复合衬里层使用Ti作为底层，其具有吸除碳和其它污染物的性质。通过添加一层分离Ti和铜的TiN层，避免了与铜反应形成高电阻率化合物的Ti的已知问题。

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