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1. 发明申请

US20080156987A1 METHOD OF TEM SAMPLE PREPARATION FOR ELECTRON HOLOGRAPHY FOR SEMICONDUCTOR DEVICES 失效
标题翻译：用于半导体器件的电子照相的TEM样品制备方法
公开(公告)号：US20080156987A1
公开(公告)日：2008-07-03
申请号：US11617386
申请日：2006-12-28
申请人： Keith E. Barton , Steven H. Boettcher , John G. Gaudiello , Leon J. Kimball , Yun Yu Wang
发明人： Keith E. Barton , Steven H. Boettcher , John G. Gaudiello , Leon J. Kimball , Yun Yu Wang
IPC分类号： G01N23/04
CPC分类号： G01N1/2806
摘要： A high quality electron microscopy sample suitable for electron holography is prepared by forming markers filled with TEOS oxide and by repeatedly applying multiple coats of an adhesive followed by a relatively low temperature cure after each application. TEOS oxide marker is readily visible during the polish, has a similar polish rate as semiconductor material, and reduces contamination during the sample preparation. The repeated application of adhesives separated by relatively low temperature cures increases the adhesive strength of the adhesive material to the semiconductor material without making it too brittle. This results in an improved control and yield of the sample preparation process.
摘要翻译：适用于电子全息术的高品质电子显微镜样品通过形成填充有TEOS氧化物的标记物，并通过反复施加多层粘合剂，然后在每次涂布之后进行相对低温固化来制备。 TEOS氧化物标记在抛光期间容易看到，具有与半导体材料相似的抛光速率，并且减少样品制备过程中的污染。通过相对低温固化分离的粘合剂的重复施加增加了粘合剂材料对半导体材料的粘合强度，而不会使其变得太脆。这导致样品制备过程的改进的控制和产率。

2. 发明授权

US06440851B1 Method and structure for controlling the interface roughness of cobalt disilicide 失效
标题翻译：控制二硅化钴界面粗糙度的方法和结构
公开(公告)号：US06440851B1
公开(公告)日：2002-08-27
申请号：US09416083
申请日：1999-10-12
申请人： Paul David Agnello , Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Kirk David Peterson , Robert Joseph Purtell , Ronnen Andrew Roy , Jean Louise Jordan-Sweet , Yun Yu Wang
发明人： Paul David Agnello , Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Kirk David Peterson , Robert Joseph Purtell , Ronnen Andrew Roy , Jean Louise Jordan-Sweet , Yun Yu Wang
IPC分类号： H01L2144
CPC分类号： H01L23/485 , H01L21/28518 , H01L2924/0002 , H01L2924/00
摘要： A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additive, over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.
摘要翻译：本文公开了一种制造具有降低的界面粗糙度的电接触以及电接触本身的方法。本发明的方法包括（a）在含硅基材上形成具有式MX的合金层，其中M是选自Co和Ni的金属，X是合金添加剂; （b）任选地在所述合金层上形成任选的氧阻隔层; （c）在足以在所述结构中形成MXSi层的温度下退火所述合金层; （d）除去所述任选的氧气阻挡层和任何剩余的合金层; 以及任选地（e）在足以在所述结构中形成MXSi 2层的温度下退火所述MXSi层。

3. 发明授权

US07208414B2 Method for enhanced uni-directional diffusion of metal and subsequent silicide formation 失效
标题翻译：用于增强金属的单向扩散和随后的硅化物形成的方法
公开(公告)号：US07208414B2
公开(公告)日：2007-04-24
申请号：US10711365
申请日：2004-09-14
申请人： Anthony G. Domenicucci , Bradley P. Jones , Christian Lavoie , Robert J. Purtell , Yun Yu Wang , Kwong Hon Wong
发明人： Anthony G. Domenicucci , Bradley P. Jones , Christian Lavoie , Robert J. Purtell , Yun Yu Wang , Kwong Hon Wong
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L29/665
摘要： The present invention provides a method for enhancing uni-directional diffusion of a metal during silicidation by using a metal-containing silicon alloy in conjunction with a first anneal in which two distinct thermal cycles are performed. The first thermal cycle of the first anneal is performed at a temperature that is capable of enhancing the uni-directional diffusion of metal, e.g., Co and/or Ni, into a Si-containing layer. The first thermal cycle causes an amorphous metal-containing silicide to form. The second thermal cycle is performed at a temperature that converts the amorphous metal-containing silicide into a crystallized metal rich silicide that is substantially non-etchable as compared to the metal-containing silicon alloy layer or a pure metal-containing layer. Following the first anneal, a selective etch is performed to remove any unreacted metal-containing alloy layer from the structure. A second anneal is performed to convert the metal rich silicide phase formed by the two thermal cycles of the first anneal into a metal silicide phase that is in its lowest resistance phase. A metal silicide is provided whose thickness is self-limiting.
摘要翻译：本发明提供了一种通过使用含金属的硅合金与进行两个不同的热循环的第一次退火相结合的方法来增强金属在硅化过程中的单向扩散。第一退火的第一热循环在能够增强金属例如Co和/或Ni的单向扩散到含Si层中的温度下进行。第一热循环导致形成含非晶态金属的硅化物。第二热循环在将含非晶态金属的硅化物转化为与含金属的硅合金层或纯金属含有层相比基本上不可蚀刻的结晶的富含金属的硅化物的温度下进行。在第一退火之后，执行选择性蚀刻以从结构中除去任何未反应的含金属合金层。执行第二退火以将由第一退火的两个热循环形成的富金属硅化物相转换成处于其最低电阻相的金属硅化物相。提供了一种金属硅化物，其厚度是自限制的。

4. 发明授权

US06331486B1 Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy 失效
标题翻译：使用金属锗合金降低金属硅化物的接触电阻的方法和结构
公开(公告)号：US06331486B1
公开(公告)日：2001-12-18
申请号：US09519897
申请日：2000-03-06
申请人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Ronnen Andrew Roy , Yun Yu Wang
发明人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Ronnen Andrew Roy , Yun Yu Wang
IPC分类号： H01L244
CPC分类号： H01L21/28518
摘要： A method of reducing contact resistance of metal silicides to a silicon-containing substrate is provided. The method includes first forming a metal germanium layer over a silicon-containing substrate. An optionally oxygen barrier layer may be formed over the metal germanium layer. Next, the structure containing the metal germanium layer is annealed at a temperature effective in converting at least a portion of the metal germanium layer into a substantially non-etchable metal silicide layer, while forming a Si-Ge interlayer between the substrate and the silicide layer. After annealing, the optional oxygen barrier layer and any remaining metal germanium layer is removed from the substrate.
摘要翻译：提供了一种降低金属硅化物与含硅衬底的接触电阻的方法。该方法包括首先在含硅衬底上形成金属锗层。可以在金属锗层上形成任选的氧阻挡层。接下来，含有金属锗层的结构在有效地将金属锗层的至少一部分转化为基本上不可蚀刻的金属硅化物层的同时，在衬底和硅化物层之间形成Si-Ge中间层的温度下进行退火。在退火之后，从衬底去除可选的氧阻挡层和任何剩余的金属锗层。

5. 发明授权

US06323130B1 Method for self-aligned formation of silicide contacts using metal silicon alloys for limited silicon consumption and for reduction of bridging 有权
标题翻译：使用金属硅合金自发对准形成硅化物接触的方法，用于有限的硅消耗和减少桥接
公开(公告)号：US06323130B1
公开(公告)日：2001-11-27
申请号：US09515033
申请日：2000-03-06
申请人： Stephen Bruce Brodsky , Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Patricia Ann O'Neil , Yun Yu Wang
发明人： Stephen Bruce Brodsky , Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Patricia Ann O'Neil , Yun Yu Wang
IPC分类号： H01L2144
CPC分类号： H01L29/665 , H01L21/28518
摘要： A method of substantially reducing Si consumption and bridging during metal silicide contact formation comprising the steps of: (a) forming a metal silicon alloy layer over a silicon-containing substrate containing an electronic device to be electrically contacted, said silicon in said alloy layer being less than about 30 atomic % and said metal is Co, Ni or mixtures thereof; (b) annealing said metal silicon alloy layer at a temperature of from about 300° to about 500° C. so as to form a metal rich silicide layer that is substantially non-etchable compared to said metal silicon alloy or pure metal; (c) selectively removing any non-reacted metal silicon alloy over non-silicon regions; and (d) annealing said metal rich silicide layer under conditions effective in forming a metal silicide phase that is in its lowest resistance phase. An optional oxygen barrier layer may be formed over the metal silicon alloy layer prior to annealing step (b).
摘要翻译：一种在金属硅化物接触形成期间显着降低Si消耗和桥接的方法，包括以下步骤：（a）在含有电接触的电子器件的含硅衬底上形成金属硅合金层，所述合金层中的所述硅为小于约30原子％，所述金属为Co，Ni或其混合物; （b）在约300℃至约500℃的温度下退火所述金属硅合金层，以便与所述金属硅合金或纯金属相比形成基本不可蚀刻的富金属硅化物层; （c）在非硅区域上有选择地去除任何未反应的金属硅合金; 和（d）在有效形成处于其最低电阻相的金属硅化物相的条件下退火所述富金属硅化物层。可以在退火步骤（b）之前在金属硅合金层上形成任选的氧阻挡层。

6. 发明授权

US06887783B2 Bilayer HDP CVD/PE CVD cap in advance BEOL interconnect structures and method thereof 有权
标题翻译：双层HDP CVD / PE CVD帽预先BEOL互连结构及其方法
公开(公告)号：US06887783B2
公开(公告)日：2005-05-03
申请号：US10650890
申请日：2003-08-28
申请人： Tze-Chiang Chen , Brett H. Engel , John A. Fitzsimmons , Terence Kane , Naftall E. Lustig , Ann McDonald , Vincent McGahay , Soon-Cheon Seo , Anthony K. Stamper , Yun Yu Wang , Erdem Kaltalioglu
发明人： Tze-Chiang Chen , Brett H. Engel , John A. Fitzsimmons , Terence Kane , Naftall E. Lustig , Ann McDonald , Vincent McGahay , Soon-Cheon Seo , Anthony K. Stamper , Yun Yu Wang , Erdem Kaltalioglu
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76834 , H01L21/76801 , H01L21/76807 , H01L21/76832 , H01L23/5226 , H01L23/53228 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structures comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.
摘要翻译：公开了一种先进的后端（BEOL）金属化结构。该结构包括双层扩散阻挡层或盖，其中第一覆盖层由优选通过高密度等离子体化学气相沉积（HDP CVD）工艺沉积的电介质材料形成，并且第二覆盖层由介电材料形成，优选沉积通过等离子体增强化学气相沉积（PE CVD）工艺。还公开了一种用于形成BEOL金属化结构的方法。本发明在包括用于层间电介质（ILD）的低k电介质材料和用于导体的铜的互连结构中是特别有用的。

7. 发明授权

US06878624B1 Pre-anneal of CoSi, to prevent formation of amorphous layer between Ti-O-N and CoSi 失效
标题翻译： CoSi的预退火，以防止在Ti-O-N和CoSi之间形成非晶层
公开(公告)号：US06878624B1
公开(公告)日：2005-04-12
申请号：US10674645
申请日：2003-09-30
申请人： John Bruley , Cyril Cabral, Jr. , Christian Lavoie , Tina J. Wagner , Yun Yu Wang , Horati S. Wildman , Wong Kwong Hon
发明人： John Bruley , Cyril Cabral, Jr. , Christian Lavoie , Tina J. Wagner , Yun Yu Wang , Horati S. Wildman , Wong Kwong Hon
IPC分类号： H01L21/336 , H01L21/44 , H01L21/768 , H01L23/52
CPC分类号： H01L21/76843 , H01L21/28518 , H01L21/76814 , H01L21/76855 , H01L21/76856 , H01L29/665
摘要： The present invention provides a method for forming an interconnect to a cobalt or nickel silicide having a TiN diffusion barrier. The inventive method comprises providing an initial structure having vias to exposed silicide regions positioned on a substrate; annealing the initial structure in a nitrogen-containing ambient, wherein a nitrogen passivation layer is formed atop the exposed silicide region; depositing Ti atop the nitrogen passivation layer; annealing the Ti in a nitrogen-containing ambient to form a TiN diffusion barrier and an amorphous Ti cobalt silicide between the TiN diffusion layer and the cobalt or nickel silicide and depositing an interconnect metal within the vias and atop the TiN diffusion barrier. The nitrogen passivation layer substantially restricts diffusion between the Ti and silicide layers minimizing the amorphous Ti cobalt silicide layer that forms. Therefore, the amorphous Ti cobalt or Ti nickel silicide is restricted to a thickness of less than about 3.0 nm.
摘要翻译：本发明提供一种用于形成具有TiN扩散阻挡层的钴或镍硅化物的互连的方法。本发明的方法包括提供具有通孔的初始结构，以暴露出位于基板上的硅化物区域; 在含氮环境中退火初始结构，其中在暴露的硅化物区域上形成氮钝化层; 在氮钝化层顶上沉积Ti; 在含氮环境中退火Ti以在TiN扩散层和钴或镍硅化物之间形成TiN扩散阻挡层和非晶Ti钴硅化物，并在通孔内和TiN扩散势垒顶上沉积互连金属。氮钝化层基本上限制了Ti和硅化物层之间的扩散，使形成的无定形Ti钴硅化物层最小化。因此，非晶Ti钴或Ti镍硅化物被限制在小于约3.0nm的厚度。

8. 发明授权

US06703641B2 Structure for detecting charging effects in device processing 失效
标题翻译：用于检测设备处理中的充电效果的结构
公开(公告)号：US06703641B2
公开(公告)日：2004-03-09
申请号：US09991507
申请日：2001-11-16
申请人： Terence L. Kane , Yun Yu Wang , Malcolm P. Cambra, Jr. , Michael P. Tenney
发明人： Terence L. Kane , Yun Yu Wang , Malcolm P. Cambra, Jr. , Michael P. Tenney
IPC分类号： H01L2358
CPC分类号： H01L22/34 , H01L2924/0002 , Y10S257/903 , H01L2924/00
摘要： A semiconductor device monitor structure is described which can detect localized defects due to floating-body effects, particularly on SOI device wafers. The monitor structure includes a plurality of cells containing PFET or NFET devices, disposed at a perimeter of the structure which is bordered by an insulating region such as shallow trench isolation (STI). Each cell includes polysilicon gate structures having a characteristic spacing given by a first distance, and a portion extending beyond the perimeter a second distance. The cells are constructed in accordance with progressively varying ground rules, so that the first distance and second distance are non-uniform between cells. The cells may be bit fail mapped for single-cell failures, thereby enabling detection of localized defects due to floating-body effects.
摘要翻译：描述了可以检测由于浮体效应引起的局部缺陷的半导体器件监视器结构，特别是在SOI器件晶片上。监视器结构包括多个包含PFET或NFET器件的单元，该单元设置在由诸如浅沟槽隔离（STI）之类的绝缘区域界定的结构的周边。每个单元包括具有由第一距离给出的特征间隔的多晶硅栅极结构，以及延伸超过周边第二距离的部分。细胞根据逐渐变化的基本规则构造，使得细胞之间的第一距离和第二距离是不均匀的。这些单元可能被单位故障映射成位故障，从而能够检测由于浮体效应引起的局部缺陷。

9. 发明授权

US06593660B2 Plasma treatment to enhance inorganic dielectric adhesion to copper 有权
标题翻译：等离子体处理以增强与铜的无机介电粘附
公开(公告)号：US06593660B2
公开(公告)日：2003-07-15
申请号：US09866937
申请日：2001-05-29
申请人： Leena P. Buchwalter , Barbara Luther , Paul D. Agnello , John P. Hummel , Terence Lawrence Kane , Dirk Karl Manger , Paul Stephen McLaughlin , Anthony Kendall Stamper , Yun Yu Wang
发明人： Leena P. Buchwalter , Barbara Luther , Paul D. Agnello , John P. Hummel , Terence Lawrence Kane , Dirk Karl Manger , Paul Stephen McLaughlin , Anthony Kendall Stamper , Yun Yu Wang
IPC分类号： H01L2348
CPC分类号： H01L21/3185 , H01L21/0445 , H01L21/76801 , H01L21/76807 , H01L21/76834
摘要： The present invention utilizes a reducing plasma treatment step to enhance the adhesion of a subsequently deposited inorganic barrier film to a copper wire or via present in a semiconductor interconnect structure such as a dual damascene structure. Interconnect structure including a material layer of Cu, Si and O, as essential elements, is formed between said copper wire or via and the inorganic barrier film.
摘要翻译：本发明利用还原等离子体处理步骤来增强后续沉积的无机阻挡膜对铜线的粘附，或通过存在于诸如双镶嵌结构的半导体互连结构中。在所述铜线或通孔与无机阻挡膜之间形成包括作为必需元素的Cu，Si和O的材料层的互连结构。

10. 发明授权

US07081676B2 Structure for controlling the interface roughness of cobalt disilicide 有权
标题翻译：控制二硅化钴界面粗糙度的结构
公开(公告)号：US07081676B2
公开(公告)日：2006-07-25
申请号：US10691299
申请日：2003-10-22
申请人： Paul David Agnello , Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Kirk David Peterson , Robert Joseph Purtell , Ronnen Andrew Roy , Jean Louise Jordan-Sweet , Yun Yu Wang
发明人： Paul David Agnello , Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Kirk David Peterson , Robert Joseph Purtell , Ronnen Andrew Roy , Jean Louise Jordan-Sweet , Yun Yu Wang
IPC分类号： H01L29/40 , H01L23/48 , H01L23/52
CPC分类号： H01L23/485 , H01L21/28518 , H01L2924/0002 , H01L2924/00
摘要： A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additive, over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.
摘要翻译：本文公开了一种制造具有降低的界面粗糙度的电接触以及电接触本身的方法。本发明的方法包括（a）在含硅基材上形成具有式MX的合金层，其中M是选自Co和Ni的金属，X是合金添加剂; （b）任选地在所述合金层上形成任选的氧阻隔层; （c）在足以在所述结构中形成MXSi层的温度下退火所述合金层; （d）除去所述任选的氧气阻挡层和任何剩余的合金层; 以及任选地（e）在足以在所述结构中形成MXSi 2层的温度下退火所述MXSi层。

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