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1. 发明授权

US5366814A Copper foil for printed circuits and process for producing the same 失效
标题翻译：印刷电路用铜箔及其制造方法
公开(公告)号：US5366814A
公开(公告)日：1994-11-22
申请号：US153327
申请日：1993-11-16
申请人： Keisuke Yamanishi , Hideo Oshima , Kazuhiko Sakaguchi
发明人： Keisuke Yamanishi , Hideo Oshima , Kazuhiko Sakaguchi
IPC分类号： C25D7/06 , C25F3/02 , H05K1/09 , H05K3/38 , B32B15/20
CPC分类号： H05K3/384 , H05K2201/0355 , H05K2203/0307 , H05K2203/0723 , Y10S428/935 , Y10T428/12438 , Y10T428/12472 , Y10T428/1291 , Y10T428/12993
摘要： A copper foil for printed circuits has a roughened layer formed on the side of the foil to be bonded to a base, the roughened layer consisting of a number of protuberant copper electrodeposits containing chromium tungsten or both. It may also have a copper plating layer covering the roughened layer and a treatment layer covering the copper plating layer and formed of either a metal selected from the group consisting of copper, chromium, nickel, iron, cobalt, and zinc, or an alloy of two or more such metals. When necessary, the copper foil may contain an anticorrosive layer including various chromate treated layers further formed on the treatment layer. The copper foil is produced by electrolyzing a raw foil as a cathode in an acidic copper electrolytic bath at a current density close to the critical density, thereby forming the roughened layer, the electrolytic bath containing 0.001-5 g/l of chromium ion tungsten ion or both. The roughened layer is electrolytically overcoated with the treatment layer following the formation of a copper plating layer, which, when necessary, is anti-corrosively treated.
摘要翻译：用于印刷电路的铜箔具有形成在箔的与基底结合的一侧上的粗糙层，该粗糙层由许多包含铬钨或两者的突出铜电沉积物组成。还可以具有覆盖粗糙层的铜镀层和覆盖铜镀层的处理层，并且由选自铜，铬，镍，铁，钴和锌的金属形成，或者由两种或更多种这样的金属。必要时，铜箔可以含有在处理层上进一步形成的各种铬酸盐处理层的防腐层。铜箔通过在酸性铜电解槽中以接近临界密度的电流密度电解原料箔作为阴极，由此形成粗糙层，电解槽含有0.001-5g / l的铬离子钨离子或两者。在形成镀铜层之后，用处理层对粗化层进行电解过涂层，当需要时，其被抗腐蚀处理。

2. 发明授权

US5456817A Surface treatment method of a copper foil for printed circuits 失效
标题翻译：印刷电路用铜箔的表面处理方法
公开(公告)号：US5456817A
公开(公告)日：1995-10-10
申请号：US327138
申请日：1994-10-21
申请人： Eiji Hino , Keisuke Yamanishi , Kazuhiko Sakaguchi
发明人： Eiji Hino , Keisuke Yamanishi , Kazuhiko Sakaguchi
IPC分类号： C23C22/24 , C25D11/38 , H05K3/06 , H05K3/24 , H05K3/38 , C25D3/56 , H05K1/09
CPC分类号： H05K3/244 , C23C22/24 , C25D11/38 , H05K3/384 , H05K2201/0355 , H05K2203/0723 , H05K3/064 , Y10S205/92
摘要： There is disclosed a treating process whereby the thermal oxidation resistance on the shiny side of a copper foil is enhanced so that the shiny side will not discolor on heating to higher temperatures than usual, without impairing the foil's solder wettability, adhesion to resist, and other properties. A Zn-Ni alloy layer which comprises 50-97 wt % Zn and 3-50 wt % Ni or a Zn-Co alloy layer which comprises 50-97 wt % Zn and 3-50 wt % Co is formed on the shiny side of a copper foil at a deposition quantity of 100-500 .mu.g/dm.sup.2 and then the alloy surface is treated for Cr-base corrosion-preventive coating. The Cr-base corrosion-preventive treatment comprises (1) a treatment for forming a coating film of chromium oxide alone, (2) a treatment for forming a mixed coating film of chromium oxide and zinc and/or zinc oxide or (1)+(2). The roughened side of the copper foil may be treated to form thereon a layer of single metal or alloy of two or more metals chosen from among Cu, Cr, Ni, Fe, Co, and Zn. The shiny side does not cause discoloration upon exposure to high-temperature conditions of 240.degree. C. for 30 minutes or 270.degree. C. for 10 minutes.
摘要翻译：公开了一种处理方法，其中铜箔的光泽面上的耐热氧化性提高，使得光泽面在加热时不会比通常更高的温度变色，而不损害箔的焊料润湿性，与抗蚀剂的粘附性等属性。包含50-97重量％Zn和3-50重量％Ni的Zn-Ni合金层或包含50-97重量％Zn和3-50重量％Co的Zn-Co合金层形成在沉积量为100-500g / dm2的铜箔，然后将合金表面处理用于Cr基防腐涂层。 Cr基防腐处理包括（1）单独形成氧化铬的涂膜的处理，（2）形成氧化铬和锌和/或氧化锌的混合涂膜的处理或（1）+ （2）。可以对铜箔的粗糙面进行处理，在其上形成选自Cu，Cr，Ni，Fe，Co和Zn中的两种或更多种金属的单一金属或合金层。闪光的一面在240℃的高温条件下暴露30分钟或270℃10分钟时不会变色。

3. 发明授权

US5389446A Copper foil for printed circuits 失效
标题翻译：铜箔用于印刷电路
公开(公告)号：US5389446A
公开(公告)日：1995-02-14
申请号：US17587
申请日：1993-02-16
申请人： Keisuke Yamanishi , Kazuhiko Sakaguchi
发明人： Keisuke Yamanishi , Kazuhiko Sakaguchi
IPC分类号： C25D7/00 , B32B15/08 , C25D3/56 , C25D11/38 , C25D15/02 , H05K3/06 , H05K3/24 , H05K3/38 , C23C16/06
CPC分类号： C25D3/56 , H05K3/384 , H05K2201/0355 , H05K2203/0723 , H05K3/064 , H05K3/244 , H05K3/382 , Y10T428/12646 , Y10T428/12778 , Y10T428/12792 , Y10T428/1291 , Y10T428/12917
摘要： There is provided a copper foil for printed circuits characterized by having a coating layer which contains zinc and zinc oxide, chromium oxide and nickel, and either or both of zinc and zinc oxide at least on the shiny side of a copper foil. The coating layer is formed by electroplating using a plating solution which contains either or both of zinc salt and zinc oxide, chromic salt and nickel salt. This copper foil resists discoloration upon exposure to high-temperature conditions of 180.degree. C. for 30 minutes. Resist adhesion is also good. The amounts of deposits are preferably 60 to 80 .mu.g Zn, 30 to 40 .mu.g Cr and 5 to 20 .mu.g Ni per dm.sup.2. The matt side of the copper foil may be treated to form thereon a single metal layer or alloy layer of one or more metals chosen from among Cu, Cr, Ni, Fe, Co, and Zn. The copper foil is suited for the fabrication of printed circuits with fine circuit patterns.
摘要翻译：提供一种用于印刷电路的铜箔，其特征在于至少在铜箔的光泽面上具有包含锌和氧化锌，氧化铬和镍以及锌和氧化锌中的任一种或两者的涂层。通过使用含有锌盐和氧化锌，铬盐和镍盐中的任一种或两者的镀液进行电镀而形成涂层。该铜箔在暴露于180℃的高温条件下抵抗变色30分钟。抵抗附着力也不错。沉积物的量优选为60〜80μgZn，30〜40g Cr，5〜20g Ni / dm 2。可以对铜箔的无光泽侧进行处理以形成选自Cu，Cr，Ni，Fe，Co和Zn中的一种或多种金属的单一金属层或合金层。铜箔适用于制造具有精细电路图案的印刷电路。

4. 发明申请

US20120012463A1 Method of Roughening Rolled Copper or Copper Alloy Foil 有权
标题翻译：粗轧铜或铜合金箔的方法
公开(公告)号：US20120012463A1
公开(公告)日：2012-01-19
申请号：US13243187
申请日：2011-09-23
申请人： Yousuke Kobayashi , Atsushi Miki , Keisuke Yamanishi
发明人： Yousuke Kobayashi , Atsushi Miki , Keisuke Yamanishi
IPC分类号： C25D15/00
CPC分类号： H05K3/384 , C22C9/00 , C22C9/02 , C22C9/04 , C22C9/06 , C25D3/38 , C25D5/10 , C25D7/0614 , C25D7/0692 , H05K2201/0355 , H05K2203/0307 , H05K2203/0723 , Y10T428/12014 , Y10T428/12063 , Y10T428/12181 , Y10T428/12431 , Y10T428/12438 , Y10T428/12903 , Y10T428/1291 , Y10T428/12993
摘要： A rolled copper or copper alloy foil having a roughened surface formed of fine copper particles is obtained by subjecting a rolled foil to roughening plating with a plating bath containing copper sulfate (Cu equivalent of 1 to 50 g/L), 1 to 150 g/L of sulfuric acid, and one or more additives selected among sodium octyl sulfate, sodium decyl sulfate, and sodium dodecyl sulfate under the conditions of temperature of 20 to 50° C. and current density of 10 to 100 A/dm2. The foil has reduced craters, which are defects unique to rolled foils having a roughened surface, has high strength, adhesive strength with the resin layer, acid resistance and anti-tin plating solution properties, high peel strength, favorable etching properties and gloss level, and is suitable for producing a flexible printed wiring board capable of bearing a fine wiring pattern. A method of roughening the rolled foil is also provided.
摘要翻译：通过使用含有硫酸铜（Cu当量1〜50g / L），1〜150g / L的电镀液对轧制箔进行粗糙化处理，得到具有由细铜颗粒形成的粗糙面的轧制铜或铜合金箔， L的硫酸，以及一种或多种选自辛基硫酸钠，癸基硫酸钠和十二烷基硫酸钠的添加剂，其温度为20〜50℃，电流密度为10〜100A / dm 2。箔具有减少的凹坑，这是具有粗糙表面的轧制箔特有的缺陷，具有高强度，与树脂层的粘合强度，耐酸性和抗锡电镀溶液性能，高剥离强度，良好的蚀刻性能和光泽度，并且适合于制造能够承受精细布线图案的柔性印刷线路板。还提供了粗糙化轧制箔的方法。

5. 发明申请

US20110300401A1 Rolled Copper Foil or Electrolytic Copper Foil for Electronic Circuit, and Method of Forming Electronic Circuit using same 审中-公开
标题翻译：用于电子电路的轧制铜箔或电解铜箔，以及使用其形成电子电路的方法
公开(公告)号：US20110300401A1
公开(公告)日：2011-12-08
申请号：US13146574
申请日：2010-01-21
申请人： Keisuke Yamanishi , Kengo Kaminaga , Ryo Fukuchi
发明人： Keisuke Yamanishi , Kengo Kaminaga , Ryo Fukuchi
IPC分类号： B32B15/01 , H05K3/00
CPC分类号： H05K1/09 , B32B15/018 , C23C26/00 , C23C28/021 , C23C28/023 , C23C28/025 , C23C30/00 , C23F1/18 , H05K3/0073 , H05K3/06 , H05K2201/0338 , H05K2201/0355 , Y10T428/12438
摘要： A rolled copper foil or electrolytic copper foil for an electronic circuit to be used for forming a circuit by etching, characterized in comprising a layer of metal of one or more types among a platinum group, gold and silver with an etching rate that is lower than the copper formed on an etching surface side of the rolled copper foil or the electrolytic copper foil, or alternatively comprising a layer of an alloy having the above-described metal as its main component. This invention aims to achieve the following upon forming a circuit by etching a copper foil of a copper clad laminate; specifically, to prevent sagging caused by the etching; to form a uniform circuit of the intended circuit width; to shorten the time of forming a circuit by etching as much as possible; to improve the etching properties in pattern etching; and to prevent the occurrence of short circuits and defects in the circuit width.
摘要翻译：一种用于通过蚀刻形成电路的电子电路用的卷绕铜箔或电解铜箔，其特征在于，在铂族金，金和银中含有一种或多种类型的金属，其蚀刻速率低于形成在轧制铜箔或电解铜箔的蚀刻表面侧上的铜，或者可选地包括具有上述金属作为其主要成分的合金层。本发明的目的是通过蚀刻覆铜层压板的铜箔来形成电路，实现以下目的：具体地，为了防止蚀刻引起的下垂; 形成预期电路宽度的均匀电路; 通过蚀刻尽可能地缩短形成电路的时间; 以提高图案蚀刻中的蚀刻性能; 并防止电路宽度短路和缺陷的发生。

6. 发明申请

US20110284496A1 Method of Forming Electronic Circuit 失效
标题翻译：电子电路形成方法
公开(公告)号：US20110284496A1
公开(公告)日：2011-11-24
申请号：US13141753
申请日：2009-12-22
申请人： Keisuke Yamanishi , Kengo Kaminaga , Ryo Fukuchi
发明人： Keisuke Yamanishi , Kengo Kaminaga , Ryo Fukuchi
IPC分类号： H05K3/00
CPC分类号： C23F1/02 , B32B15/08 , B32B15/20 , B32B2307/406 , B32B2307/50 , B32B2307/732 , B32B2457/08 , C23C22/05 , C23F1/14 , C25D3/562 , C25D5/022 , C25D5/12 , C25D5/48 , C25D7/0614 , H05K3/06 , H05K3/067 , H05K3/384 , H05K2201/0338 , H05K2201/0355 , H05K2203/0723
摘要： Provided is a method of forming an electronic circuit, wherein a nickel or nickel alloy layer is formed on an etching side of a rolled copper foil or an electrolytic copper foil, the rolled copper foil or the electrolytic copper foil is bonded to a resin substrate to obtain a copper-clad laminate, a resist pattern for forming a circuit is subsequently applied on the copper foil, any unwanted portion of the copper foil and the nickel or nickel alloy layer of the copper-clad laminate other than the portion to which the resist pattern was applied is removed using an etching solution of an aqueous ferric chloride, the resist is further removed, and soft etching is additionally performed in order to remove the remnant nickel or nickel alloy layer and thereby form a circuit in which the space between copper circuit lines is of a width that is double or more from the thickness of copper. This invention aims to form a circuit with a uniform circuit width, improve the etching properties in pattern etching, and prevent the occurrence of short circuits and defects in the circuit width.
摘要翻译：提供一种形成电子电路的方法，其中在轧制的铜箔或电解铜箔的蚀刻侧上形成镍或镍合金层，将轧制的铜箔或电解铜箔结合到树脂基板上得到覆铜层压板，随后在铜箔上涂覆用于形成电路的抗蚀剂图案，铜箔的不需要部分和覆铜层压板的镍或镍合金层除了抗蚀剂的部分使用氯化铁水溶液的蚀刻溶液除去图案，进一步除去抗蚀剂，另外进行软蚀刻以除去残留的镍或镍合金层，从而形成电路，其中铜电路线的宽度是铜的厚度的两倍或更多。本发明旨在形成具有均匀电路宽度的电路，提高图案蚀刻中的蚀刻性能，并且防止电路宽度中的短路和缺陷的发生。

7. 发明申请

US20130071652A1 LAMINATE FOR FLEXIBLE WIRING 审中-公开
标题翻译：柔性布线层压板
公开(公告)号：US20130071652A1
公开(公告)日：2013-03-21
申请号：US13643626
申请日：2011-04-18
申请人： Keisuke Yamanishi , Hideta Arai , Atsushi Miki
发明人： Keisuke Yamanishi , Hideta Arai , Atsushi Miki
IPC分类号： B32B15/08 , B32B5/00
CPC分类号： B32B15/08 , B32B5/00 , B32B15/20 , C22C9/00 , C25D5/02 , C25D7/0607 , H05K1/09 , H05K3/022 , H05K2201/0154 , H05K2201/0355 , Y10T428/265 , Y10T428/31678
摘要： A laminate for flexible wiring in which copper plating is entirely or locally applied on a copper foil that is cladded on an insulating resin substrate, characterized in that a ratio A=[(200)/{(111)+(200)+(220)+(311)}]×100, i.e. a ratio of an area intensity of a peak in the X-ray diffraction of the copper plating surface is more than 90. The present invention can provide the laminate for flexible wiring in which copper plating is entirely or locally applied on a copper foil cladded on an insulating resin substrate, characterized in having particularly high bendability and enables the formation of fine patterns, namely, high dense patterns of wiring.
摘要翻译：一种用于柔性布线的层压板，其中铜镀层完全或局部施加在包覆在绝缘树脂基板上的铜箔上，其特征在于：A = [（200）/ {（111）+（200）+（220））+（311）}]×100，即镀铜表面的X射线衍射中的峰面积强度比大于90.本发明可以提供用于柔性布线的层压体，其中镀铜完全或局部施加在包覆在绝缘树脂基板上的铜箔上，其特征在于具有特别高的弯曲性，并且能够形成精细图案，即高密集布线图案。

8. 发明申请

US20110293960A1 Rolled Copper Foil or Electrolytic Copper Foil for Electronic Circuit, and Method of Forming Electronic Circuit using same 失效
标题翻译：用于电子电路的轧制铜箔或电解铜箔，以及使用其形成电子电路的方法
公开(公告)号：US20110293960A1
公开(公告)日：2011-12-01
申请号：US13141995
申请日：2009-12-22
申请人： Keisuke Yamanishi , Kengo Kaminaga , Ryo Fukuchi
发明人： Keisuke Yamanishi , Kengo Kaminaga , Ryo Fukuchi
IPC分类号： B32B15/20 , H05K3/00
CPC分类号： C23C30/00 , B32B15/01 , B32B15/20 , B32B2307/306 , B32B2307/406 , B32B2307/50 , B32B2307/732 , B32B2457/08 , C22C9/00 , C23C22/05 , C23F1/02 , C25D1/04 , C25D5/022 , C25D5/12 , C25D7/0614 , H05K3/06 , H05K3/067 , H05K3/384 , H05K2201/0338 , H05K2201/0355 , H05K2203/0723 , Y10T428/12438 , Y10T428/12514 , Y10T428/12569 , Y10T428/12583 , Y10T428/1259 , Y10T428/12611 , Y10T428/1266 , Y10T428/12792 , Y10T428/12847 , Y10T428/12861 , Y10T428/1291 , Y10T428/12944 , Y10T428/273
摘要： Provided is a rolled copper foil or electrolytic copper foil for an electronic circuit to be used for forming a circuit by etching, wherein the copper foil comprises a heat resistance layer composed of zinc or zinc alloy or its oxide formed on an etching side of the rolled copper foil or electrolytic copper foil, and a layer of nickel or nickel alloy, which is a metal or alloy with a lower etching rate than copper, formed on the heat resistance layer. This invention aims to prevent sagging caused by the etching, to form a uniform circuit having the intended circuit width, and to shorten the time of forming a circuit by etching as much as possible, when forming a circuit by etching a copper foil of the copper-clad laminate; and also aims to make the thickness of the nickel or nickel alloy layer as thin as possible, to inhibit oxidation when exposed to heat, to prevent tarnish (discoloration) known as “YAKE”, to improve the etching properties in pattern etching, and to prevent the occurrence of short circuits and defects in the circuit width.
摘要翻译：提供一种用于通过蚀刻形成电路的电子电路的卷绕铜箔或电解铜箔，其中铜箔包括由锌或锌合金构成的耐热层或其在轧制的蚀刻侧上形成的氧化物铜箔或电解铜箔，和形成在耐热层上的，具有比铜蚀刻速率低的金属或合金的镍或镍合金层。本发明旨在防止蚀刻引起的下垂，形成具有预期电路宽度的均匀电路，并且通过蚀刻形成电路时可尽可能地缩短形成电路的时间，当通过蚀刻铜箔的铜箔单层层压板并且还旨在使镍或镍合金层的厚度尽可能薄，以防止暴露于热时的氧化，以防止称为“YAKE”的变色（变色），以改善图案蚀刻中的蚀刻性能，并且防止电路宽度短路和缺陷的发生。

9. 发明授权

US08357307B2 Method of forming electronic circuit 失效
标题翻译：电子电路形成方法
公开(公告)号：US08357307B2
公开(公告)日：2013-01-22
申请号：US13141753
申请日：2009-12-22
申请人： Keisuke Yamanishi , Kengo Kaminaga , Ryo Fukuchi
发明人： Keisuke Yamanishi , Kengo Kaminaga , Ryo Fukuchi
IPC分类号： H01B13/00
CPC分类号： C23F1/02 , B32B15/08 , B32B15/20 , B32B2307/406 , B32B2307/50 , B32B2307/732 , B32B2457/08 , C23C22/05 , C23F1/14 , C25D3/562 , C25D5/022 , C25D5/12 , C25D5/48 , C25D7/0614 , H05K3/06 , H05K3/067 , H05K3/384 , H05K2201/0338 , H05K2201/0355 , H05K2203/0723
摘要： Provided is a method of forming an electronic circuit, wherein a nickel or nickel alloy layer is formed on an etching side of a rolled copper foil or an electrolytic copper foil, the rolled copper foil or the electrolytic copper foil is bonded to a resin substrate to obtain a copper-clad laminate, a resist pattern for forming a circuit is subsequently applied on the copper foil, any unwanted portion of the copper foil and the nickel or nickel alloy layer of the copper-clad laminate other than the portion to which the resist pattern was applied is removed using an etching solution of an aqueous ferric chloride, the resist is further removed, and soft etching is additionally performed in order to remove the remnant nickel or nickel alloy layer and thereby form a circuit in which the space between copper circuit lines is of a width that is double or more from the thickness of copper. This invention aims to form a circuit with a uniform circuit width, improve the etching properties in pattern etching, and prevent the occurrence of short circuits and defects in the circuit width.
摘要翻译：提供一种形成电子电路的方法，其中在轧制的铜箔或电解铜箔的蚀刻侧上形成镍或镍合金层，将轧制的铜箔或电解铜箔结合到树脂基板上得到覆铜层压板，随后在铜箔上涂覆用于形成电路的抗蚀剂图案，铜箔的不需要部分和覆铜层压板的镍或镍合金层除了抗蚀剂的部分使用氯化铁水溶液的蚀刻溶液除去图案，进一步除去抗蚀剂，另外进行软蚀刻以除去残留的镍或镍合金层，从而形成电路，其中铜电路线的宽度是铜的厚度的两倍或更多。本发明旨在形成具有均匀电路宽度的电路，提高图案蚀刻中的蚀刻性能，并且防止电路宽度中的短路和缺陷的发生。

10. 发明申请

US20110297641A1 Rolled Copper Foil or Electrolytic Copper Foil for Electronic Circuit, and Method of Forming Electronic Circuit using same 有权
标题翻译：用于电子电路的轧制铜箔或电解铜箔，以及使用其形成电子电路的方法
公开(公告)号：US20110297641A1
公开(公告)日：2011-12-08
申请号：US13142002
申请日：2009-12-22
申请人： Keisuke Yamanishi , Kengo Kaminaga , Ryo Fukuchi
发明人： Keisuke Yamanishi , Kengo Kaminaga , Ryo Fukuchi
IPC分类号： H05K3/00 , B32B15/01 , B32B15/20 , B32B15/04
CPC分类号： C23F1/02 , B32B15/01 , B32B15/018 , C22C9/00 , C23C22/05 , C23C28/00 , C23C28/021 , C23C28/023 , C23C28/025 , C23C28/321 , C23C28/322 , C23C28/3225 , C23C28/345 , C25D1/04 , C25D5/022 , C25D5/12 , C25D7/0614 , H05K1/09 , H05K3/06 , H05K3/067 , H05K3/384 , H05K2201/0338 , H05K2201/0355 , H05K2203/0723 , Y10T428/12438 , Y10T428/12493 , Y10T428/12514 , Y10T428/12535 , Y10T428/12792 , Y10T428/12861 , Y10T428/12882 , Y10T428/1291 , Y10T428/24917
摘要： Provided is a rolled copper foil or electrolytic copper foil for an electronic circuit to be used for forming a circuit by etching, wherein the copper foil comprises a nickel or nickel alloy layer with a lower etching rate than copper formed on an etching side of the rolled copper foil or electrolytic copper foil, and a heat resistance layer composed of zinc or zinc alloy or its oxide formed on the nickel or nickel alloy layer. This invention aims to prevent sagging caused by the etching, to form a uniform circuit having the intended circuit width, and to shorten the time of forming a circuit by etching as much as possible, when forming a circuit by etching a copper foil of the copper-clad laminate; and also aims to make the thickness of the nickel or nickel alloy layer as thin as possible, to inhibit oxidation when exposed to heat, to prevent tarnish (discoloration) known as “YAKS”, to improve the etching properties in pattern etching, and to prevent the occurrence of short circuits and defects in the circuit width.
摘要翻译：提供一种用于通过蚀刻形成电路的电子电路的卷绕铜箔或电解铜箔，其中铜箔包括镍或镍合金层，其蚀刻速率低于在轧制的蚀刻侧上形成的铜铜箔或电解铜箔，以及由镍或镍合金层上形成的锌或锌合金或其氧化物构成的耐热层。本发明旨在防止蚀刻引起的下垂，形成具有预期电路宽度的均匀电路，并且通过蚀刻形成电路时可尽可能地缩短形成电路的时间，当通过蚀刻铜箔的铜箔单层层压板并且还旨在使镍或镍合金层的厚度尽可能薄，以防止暴露于热时的氧化，以防止称为“YAKS”的变色（变色），以改善图案蚀刻中的蚀刻性能，并且防止电路宽度短路和缺陷的发生。

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