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1. 发明申请

US20100239024A1 IMAGE DECODING DEVICE AND IMAGE DECODING METHOD 有权
标题翻译：图像解码设备和图像解码方法
公开(公告)号：US20100239024A1
公开(公告)日：2010-09-23
申请号：US12743033
申请日：2008-11-14
申请人： Keishi Chikamura , Takashi Hashimoto
发明人： Keishi Chikamura , Takashi Hashimoto
IPC分类号： H04N7/12
CPC分类号： H04N19/436 , H04N19/44 , H04N19/51 , H04N19/52 , H04N19/61
摘要： To decode coded pictures each of which has dependencies within the picture, using conventional decoding circuits and without deteriorating the efficiency in parallel processing.An image decoding device (100) includes: a stream segmentation unit (110) which segments a bit stream such that each of the coded pictures are segmented into two areas; and decoding processing units (120, 130) each of which decodes a corresponding one of the two segmented bit streams. The respective decoding processing units (120, 130) include: decoding units (123, 133) each of which generates decoded data including pixel data and control data; transfer determination units (124, 134) each of which determines whether or not the decoded data is referred to in another one of the processing units; data transfer units (125, 135) each of which transfers decoded data to the other processing unit; and decoding determination units (122, 132) each of which determines whether or not the decoded data to be referred to has been obtained. Each of the decoding units (123, 133) decodes a corresponding one of the segmented bit streams when reference decoded data has been obtained.
摘要翻译：为了解码每个图像中具有依赖性的编码图像，使用传统的解码电路并且不降低并行处理的效率。图像解码装置（100）包括：流分割单元（110），其分割位流，使得每个编码图像被分割成两个区域; 以及解码处理单元（120,130），每个解码处理单元解码两个分段比特流中的对应的一个。相应的解码处理单元（120,130）包括：解码单元（123,133），每个解码单元生成包括像素数据和控制数据的解码数据; 转移确定单元（124,134），每个确定单元确定在另一个处理单元中是否参考解码数据; 数据传送单元（125,135），每个数据传送单元将解码的数据传送到另一个处理单元; 以及解码确定单元（122,132），每个解码确定单元确定是否已经获得了要被提及的解码数据。当已经获得参考解码数据时，解码单元（123,133）中的每一个解码对应的一个分段比特流。

2. 发明授权

US08565315B2 Image decoding device and image decoding method 有权
标题翻译：图像解码装置和图像解码方法
公开(公告)号：US08565315B2
公开(公告)日：2013-10-22
申请号：US12743033
申请日：2008-11-14
申请人： Keishi Chikamura , Takashi Hashimoto
发明人： Keishi Chikamura , Takashi Hashimoto
IPC分类号： H04N7/12 , H04N11/02
CPC分类号： H04N19/436 , H04N19/44 , H04N19/51 , H04N19/52 , H04N19/61
摘要： To decode coded pictures each of which has dependencies within the picture, using conventional decoding circuits and without deteriorating the efficiency in parallel processing.An image decoding device (100) includes: a stream segmentation unit (110) which segments a bit stream such that each of the coded pictures are segmented into two areas; and decoding processing units (120, 130) each of which decodes a corresponding one of the two segmented bit streams. The respective decoding processing units (120, 130) include: decoding units (123, 133) each of which generates decoded data including pixel data and control data; transfer determination units (124, 134) each of which determines whether or not the decoded data is referred to in another one of the processing units; data transfer units (125, 135) each of which transfers decoded data to the other processing unit; and decoding determination units (122, 132) each of which determines whether or not the decoded data to be referred to has been obtained. Each of the decoding units (123, 133) decodes a corresponding one of the segmented bit streams when reference decoded data has been obtained.
摘要翻译：为了解码每个图像中具有依赖性的编码图像，使用传统的解码电路并且不降低并行处理的效率。图像解码装置（100）包括：流分割单元（110），其分割位流，使得每个编码图像被分割成两个区域; 以及解码处理单元（120,130），每个解码处理单元解码两个分段比特流中的对应的一个。相应的解码处理单元（120,130）包括：解码单元（123,133），每个解码单元生成包括像素数据和控制数据的解码数据; 转移确定单元（124,134），每个确定单元确定在另一个处理单元中是否参考解码数据; 数据传送单元（125,135），每个数据传送单元将解码的数据传送到另一个处理单元; 以及解码确定单元（122,132），每个解码确定单元确定是否已经获得了要被提及的解码数据。当已经获得参考解码数据时，解码单元（123,133）中的每一个解码对应的一个分段比特流。

3. 发明申请

US20100246665A1 PARALLELIZATION OF HIGH-PERFORMANCE VIDEO ENCODING ON A SINGLE-CHIP MULTIPROCESSOR 有权
标题翻译：高性能视频编码在单芯片多媒体处理器上的并行化
公开(公告)号：US20100246665A1
公开(公告)日：2010-09-30
申请号：US12625484
申请日：2009-11-24
申请人： J. Dean Brederson , Greg Gillis , Sean Heffernan , Daichi Furusaka , Keishi Chikamura , Masato Hori , Di Wu , Lim Boon Shyang
发明人： J. Dean Brederson , Greg Gillis , Sean Heffernan , Daichi Furusaka , Keishi Chikamura , Masato Hori , Di Wu , Lim Boon Shyang
IPC分类号： H04N7/26
CPC分类号： H04N19/00515 , H04N19/174 , H04N19/423 , H04N19/433 , H04N19/436 , H04N19/61
摘要： High-quality video encoding may be implemented using a single-chip multiprocessor system. Video encoding may be parallelized to take advantage of multiple processing elements available on a single-chip multiprocessor system. Task level parallelism may comprise parallelizing encoding tasks, such as motion estimation, compensation, transformation, quantization, deblocking filtering, and the like across multiple processing elements. Data level parallelism may comprise segmenting video frame data into macroblock partitions and slabs adapted to provide data independence between parallel processing elements. Data communications and synchronization features of the single-chip system may be leveraged to provide for data sharing and synchronism between processing elements.
摘要翻译：可以使用单片多处理器系统来实现高质量视频编码。视频编码可以并行化以利用单芯片多处理器系统上可用的多个处理元件。任务级并行可以包括跨多个处理元件并行编码任务，诸如运动估计，补偿，变换，量化，去块滤波等。数据级并行可以包括将视频帧数据分割成宏块分区和适于在并行处理元件之间提供数据独立性的平板。可以利用单芯片系统的数据通信和同步特征来提供处理元件之间的数据共享和同步。

4. 发明申请

US20070028055A1 Cache memory and cache memory control method 审中-公开
标题翻译：缓存内存和缓存内存控制方式
公开(公告)号：US20070028055A1
公开(公告)日：2007-02-01
申请号：US10571531
申请日：2004-08-23
申请人： Tetsuya Tanaka , Ryuta Nakanishi , Tokuzo Kiyohara , Hiroyuki Morishita , Keishi Chikamura
发明人： Tetsuya Tanaka , Ryuta Nakanishi , Tokuzo Kiyohara , Hiroyuki Morishita , Keishi Chikamura
IPC分类号： G06F12/00
CPC分类号： G06F12/127 , G06F12/124
摘要： A cache memory of the present invention includes: for each cache entry, way 0 to way 3 which hold use flags U indicating whether or not the use flags U have been accessed; and a control unit which: updates, when a cache entry is hit, a use flag U corresponding to the hit cache entry so that the use flag U indicates that the cache entry has been accessed; and reset, in the case where all other use flags in the same set indicates that the cache entries have been accessed herein, the all other use flags so that the use flags indicate that the cache entries have not been accessed; and select a cache entry to be replaced from among the cache entries corresponding to the use flags indicating that the cache entries have not been accessed.
摘要翻译：本发明的高速缓存存储器包括：对于每个高速缓存条目，方式0到路径3，其保持使用标志U，指示是否已经访问了使用标志U; 以及控制单元，其在高速缓存条目被命中时更新与所述命中高速缓存条目对应的使用标志U，使得所述使用标志U指示所述高速缓存条目已经被访问; 并且在同一集合中的所有其他使用标志指示已经在这里访问了高速缓存条目的情况下，复位所有其他使用标志，使得使用标志指示高速缓存条目未被访问; 并且从与指示高速缓存条目未被访问的使用标志相对应的高速缓存条目中选择要替换的高速缓存条目。

5. 发明授权

US08681862B2 Moving picture decoding apparatus and moving picture decoding method 有权
标题翻译：运动图像解码装置和运动图像解码方法
公开(公告)号：US08681862B2
公开(公告)日：2014-03-25
申请号：US12517108
申请日：2008-05-14
申请人： Keishi Chikamura , Takeshi Tanaka
发明人： Keishi Chikamura , Takeshi Tanaka
IPC分类号： H04N7/12 , H04N11/02 , H04N11/04 , H04B1/66 , H04N7/26
CPC分类号： H04N19/00515 , H04N19/433 , H04N19/44 , H04N19/52 , H04N19/573 , H04N19/61
摘要： A moving picture decoding apparatus (10) that decodes moving picture data including a coded picture which has been coded according to a coding scheme of performing inter-frame prediction with reference to a maximum of n pictures, where n is an integer equal to or greater than 2, the moving picture decoding apparatus (10) comprising: an H.264 decoder (100) which decodes the coded picture included in the moving picture data using the inter-frame prediction; an external memory (107) which stores a decoded picture for external output thereof; an internal memory (106) which stores n decoded pictures which can be referred to for the inter-frame prediction; and a second transfer unit (102) which transfers the decoded picture from the external memory (107) to the internal memory (106) so that the n decoded pictures are stored in the internal memory (106) before decoding of one coded picture starts.
摘要翻译：一种运动图像解码装置（10），其对包含编码图像的运动图像数据进行解码，所述编码图像已经根据参照n个图像的最大值执行帧间预测的编码方案被编码，其中n是等于或大于等于的整数 2），运动图像解码装置（10）包括：H.264解码器（100），其使用帧间预测对包含在运动图像数据中的编码图像进行解码; 外部存储器（107），其存储用于其外部输出的解码图像; 内部存储器（106），其存储可以参考帧间预测的n个解码图像; 以及将解码图像从外部存储器（107）传送到内部存储器（106）的第二传送单元（102），使得在解码一个编码图像开始之前，将n个解码的图像存储在内部存储器（106）中。

6. 发明授权

US08649439B2 Decoding circuit, decoding device, and decoding system 有权
标题翻译：解码电路，解码装置和解码系统
公开(公告)号：US08649439B2
公开(公告)日：2014-02-11
申请号：US11791220
申请日：2005-11-15
申请人： Keishi Chikamura , Takeshi Tanaka
发明人： Keishi Chikamura , Takeshi Tanaka
IPC分类号： H04N7/12
CPC分类号： H04N19/433 , H04N19/436 , H04N19/44 , H04N19/513 , H04N19/577
摘要： A decoding circuit, a decoding device, and a decoding system are included for decoding a B picture encoded by a direct mode at a high speed. A decoding process of an n-th macroblock is performed in parallel with transfer of a motion vector of an anchor block for an (n+1)-th macroblock to a buffer 106. With this construction, even if the (n+1)-th macroblock is encoded by the direct mode, a motion vector can be immediately calculated using the motion vector of the anchor block for the (n+1)-th macroblock in the buffer 106, when the (n+1)-th macroblock is decoded during a time T2.
摘要翻译：包括解码电路，解码装置和解码系统，用于对由直接模式高速编码的B图像进行解码。与将第（n + 1）个宏块的锚块的运动矢量传送到缓冲器106并行地执行第n个宏块的解码处理。利用这种结构，即使第（n + 1）通过直接模式编码第二宏块，当第（n + 1）个宏块在第（n + 1）个宏块时，可以使用缓冲器106中的第（n + 1）个宏块的锚块的运动矢量立即计算运动矢量在时间T2期间被解码。

7. 发明申请

US20100054332A1 MOVING PICTURE DECODING APPARATUS AND MOVING PICTURE DECODING METHOD 有权
标题翻译：移动图像解码装置和移动图像解码方法
公开(公告)号：US20100054332A1
公开(公告)日：2010-03-04
申请号：US12517108
申请日：2008-05-14
申请人： Keishi Chikamura , Takeshi Tanaka
发明人： Keishi Chikamura , Takeshi Tanaka
IPC分类号： H04N7/26 , H04N7/32
CPC分类号： H04N19/00515 , H04N19/433 , H04N19/44 , H04N19/52 , H04N19/573 , H04N19/61
摘要： A moving picture decoding apparatus (10) that decodes moving picture data including a coded picture which has been coded according to a coding scheme of performing inter-frame prediction with reference to a maximum of n pictures, where n is an integer equal to or greater than 2, the moving picture decoding apparatus (10) comprising: an H.264 decoder (100) which decodes the coded picture included in the moving picture data using the inter-frame prediction; an external memory (107) which stores a decoded picture for external output thereof; an internal memory (106) which stores n decoded pictures which can be referred to for the inter-frame prediction; and a second transfer unit (102) which transfers the decoded picture from the external memory (107) to the internal memory (106) so that the n decoded pictures are stored in the internal memory (106) before decoding of one coded picture starts.
摘要翻译：一种运动图像解码装置（10），其对包含编码图像的运动图像数据进行解码，所述编码图像已经根据参照n个图像的最大值执行帧间预测的编码方案被编码，其中n是等于或大于等于的整数 2），运动图像解码装置（10）包括：H.264解码器（100），其使用帧间预测对包含在运动图像数据中的编码图像进行解码; 外部存储器（107），其存储用于其外部输出的解码图像; 内部存储器（106），其存储可以参考帧间预测的n个解码图像; 以及将解码图像从外部存储器（107）传送到内部存储器（106）的第二传送单元（102），使得在解码一个编码图像开始之前，将n个解码的图像存储在内部存储器（106）中。

8. 发明授权

US08855191B2 Parallelization of high-performance video encoding on a single-chip multiprocessor 有权
标题翻译：在单芯片多处理器上并行化高性能视频编码
公开(公告)号：US08855191B2
公开(公告)日：2014-10-07
申请号：US12625484
申请日：2009-11-24
申请人： J. Dean Brederson , Greg Gillis , Sean Heffernan , Daichi Furusaka , Keishi Chikamura , Masato Hori , Di Wu , Lim Boon Shyang
发明人： J. Dean Brederson , Greg Gillis , Sean Heffernan , Daichi Furusaka , Keishi Chikamura , Masato Hori , Di Wu , Lim Boon Shyang
IPC分类号： H04N7/12 , H04N19/61 , H04N19/433 , H04N19/436 , H04N19/174 , H04N19/423
CPC分类号： H04N19/00515 , H04N19/174 , H04N19/423 , H04N19/433 , H04N19/436 , H04N19/61
摘要： High-quality video encoding may be implemented using a single-chip multiprocessor system. Video encoding may be parallelized to take advantage of multiple processing elements available on a single-chip multiprocessor system. Task level parallelism may comprise parallelizing encoding tasks, such as motion estimation, compensation, transformation, quantization, deblocking filtering, and the like across multiple processing elements. Data level parallelism may comprise segmenting video frame data into macroblock partitions and slabs adapted to provide data independence between parallel processing elements. Data communications and synchronization features of the single-chip system may be leveraged to provide for data sharing and synchronism between processing elements.
摘要翻译：可以使用单片多处理器系统来实现高质量视频编码。视频编码可以并行化以利用单芯片多处理器系统上可用的多个处理元件。任务级并行可以包括跨多个处理元件并行编码任务，诸如运动估计，补偿，变换，量化，去块滤波等。数据级并行可以包括将视频帧数据分割成宏块分区和适于在并行处理元件之间提供数据独立性的平板。可以利用单芯片系统的数据通信和同步特征来提供处理元件之间的数据共享和同步。

9. 发明申请

US20080008244A1 Decoding Circuit, Decoding Device, And Decoding System 有权
标题翻译：解码电路，解码设备和解码系统
公开(公告)号：US20080008244A1
公开(公告)日：2008-01-10
申请号：US11791220
申请日：2005-11-15
申请人： Keishi Chikamura , Takeshi Tanaka
发明人： Keishi Chikamura , Takeshi Tanaka
IPC分类号： H04N11/02 , H04N7/12 , H04N7/26
CPC分类号： H04N19/433 , H04N19/436 , H04N19/44 , H04N19/513 , H04N19/577
摘要： An object of the present invention is to provide a decoding circuit, a decoding device, and a decoding system for decoding a B picture encoded by a direct mode at a high speed. A decoding process of an n-th macroblock (steps S103 to S115) is performed in parallel with transfer of a motion vector of an anchor block for an (n+1)-th macroblock to a buffer 106 (steps S102 and S116). With this construction, even if the (n+1)-th macroblock is encoded by the direct mode, a motion vector can be immediately calculated using the motion vector of the anchor block for the (n+1)-th macroblock in the buffer 106, when the (n+1)-th macroblock is decoded during a time T2.
摘要翻译：本发明的目的是提供一种解码电路，解码装置和解码系统，用于对通过直接模式高速编码的B图像进行解码。与第（n + 1）个宏块的锚块的运动矢量传送到缓冲器106并行地执行第n个宏块的解码处理（步骤S103〜S115）（步骤S102和 S 116）。利用这种结构，即使第（n + 1）个宏块被直接模式编码，也可以使用缓冲器中第（n + 1）个宏块的锚块的运动矢量立即计算运动矢量 106，当第（n + 1）个宏块在时间T 2期间被解码时。

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