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1. 发明申请

US20070138573A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070138573A1
公开(公告)日：2007-06-21
申请号：US11565913
申请日：2006-12-01
申请人： Keiichiro KASHIHARA , Tomonori Okudaira , Tadashi Yamaguchi , Atsushi Ishinaga , Kenshi Kanegae , Akihiko Tsuzumitani
发明人： Keiichiro KASHIHARA , Tomonori Okudaira , Tadashi Yamaguchi , Atsushi Ishinaga , Kenshi Kanegae , Akihiko Tsuzumitani
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device according to the present invention comprises a silicon substrate, a gate electrode formed on a main surface of the silicon substrate with a gate insulation film therethrough, a sidewall spacer formed so as to cover a side surface of the gate electrode and including at least two layers of a silicon oxide film as a lowermost layer and a silicon nitride film formed thereon, a source region and a drain region formed in the main surface of the silicon substrate so as to sandwich the gate electrode, a protection film formed so as to cover an end surface of the silicon oxide film without extending below said silicon nitride film, the end surface being on a side of said source region and said drain region, and a metal silicide layer formed in the source region and the drain region on a side of said protection film away from said gate electrode.
摘要翻译：根据本发明的半导体器件包括硅衬底，在硅衬底的主表面上形成有栅绝缘膜的栅电极，形成为覆盖栅电极的侧表面的侧壁间隔件，至少两层作为最下层的氧化硅膜和形成在其上的氮化硅膜，在硅衬底的主表面中形成的源极区和漏极区，以便夹着栅电极，保护膜形成为为了覆盖氧化硅膜的端面而不延伸到所述氮化硅膜的下方，所述端面位于所述源极区域和所述漏极区域的一侧，以及形成在所述源极区域和所述漏极区域中的金属硅化物层所述保护膜的一侧远离所述栅电极。

2. 发明授权

US07663191B2 Semiconductor device and manufacturing method thereof with rounded gate including a silicide on the top and at the corners 有权
标题翻译：半导体器件及其制造方法，其具有在顶部和拐角处具有硅化物的圆形栅极
公开(公告)号：US07663191B2
公开(公告)日：2010-02-16
申请号：US11178612
申请日：2005-07-12
申请人： Kenshi Kanegae , Akihiko Tsuzumitani , Atsushi Ikeda
发明人： Kenshi Kanegae , Akihiko Tsuzumitani , Atsushi Ikeda
IPC分类号： H01L27/092 , H01L27/095
CPC分类号： H01L21/32139 , H01L21/28052 , H01L21/28114 , H01L21/321 , H01L21/32132 , H01L21/32134 , H01L21/32137 , H01L29/665
摘要： In order that a top surface of a gate electrode does not have sharp portions, ends of the top surface of the gate electrode are rounded before refractory metal is deposited for silicidation. This reduces intensive application of film stresses which are generated in heat treatment, enabling formation of a silicide layer with a uniform, sufficient thickness.
摘要翻译：为了使栅电极的上表面不具有尖锐部分，在沉积难熔金属以进行硅化处理之前，栅极顶表面的端部是圆形的。这减少了在热处理中产生的膜应力的集约应用，使得能够形成具有均匀的足够厚度的硅化物层。

3. 发明申请

US20060006478A1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060006478A1
公开(公告)日：2006-01-12
申请号：US11178612
申请日：2005-07-12
申请人： Kenshi Kanegae , Akihiko Tsuzumitani , Atsushi Ikeda
发明人： Kenshi Kanegae , Akihiko Tsuzumitani , Atsushi Ikeda
IPC分类号： H01L29/76 , H01L21/3205
CPC分类号： H01L21/32139 , H01L21/28052 , H01L21/28114 , H01L21/321 , H01L21/32132 , H01L21/32134 , H01L21/32137 , H01L29/665
摘要： In order that a top surface of a gate electrode does not have sharp portions, ends of the top surface of the gate electrode are rounded before refractory metal is deposited for silicidation. This reduces intensive application of film stresses which are generated in heat treatment, enabling formation of a silicide layer with a uniform, sufficient thickness.
摘要翻译：为了使栅电极的上表面不具有尖锐部分，在沉积难熔金属以进行硅化处理之前，栅极顶表面的端部是圆形的。这减少了在热处理中产生的膜应力的集约应用，使得能够形成具有均匀的足够厚度的硅化物层。

4. 发明授权

US07973367B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07973367B2
公开(公告)日：2011-07-05
申请号：US12650009
申请日：2009-12-30
申请人： Kenshi Kanegae , Akihiko Tsuzumitani , Atsushi Ikeda
发明人： Kenshi Kanegae , Akihiko Tsuzumitani , Atsushi Ikeda
IPC分类号： H01L27/092 , H01L27/095
CPC分类号： H01L21/32139 , H01L21/28052 , H01L21/28114 , H01L21/321 , H01L21/32132 , H01L21/32134 , H01L21/32137 , H01L29/665
摘要： In order that a top surface of a gate electrode does not have sharp portions, ends of the top surface of the gate electrode are rounded before refractory metal is deposited for silicidation. This reduces intensive application of film stresses which are generated in heat treatment, enabling formation of a silicide layer with a uniform, sufficient thickness.
摘要翻译：为了使栅电极的上表面不具有尖锐部分，在沉积难熔金属以进行硅化处理之前，栅极顶表面的端部是圆形的。这减少了在热处理中产生的膜应力的集约应用，使得能够形成具有均匀的足够厚度的硅化物层。

5. 发明申请

US20100102396A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100102396A1
公开(公告)日：2010-04-29
申请号：US12650009
申请日：2009-12-30
申请人： Kenshi Kanegae , Akihiko Tsuzumitani , Atsushi Ikeda
发明人： Kenshi Kanegae , Akihiko Tsuzumitani , Atsushi Ikeda
IPC分类号： H01L27/088 , H01L29/78
CPC分类号： H01L21/32139 , H01L21/28052 , H01L21/28114 , H01L21/321 , H01L21/32132 , H01L21/32134 , H01L21/32137 , H01L29/665
摘要： In order that a top surface of a gate electrode does not have sharp portions, ends of the top surface of the gate electrode are rounded before refractory metal is deposited for silicidation. This reduces intensive application of film stresses which are generated in heat treatment, enabling formation of a silicide layer with a uniform, sufficient thickness.
摘要翻译：为了使栅电极的上表面不具有尖锐部分，在沉积难熔金属以进行硅化处理之前，栅极顶表面的端部是圆形的。这减少了在热处理中产生的膜应力的集约应用，使得能够形成具有均匀的足够厚度的硅化物层。

6. 发明申请

US20100078730A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100078730A1
公开(公告)日：2010-04-01
申请号：US12633486
申请日：2009-12-08
申请人： Yoichi YOSHIDA , Akihiko Tsuzumitani , Kenshi Kanegae
发明人： Yoichi YOSHIDA , Akihiko Tsuzumitani , Kenshi Kanegae
IPC分类号： H01L27/092 , H01L21/762 , H01L29/772
CPC分类号： H01L21/823842 , H01L21/28097 , H01L21/823835 , H01L29/4975 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/6656
摘要： A semiconductor device includes a gate electrode. The gate electrode includes a silicide layer obtained by siliciding porous silicon or organic silicon.
摘要翻译：半导体器件包括栅电极。栅电极包括通过硅化多孔硅或有机硅而获得的硅化物层。

7. 发明授权

US08242567B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08242567B2
公开(公告)日：2012-08-14
申请号：US13117786
申请日：2011-05-27
申请人： Kenshi Kanegae , Akihiko Tsuzumitani , Atsushi Ikeda
发明人： Kenshi Kanegae , Akihiko Tsuzumitani , Atsushi Ikeda
IPC分类号： H01L21/70 , H01L21/02
CPC分类号： H01L21/32139 , H01L21/28052 , H01L21/28114 , H01L21/321 , H01L21/32132 , H01L21/32134 , H01L21/32137 , H01L29/665
摘要： In order that a top surface of a gate electrode does not have sharp portions, ends of the top surface of the gate electrode are rounded before refractory metal is deposited for silicidation. This reduces intensive application of film stresses which are generated in heat treatment, enabling formation of a silicide layer with a uniform, sufficient thickness.
摘要翻译：为了使栅电极的上表面不具有尖锐部分，在沉积难熔金属以进行硅化处理之前，栅极顶表面的端部是圆形的。这减少了在热处理中产生的膜应力的集约应用，使得能够形成具有均匀的足够厚度的硅化物层。

8. 发明申请

US20110227172A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110227172A1
公开(公告)日：2011-09-22
申请号：US13117786
申请日：2011-05-27
申请人： Kenshi Kanegae , Akihiko Tsuzumitani , Atsushi Ikeda
发明人： Kenshi Kanegae , Akihiko Tsuzumitani , Atsushi Ikeda
IPC分类号： H01L29/78
CPC分类号： H01L21/32139 , H01L21/28052 , H01L21/28114 , H01L21/321 , H01L21/32132 , H01L21/32134 , H01L21/32137 , H01L29/665
摘要： In order that a top surface of a gate electrode does not have sharp portions, ends of the top surface of the gate electrode are rounded before refractory metal is deposited for silicidation. This reduces intensive application of film stresses which are generated in heat treatment, enabling formation of a silicide layer with a uniform, sufficient thickness.
摘要翻译：为了使栅电极的上表面不具有尖锐部分，在沉积难熔金属以进行硅化处理之前，栅极顶表面的端部是圆形的。这减少了在热处理中产生的膜应力的集约应用，使得能够形成具有均匀的足够厚度的硅化物层。

9. 发明授权

US06784474B2 Semiconductor memory device and method for fabricating the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06784474B2
公开(公告)日：2004-08-31
申请号：US10203430
申请日：2002-08-08
申请人： Hisashi Ogawa , Yoshihiro Mori , Akihiko Tsuzumitani
发明人： Hisashi Ogawa , Yoshihiro Mori , Akihiko Tsuzumitani
IPC分类号： H01L2976
CPC分类号： H01L27/10894 , H01L27/10885 , H01L28/55 , H01L28/60 , Y10S257/905 , Y10S257/908
摘要： A memory cell in a DRAM, which is a semiconductor memory device, is provided with a bit line 21a connected to a bit line plug 20b and a local interconnect 21b, over a first interlevel insulating film 18. A conductor sidewall 40 of TiAlN is formed on side faces of hard mask 37, upper barrier metal 36, Pt film 35 and BST film 34. No contact hole is provided on the Pt film 35 constituting an upper electrode 35a. The upper electrode 35a is connected to an upper interconnect (a Cu interconnect 42) via the conductor sidewall 40, dummy lower electrode 33b, dummy cell plug 30 and local interconnect 21b. The Pt film 35 is not exposed to a reducing atmosphere, and therefore deterioration in characteristics of the capacitive insulating film 34a can be prevented.
摘要翻译：作为半导体存储器件的DRAM中的存储单元在第一层间绝缘膜18上设置有连接到位线插头20b和局部互连21b的位线21a。形成TiAlN的导体侧壁40 在硬掩模37，上阻挡金属36，Pt膜35和BST膜34的侧面上。在构成上电极35a的Pt膜35上没有设置接触孔。上电极35a经由导体侧壁40，虚拟下电极33b，虚设电池插塞30和局部互连21b与上互连（铜互连42）连接。 Pt膜35不暴露于还原气氛中，因此可以防止电容绝缘膜34a的特性劣化。

10. 发明授权

US06265262B1 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06265262B1
公开(公告)日：2001-07-24
申请号：US09587363
申请日：2000-06-02
申请人： Yasutoshi Okuno , Akihiko Tsuzumitani , Yoshihiro Mori
发明人： Yasutoshi Okuno , Akihiko Tsuzumitani , Yoshihiro Mori
IPC分类号： H01L218242
CPC分类号： H01L21/7687 , H01L21/28518 , H01L21/76849 , H01L21/76889 , H01L27/10852 , H01L28/60
摘要： A silicon film is formed within a contact hole formed in a first insulating film on a semiconductor substrate in a manner that an upper portion of the contact hole remains, and a cobalt film is then deposited on the silicon film. Thereafter, a heat treatment is carried out so as to react the silicon film with the cobalt film, thereby forming a cobalt silicide layer in the surface portion of the silicon film. A barrier layer is formed on the cobalt silicide layer so as to completely fill the contact hole, and thus, a plug including the polysilicon film, the cobalt silicide layer and the barrier layer is formed. After a recess is formed in a second insulating film deposited on the first insulating film so as to expose the top surface of the plug, a capacitor bottom electrode, a capacitor dielectric film and a capacitor top electrode are successively formed in the recess.
摘要翻译：在半导体基板上形成在第一绝缘膜上的接触孔内形成硅膜，使得保留接触孔的上部，然后在硅膜上沉积钴膜。此后，进行热处理以使硅膜与钴膜反应，从而在硅膜的表面部分形成钴硅化物层。在硅化钴层上形成阻挡层，以完全填充接触孔，从而形成包括多晶硅膜，硅化钴层和阻挡层的插塞。在沉积在第一绝缘膜上的第二绝缘膜中形成凹部以暴露插头的顶面之后，在凹部中依次形成电容器底部电极，电容器电介质膜和电容器顶部电极。

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