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    • 6. 发明授权
    • Liquid crystal display
    • 液晶显示器
    • US08823622B2
    • 2014-09-02
    • US11933232
    • 2007-10-31
    • Michiru SendaRyoichi Yokoyama
    • Michiru SendaRyoichi Yokoyama
    • G09G3/36
    • G09G3/3648G09G3/3614G09G3/3677G09G2310/0218G09G2310/08G09G2340/16
    • A liquid crystal display includes a plurality of gate lines having odd-numbered gate lines and even-numbered gate lines, a plurality of source lines, a first gate driver which drives the odd-numbered gate lines, a second gate driver which drives the even-numbered gate lines and a driving controller which outputs an overdriven image signal in at least one driving period of a plurality of driving periods and outputs a normal image signal in remaining driving periods of the plurality of driving periods. The overdriven image signal is obtained by adding an overdrive voltage to the normal image signal, and the overdrive voltage is set according to a level of the normal image signal.
    • 液晶显示器包括具有奇数栅极线和偶数栅极线的多条栅极线,多条源极线,驱动奇数栅极线的第一栅极驱动器,驱动奇数栅极线的第二栅极驱动器 并且驱动控制器在多个驱动周期的至少一个驱动周期内输出过驱动图像信号,并且在多个驱动周期的剩余驱动周期中输出正常图像信号。 通过向正常图像信号添加过驱动电压来获得过驱动图像信号,并且根据正常图像信号的电平来设定过驱动电压。
    • 7. 发明授权
    • Delay locked-loop circuit and display apparatus
    • 延迟锁定环电路和显示设备
    • US08816733B2
    • 2014-08-26
    • US12379727
    • 2009-02-27
    • Hiroshi MizuhashiMichiru SendaGen Koide
    • Hiroshi MizuhashiMichiru SendaGen Koide
    • H03L7/06H03L7/081H03L7/093
    • H03L7/0814H03L7/0818H03L7/093
    • A delay locked-loop circuit includes: a phase comparator detecting a phase difference between an external clock and an internal clock; an up/down counter controlling a delay time in accordance with an output signal from the phase comparator; and a delay line including plural unit delay circuits corresponding to plural bits of a signal output from the up/down counter in order to control the delay of the external clock to conform the external clock to the internal clock, and in which the unit delay circuits controlled by the output from a same bit in the output from the up/down counter are not connected adjacently to each other in the connection of the plural unit delay circuits in series.
    • 延迟锁定环电路包括:检测外部时钟和内部时钟之间的相位差的相位比较器; 上/下计数器根据来自相位比较器的输出信号控制延迟时间; 以及延迟线,包括对应于从上/下计数器输出的信号的多个比特的多个单位延迟电路,以便控制外部时钟的延迟以使外部时钟符合内部时钟,并且其中单位延迟电路 在多个单元延迟电路的串联连接中,来自上/下计数器的输出中的同一位的输出控制不相互连接。
    • 9. 发明申请
    • IMAGE PICKUP UNIT AND IMAGE-PICKUP AND DISPLAY SYSTEM
    • 图像拾取单元和图像拾取和显示系统
    • US20130044250A1
    • 2013-02-21
    • US13571620
    • 2012-08-10
    • Michiru SendaShinji Fujimoto
    • Michiru SendaShinji Fujimoto
    • H01L27/146H04N5/225
    • H04N5/3597H04N5/32
    • An image pickup unit including: an image pickup section including pixels, each of the pixels including a photoelectric conversion device; and a drive section performing a line-sequential readout drive and a line-sequential reset drive. The drive section intermittently performs the line-sequential reset drive multiple times during one frame period, to allow a non-overlap period to be provided at least in part of reset operation periods in an overlap period. The overlap period is a period during which a drive period of one of the multiple line-sequential reset drives and a drive period of one of the remaining multiple line-sequential reset drives are overlapped. The non-overlap period is a period during which each of the reset operations by the one of the multiple line-sequential drives is not overlapped with any of the reset operations by the one of the remaining multiple line-sequential reset drives.
    • 一种图像拾取单元,包括:包括像素的图像拾取部分,每个像素包括光电转换装置; 以及执行行顺序读出驱动和行顺序复位驱动的驱动部。 驱动部分在一个帧周期期间间歇地执行行顺序复位驱动,以允许在重叠周期中至少部分复位操作期间提供非重叠周期。 重叠期间是多个行顺序复位驱动中的一个的驱动周期和剩余的多个行顺序复位驱动中的一个的驱动周期重叠的时间段。 非重叠周期是其中多个线顺序驱动器中的一个驱动器的每个复位操作不与剩余的多个行顺序重置驱动器中的一个的任何复位操作重叠的时段。
    • 10. 发明申请
    • SIGNAL TRANSMISSION APPARATUS AND IMAGING DISPLAY SYSTEM
    • 信号传输装置和成像显示系统
    • US20120299804A1
    • 2012-11-29
    • US13468403
    • 2012-05-10
    • Michiru Senda
    • Michiru Senda
    • H01L27/146G09G3/20
    • H04N5/374G09G3/20G09G2300/0426G09G2330/04G09G2330/06H04N5/32
    • A signal transmission apparatus including electrostatic discharge protection circuits arranged between a signal line and a wiring line of plural pixel wiring lines, each having a first transistor and a capacitor device; and a first control line connected to the electrostatic discharge protection circuits, wherein, in the electrostatic discharge protection circuit, a gate of the first transistor is connected to the first control line, one of a source and a drain in the first transistor is connected to one signal line and one terminal of the capacitor device as well as the other is connected to another wiring line, and the other terminal of the capacitor device is connected to the gate of the first transistor.
    • 一种信号传输装置,包括布置在多个像素布线的信号线和布线之间的静电放电保护电路,每个具有第一晶体管和电容器装置; 以及连接到所述静电放电保护电路的第一控制线,其中在所述静电放电保护电路中,所述第一晶体管的栅极连接到所述第一控制线,所述第一晶体管中的源极和漏极之一连接到 电容器装置的一个信号线和一个端子以及另一个连接到另一个布线,并且电容器装置的另一个端子连接到第一晶体管的栅极。