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    • 1. 发明授权
    • Vacuum heat treating method and apparatus therefor
    • 真空热处理方法及其设备
    • US07357843B2
    • 2008-04-15
    • US10485826
    • 2001-11-30
    • Kazuyoshi YamaguchiYasunori Tanaka
    • Kazuyoshi YamaguchiYasunori Tanaka
    • C23C8/20C21D1/74
    • C23C8/30C23C8/20C23C8/22C23C8/32
    • The present invention provides a vacuum heat treating method, such as carburization, carbonitridation, high temperature carburization, high concentration carburization and the like, performed while supplying a mixed gas of ethylene gas and hydrogen gas under reduced pressures. The method includes: detecting a quantity of ethylene gas and that of hydrogen gas in a vacuum heat treating furnace (1); calculating an equivalent carbon concentration of atmosphere on the basis of the detected quantity of ethylene gas and that of hydrogen gas; and comparing the calculated value with a targeted value which is set on the basis of a material specification and required heat treatment performance of an object to be treated (a workpiece), to control quantities of ethylene gas and hydrogen gas supplied into the vacuum heat treating furnace (1) on the basis of a difference between the calculated value and the targeted value. A heat treatment quality required for the workpiece can be obtained with accuracy and reproducibility.
    • 本发明提供了在减压下供给乙烯气体和氢气的混合气体的同时进行渗碳,碳氮化,高温渗碳,高浓度渗碳等的真空热处理方法。 该方法包括:在真空热处理炉(1)中检测乙烯气体量和氢气量; 基于检测到的乙烯气体量和氢气的量来计算大气的等效碳浓度; 将计算出的值与根据材料规格设定的目标值和被处理物(工件)的要求的热处理性能进行比较,以控制提供给真空热处理的乙烯气体和氢气的量 基于计算值与目标值之差的炉(1)。 可以准确和重复地获得工件所需的热处理质量。
    • 7. 发明授权
    • Transfer apparatus
    • 转运设备
    • US06714265B2
    • 2004-03-30
    • US09972964
    • 2001-10-10
    • Naoyoshi ChinoYasunori TanakaMasato Mizuno
    • Naoyoshi ChinoYasunori TanakaMasato Mizuno
    • G02F113
    • B41J2/4473B41J2/445
    • The transfer apparatus includes a light source, a transmission type image display device in which a liquid crystal layer is held between two sets of substrates and polarizing plates and a photosensitive recording medium. The light source, the image display device and the photosensitive recording medium are arranged in series along a direction in which light from the light source advances and the image display device and the photosensitive recording medium are arranged in a non-contact state. A display image transmitted from the transmission type image display device is transferred to the photosensitive recording medium. A distance between the image display device and the photosensitive recording medium and a sum total of thicknesses of the substrate and the polarizing plate at least on a side of the photosensitive recording medium in the image display device are set in accordance with a definition of the display image.
    • 转印装置包括光源,其中液晶层保持在两组基板和偏振片之间的透射型图像显示装置和感光记录介质。 光源,图像显示装置和感光记录介质沿着来自光源的光前进的方向串联布置,并且图像显示装置和感光记录介质被布置在非接触状态。 从透射型图像显示装置发送的显示图像被转印到感光记录介质。 图像显示装置和感光记录介质之间的距离和至少在图像显示装置中的感光记录介质的一侧上的基板和偏振板的厚度的总和被设置为根据显示器的定义 图片。
    • 8. 发明授权
    • Interface circuit between different potential levels
    • 不同电位之间的接口电路
    • US5963055A
    • 1999-10-05
    • US810117
    • 1997-02-25
    • Yasunori TanakaIkue Yamamoto
    • Yasunori TanakaIkue Yamamoto
    • H01L21/8238H01L27/092H03K19/003H03K19/0175H03K19/0948H03K19/0185
    • H03K19/00315
    • A semiconductor output circuit serves as an interface circuit between LSIs having a high and a low supply voltages. The output circuit has at least a pre-buffer and an output stage circuit. The output stage circuit has a pull-up n-channel transistor arranged between an output pad and a low-voltage power source. The output pad may receive a high voltage from an external circuit, or the LSI operating with high supply voltage. The pre-buffer applies a voltage in the range of a ground voltage and a high voltage to the gate of the pull-up transistor, to turn on and off the pull-up transistor. The output stage circuit further has a reverse current prevention circuit formed between and connected to the low-voltage power source and the pull-up transistor, to block a reverse current flowing from the output pad to the low-voltage power source when the high voltage is applied to the output pad.
    • 半导体输出电路用作具有高电源电压和低电源电压的LSI之间的接口电路。 输出电路至少具有预缓冲器和输出级电路。 输出级电路具有布置在输出焊盘和低压电源之间的上拉n沟道晶体管。 输出焊盘可以从外部电路接收高电压,或者以高电源电压工作的LSI。 预缓冲器将接地电压和高电压范围内的电压施加到上拉晶体管的栅极,以便导通和关断上拉晶体管。 输出级电路还具有形成在低电压电源和上拉晶体管之间并连接到低电压电源和上拉晶体管的反向电流防止电路,以在高电压时抑制从输出焊盘流向低压电源的反向电流 被施加到输出垫。
    • 9. 发明授权
    • LSI chip having programmable buffer circuit
    • LSI芯片具有可编程缓冲电路
    • US5804987A
    • 1998-09-08
    • US636131
    • 1996-04-22
    • Kyohsuke OgawaYasunori Tanaka
    • Kyohsuke OgawaYasunori Tanaka
    • G06F3/14H03K19/173H03K19/08
    • H03K19/1736
    • An LSI chip is mounted on an LSI board. Sub-buffer circuit areas where input buffers, output buffers or input/output buffers are to be formed are provided in signal lines extending from the pad to the internal circuit of the LSI chip. Each sub-buffer circuit area has a plurality of basic elements, such as transistors and resistors, connected in parallel to one another so that different combinations of those elements can be selected by switches. A latch controller is incorporated in the LSI chip, and it has latch circuits serially connected to form a shift register structure. This latch controller sends a program signal for determining the buffer circuit characteristic to the sub-buffer circuit areas. This program signal is generated when program data is input to the latch controller. The program data is given serially via input buffers from the pads on the LSI chip. The latch controller transfers the program data to the latch circuits one after another in synchronism with a clock signal. Those pads connected to the output buffers become signal extending terminals to another circuit.
    • LSI芯片安装在LSI板上。 在从芯片延伸到LSI芯片的内部电路的信号线中设置要形成输入缓冲器,输出缓冲器或输入/输出缓冲器的子缓冲器电路区域。 每个子缓冲电路区域具有彼此并联连接的多个基本元件,例如晶体管和电阻器,从而可以通过开关选择这些元件的不同组合。 锁存控制器并入LSI芯片中,并具有串联连接形成移位寄存器结构的锁存电路。 该锁存器控制器向子缓冲器电路区域发送用于确定缓冲器电路特性的程序信号。 当程序数据被输入到锁存控制器时,产生该程序信号。 程序数据通过LSI芯片上的焊盘的输入缓冲器串行给出。 锁存器控制器与时钟信号同步地将程序数据一个接一个地传送到锁存电路。 连接到输出缓冲器的那些焊盘成为到另一个电路的信号延伸端子。
    • 10. 发明授权
    • Output circuit device preventing overshoot and undershoot
    • 输出电路装置防止过冲和下冲
    • US5801550A
    • 1998-09-01
    • US564499
    • 1995-11-29
    • Yasunori TanakaIkue Yamamoto
    • Yasunori TanakaIkue Yamamoto
    • H03K19/0175H03K17/16
    • H03K17/167
    • The pulse output circuit device comprises two transistors (2, 4) for constructing an output buffer, a transistor (7) connected between the output line (OUTP) of the output buffer and the high potential supply voltage (VDD), a transistor (8) connected between the output line (OUT) of the output buffer and the low potential supply voltage (GND), a control circuit (39) for applying a gate signal to the transistor (7), and a control circuit (40) for applying a gate signal to the transistor (8). Whenever the signal level of the output buffer changes, the two control circuits (39, 40) turn on the transistor (7) or the transistor (8) for sharp level transition at the start of level transition, but turn on the transistor (7) or the transistor (8) on the basis of the relationship between the output level of the control circuit (39, 40) and the operating point of the transistor (7) or the transistor (8) at the end of level transition for absorption of the charge and discharge current to and from a parasitic capacitance (27). In the pulse output circuit device, it is possible to effectively prevent overshoot and undershoot caused when a pulse signal is outputted therethrough, while keeping the high output response speed and without increasing the circuit area.
    • 脉冲输出电路装置包括用于构成输出缓冲器的两个晶体管(2,4),连接在输出缓冲器的输出线(OUTP)和高电位电源电压(VDD)之间的晶体管(7),晶体管(8) ),连接在输出缓冲器的输出线(OUT)和低电位电源电压(GND)之间,控制电路(39),用于向晶体管(7)施加栅极信号;以及控制电路(40) 到晶体管(8)的栅极信号。 每当输出缓冲器的信号电平变化时,两个控制电路(39,40)在电平转换开始时导通晶体管(7)或晶体管(8)以进行尖锐的电平转换,而导通晶体管(7 )或晶体管(8),基于控制电路(39,40)的输出电平与晶体管(7)或晶体管(8)在电平转换结束时的吸收的操作点之间的关系 的来自寄生电容(27)的充放电电流。 在脉冲输出电路装置中,在保持高输出响应速度且不增加电路面积的同时,可以有效地防止在输出脉冲信号时引起的过冲和下冲。