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    • 1. 发明授权
    • Waiting time display system
    • 等待时间显示系统
    • US4575707A
    • 1986-03-11
    • US471891
    • 1983-03-03
    • Kazuyoshi ImazekiToshiyuki TanakaFumio Hayashibara
    • Kazuyoshi ImazekiToshiyuki TanakaFumio Hayashibara
    • G07C11/00G08B5/36G08B7/00
    • G07C11/00G08B5/36
    • A waiting time display system comprises a plurality of remote stations each including a waiting time display unit comprising a display portion for producing a visual display corresponding to waiting time and a control unit comprising control means selectively actuatable for producing predetermined output signals corresponding to a selected waiting time. A centralized monitoring unit is also provided and is responsive to the output signals from each control unit for monitoring the waiting time displayed on each display unit. A plurality of transmission lines coupled intermediate each of the control units and its associated display unit and intermediate each of the control units and the centralized monitoring unit for transmitting the output signals from each control unit to its associated display unit and to the centralized monitoring unit, respectively.
    • 等待时间显示系统包括多个远程站,每个远程站包括等待时间显示单元,该等待时间显示单元包括用于产生与等待时间相对应的视觉显示的显示部分,以及包括控制装置的控制单元,所述控制装置可选择地致动以产生对应于所选等待 时间。 还提供了一个集中监控单元,并响应于每个控制单元的输出信号来监测每个显示单元上显示的等待时间。 多个传输线耦合在每个控制单元及其相关联的显示单元之间,并且每个控制单元和集中监控单元中间,用于将来自每个控制单元的输出信号发送到其相关联的显示单元和集中监视单元, 分别。
    • 2. 发明授权
    • Portable transceiver
    • 便携式收发器
    • US4618997A
    • 1986-10-21
    • US592825
    • 1984-03-23
    • Kazuyoshi ImazekiToshiyuki TanakaHiromichi Miyakoshi
    • Kazuyoshi ImazekiToshiyuki TanakaHiromichi Miyakoshi
    • H04B1/40
    • H04B1/405
    • A micrprocessor-controlled, frequency-synthesized radio transceiver system comprise a microprocessor for controlling the synthesis of local-oscillator frequencies for both the transmitting and receiving of radio signals. The microprocessor has a predetermined control capacity significantly smaller than the capacity required to control the synthesis of local-oscillator frequencies for a first plurality of radio frequencies. A transmitter circuit and a receiver circuit are capable of operating at all radio frequencies within the same predetermined band of frequencies. A control input arrangement permits customizing the microprocessor to control the synthesis of local-oscillator frequencies for a second plurality of radio frequencies within its predetermined control capacity. A phase-locked loop system is also provided for synthesizing the local oscillator frequencies, and comprises a VCO responsive to each of a plurality of predetermined voltage levels for generating an oscillatory signal at a corresponding frequency, a PLL control circuit coupled with the VCO and responsive to predetermined master control signals, each corresponding to a desired frequency, for producing a corresponding voltage level, and a pre-scaler circuit coupled intermediate the VCO and the PLL control circuit and responsive to the oscillatory signal for producing a scaled feedback control signal at a much lower frequency. The PLL control circuit is responsive to the feedback control signal for locking in the frequency of the oscillatory signal to the desired frequency.
    • 微处理器控制的频率合成的无线电收发器系统包括用于控制无线电信号的发送和接收的本地振荡器频率的合成的微处理器。 微处理器具有明显小于控制第一多个无线电频率的本地振荡器频率的合成所需的容量的预定控制能力。 发射机电路和接收机电路能够在相同的预定频带内的所有射频上操作。 控制输入​​装置允许定制微处理器以控制在其预定控制能力内的第二多个无线电频率的本地振荡器频率的合成。 还提供了一种用于合成本地振荡器频率的锁相环系统,并且包括响应于多个预定电压电平中的每一个以产生相应频率的振荡信号的VCO,与VCO耦合的PLL控制电路和响应 到预定的主控制信号,每个对应于期望频率的主控制信号,用于产生相应的电压电平,以及耦合在VCO和PLL控制电路之间的预定标器电路,并响应于振荡信号,以产生一个缩放的反馈控制信号 频率低得多 PLL控制电路响应反馈控制信号,将振荡信号的频率锁定到期望的频率。
    • 3. 发明授权
    • Digital signal generating circuit
    • 数字信号发生电路
    • US4427904A
    • 1984-01-24
    • US288972
    • 1981-07-31
    • Kazuyoshi ImazekiToshiyuki Tanaka
    • Kazuyoshi ImazekiToshiyuki Tanaka
    • H04J7/00G08C19/02H02P6/20H04Q9/06H03K13/00H03K19/08H03K19/092
    • G08C19/025
    • A digital signal generating circuit having a control site, a remote digital signal generating site and a two-wire cable connecting said control site and said digital signal generating site. The control site produces various Zener diode trap voltages by switch state combinations. These trap voltages are transmitted to said digital signal generating site through said two-wire cable. A plurality of level sensing units are provided in said digital signal generating site. These level sensing units sense the respective levels of the transmitted trap voltages. A plurality of switching units are provided relating to the respective level sensing units, each for generating one of two logical outputs when the related sensing unit senses a predetermined trap level condition.
    • 一种数字信号发生电路,其具有控制站点,远程数字信号发生站点和连接所述控制站点和所述数字信号发生站点的双线电缆。 控制站通过开关状态组合产生各种齐纳二极管陷波电压。 这些陷波电压通过所述双线电缆传输到所述数字信号发生站。 在所述数字信号发生位置设置多个电平感测单元。 这些电平感测单元感测传输的陷波电压的相应电平。 提供了多个开关单元,其关于各个电平感测单元,每个开关单元用于当相关感测单元感测到预定的陷阱电平状况时,产生两个逻辑输出中的一个。