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1. 发明申请

US20060117308A1 Data processing apparatus and ic card 审中-公开
标题翻译：数据处理装置和IC卡
公开(公告)号：US20060117308A1
公开(公告)日：2006-06-01
申请号：US10521551
申请日：2002-08-30
申请人： Kazuya Hirayanagi , Kenji Kitagawa , Kesami Hagiwara , Tkanori Aoki , Naoki Mitsuishi
发明人： Kazuya Hirayanagi , Kenji Kitagawa , Kesami Hagiwara , Tkanori Aoki , Naoki Mitsuishi
IPC分类号： G06F9/45
CPC分类号： G06F9/30174 , G06F9/30181
摘要： A data processing apparatus (1) can implement the execution of a virtual machine instruction based on an execution routine specified by the native instruction of a CPU (2) and has an address converting unit (3) capable of sequentially converting an address output from the CPU into the address of the native instruction by utilizing the address of a prepared execution routine in response to the application of a prescribed condition. The address converting unit reads a virtual machine instruction to be executed next and prepares the address of an execution routine corresponding thereto in parallel with the execution of the execution routine by the CPU based on the address of the native instruction which is sequentially converted. Accordingly, it is possible to reduce the overhead of a processing of loading the virtual machine instruction and a processing of executing an instruction in accordance with the execution routine which is caused by an address calculation processing based on the load processing. Consequently, it is possible to increase the speed of a data processing to be carried out by a virtual machine program described in a virtual machine instruction.
摘要翻译：数据处理装置（1）可以基于由CPU（2）的本机指令指定的执行例程来实现虚拟机指令的执行，并具有地址转换单元（3），其能够顺序地转换从 CPU响应于规定条件的应用利用准备的执行例程的地址，将其写入本地指令的地址。地址转换单元读取下一个要执行的虚拟机指令，并根据顺序地转换的本地指令的地址，通过CPU执行执行例程来准备与之相对应的执行例行程序的地址。因此，可以减少加载虚拟机指令的处理的开销和根据由基于加载处理的地址计算处理引起的执行例程来执行指令的处理。因此，可以增加由虚拟机指令中描述的虚拟机程序执行的数据处理的速度。

2. 发明授权

US07290124B2 Data processor employing register banks with overflow protection to enhance interrupt processing and task switching 有权
标题翻译：数据处理器采用具有溢出保护功能的寄存器组来增强中断处理和任务切换
公开(公告)号：US07290124B2
公开(公告)日：2007-10-30
申请号：US10690643
申请日：2003-10-23
申请人： Yasuo Sugure , Tomomi Ishikura , Kazuya Hirayanagi , Takeshi Kataoka , Seiji Takeuchi , Hiromichi Yamada , Takanaga Yamazaki
发明人： Yasuo Sugure , Tomomi Ishikura , Kazuya Hirayanagi , Takeshi Kataoka , Seiji Takeuchi , Hiromichi Yamada , Takanaga Yamazaki
IPC分类号： G06F9/48
CPC分类号： G06F9/30043 , G06F9/3012 , G06F9/30123
摘要： The present invention prevents a data processor from undesirable operation stop due to an overflow of a plurality of register banks. A status register includes an overflow flag to indicate an overflow of the plurality of register banks. When an interrupt exception occurs in a state in which data has been saved to all banks of the register banks, and the accepted interrupt exception is permitted to use the register banks, a central processing unit saves data of a register set to a stack area and reflects an overflow state in the overflow flag. When the overflow flag indicates an overflow state, if data restoration from the register banks to the register set is directed, the central processing unit restores the data from the stack area to the register set.
摘要翻译：本发明防止数据处理器由于多个寄存器组的溢出而不期望的操作停止。状态寄存器包括用于指示多个寄存器组的溢出的溢出标志。当数据已被保存到寄存器组的所有存储体的状态中发生中断异常时，允许接受的中断异常使用寄存器组，中央处理单元将寄存器组的数据保存到堆栈区域，反映溢出标志中的溢出状态。当溢出标志指示溢出状态时，如果从寄存器组到寄存器组的数据恢复被定向，则中央处理单元将数据从堆栈区恢复到寄存器组。

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