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1. 发明申请

US20070161156A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070161156A1
公开(公告)日：2007-07-12
申请号：US11687981
申请日：2007-03-19
申请人： Kazutoshi Shiba , Hiroyuki Kunishima
发明人： Kazutoshi Shiba , Hiroyuki Kunishima
IPC分类号： H01L21/00
CPC分类号： H01L23/5329 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： There is provided a method of manufacturing a semiconductor device in which interconnect capacitance is restrained. The semiconductor device 200 comprises a semiconductor substrate; a second interconnect insulating film 216 constituted of a ladder-type hydrogen siloxane formed on the semiconductor substrate; a second protection film 217 provided on the second interconnect insulating film 216; and an upper interconnect 270 formed in the second interconnect insulating film 216 and the second protection film 217. The second interconnect insulating film 216 is constituted of for example an L-Ox™ (trademark) film, and the second protection film 217 is constituted of for example a silicon oxide film.
摘要翻译：提供一种制造半导体器件的方法，其中互连电容被抑制。半导体器件200包括半导体衬底; 由在半导体衬底上形成的梯型氢硅氧烷构成的第二互连绝缘膜216; 设置在第二互连绝缘膜216上的第二保护膜217; 以及形成在第二互连绝缘膜216和第二保护膜217中的上互连270。第二互连绝缘膜216由例如L-Ox TM（商标）膜构成，第二保护膜217由例如氧化硅膜构成。

2. 发明授权

US07211896B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07211896B2
公开(公告)日：2007-05-01
申请号：US10767335
申请日：2004-01-30
申请人： Kazutoshi Shiba , Hiroyuki Kunishima
发明人： Kazutoshi Shiba , Hiroyuki Kunishima
IPC分类号： H01L23/48 , H01L29/40 , H01L214/763 , H01L21/44
CPC分类号： H01L23/5329 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： There is provided a method of manufacturing a semiconductor device in which interconnect capacitance is restrained. The semiconductor device 200 comprises a semiconductor substrate; a second interconnect insulating film 216 constituted of a ladder-type hydrogen siloxane formed on the semiconductor substrate; a second protection film 217 provided on the second interconnect insulating film 216; and an upper interconnect 270 formed in the second interconnect insulating film 216 and the second protection film 217. The second interconnect insulating film 216 is constituted of for example an L-Ox™ (trademark) film, and the second protection film 217 is constituted of for example a silicon oxide film.
摘要翻译：提供一种制造半导体器件的方法，其中互连电容被抑制。半导体器件200包括半导体衬底; 由在半导体衬底上形成的梯型氢硅氧烷构成的第二互连绝缘膜216; 设置在第二互连绝缘膜216上的第二保护膜217; 以及形成在第二互连绝缘膜216和第二保护膜217中的上互连270。第二互连绝缘膜216由例如L-Ox TM（商标）膜构成，第二保护膜217由例如氧化硅膜构成。

3. 发明授权

US07476611B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07476611B2
公开(公告)日：2009-01-13
申请号：US10980596
申请日：2004-11-04
申请人： Hiroyuki Kunishima , Toshiyuki Takewaki
发明人： Hiroyuki Kunishima , Toshiyuki Takewaki
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/2855 , H01L21/2885 , H01L21/76858 , H01L21/76864 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L21/76883 , H01L21/76886 , H01L23/53238 , H01L24/11 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05567 , H01L2224/05666 , H01L2224/13022 , H01L2224/13099 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/0104 , H01L2924/01041 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04953 , H01L2924/13091 , H01L2924/19043 , H01L2924/3011 , H01L2924/00 , H01L2224/05552 , H01L2924/00014 , H01L2924/013
摘要： An interconnect trench is formed on a dielectric layer 12 and a first HSQ layer 14 formed on a semiconductor substrate, and a tantalum family barrier metal layer 24a is formed all over the substrate. Then a seed copper-containing metal layer 60 and a plated copper layer 62 are formed so as to fill a part of the interconnect trench. After that, a bias-sputtered copper-containing metal layer 64 is formed on the plated copper layer 62 so as to fill the remaining portion of the interconnect trench and then heat treatment is performed. As a result, a dissimilar metal contained in the bias-sputtered copper-containing metal layer 64 diffuses uniformly into the plated copper layer 62.
摘要翻译：在形成在半导体衬底上的电介质层12和第一HSQ层14上形成互连沟槽，并且在整个衬底上形成钽族阻挡层金属层24a。然后，形成种子含铜金属层60和电镀铜层62，以填充互连沟槽的一部分。之后，在镀铜层62上形成偏置溅射的含铜金属层64，以填充互连槽的剩余部分，然后进行热处理。结果，偏置溅射的含铜金属层64中所含的异种金属均匀地扩散到镀覆铜层62中。

4. 发明授权

US06949832B2 Semiconductor device including dissimilar element-diffused metal layer and manufacturing method thereof 有权
标题翻译：包括异种元素扩散金属层的半导体器件及其制造方法
公开(公告)号：US06949832B2
公开(公告)日：2005-09-27
申请号：US10613069
申请日：2003-07-07
申请人： Hiroyuki Kunishima , Toshiyuki Takewaki
发明人： Hiroyuki Kunishima , Toshiyuki Takewaki
IPC分类号： H01L21/3205 , H01L21/285 , H01L21/288 , H01L21/60 , H01L21/768 , H01L23/52 , H01L23/532 , H01L23/48
CPC分类号： H01L21/76843 , H01L21/2855 , H01L21/2885 , H01L21/76858 , H01L21/76864 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L21/76883 , H01L21/76886 , H01L23/53238 , H01L24/11 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05567 , H01L2224/05666 , H01L2224/13022 , H01L2224/13099 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/0104 , H01L2924/01041 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04953 , H01L2924/13091 , H01L2924/19043 , H01L2924/3011 , H01L2924/00 , H01L2224/05552 , H01L2924/00014 , H01L2924/013
摘要： An interconnect trench is formed on a dielectric layer 12 and a first HSQ layer 14 formed on a semiconductor substrate, and a tantalum family barrier metal layer 24a is formed all over the substrate. Then a seed copper-containing metal layer 60 and a plated copper layer 62 are formed so as to fill a part of the interconnect trench. After that, a bias-sputtered copper-containing metal layer 64 is formed on the plated copper layer 62 so as to fill the remaining portion of the interconnect trench and then heat treatment is performed. As a result, a dissimilar metal contained in the bias-sputtered copper-containing metal layer 64 diffuses uniformly into the plated copper layer 62.
摘要翻译：在形成在半导体衬底上的电介质层12和第一HSQ层14上形成互连沟槽，并且在整个衬底上形成钽族势垒金属层24a。然后，形成种子含铜金属层60和电镀铜层62，以填充互连沟槽的一部分。之后，在镀铜层62上形成偏置溅射的含铜金属层64，以填充互连槽的剩余部分，然后进行热处理。结果，偏置溅射的含铜金属层64中所含的异种金属均匀地扩散到镀覆铜层62中。

5. 发明申请

US20090186284A1 Reticle, and method of laying out wirings and vias 有权
标题翻译：掩模版，布线布线和通孔的方法
公开(公告)号：US20090186284A1
公开(公告)日：2009-07-23
申请号：US12318951
申请日：2009-01-13
申请人： Hiroyuki Kunishima
发明人： Hiroyuki Kunishima
IPC分类号： G03F1/00 , G03F7/20
CPC分类号： H01L23/5226 , G03F1/00 , G03F1/36 , H01L21/31144 , H01L21/76816 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： Provided is a reticle used for forming a plurality of vias for connecting first wirings provided in a first wiring layer and second wirings provided in a second wiring layer formed above the first wiring layer. The first wirings and the second wirings are provided along one of a first direction and a second direction, and the first direction and the second direction perpendicularly cross each other. The reticle includes a plurality of via opening patterns for forming the plurality of vias. Each of the plurality of via opening patterns has a rectangular shape, and is arranged to cause each side of each of the via opening patterns to be diagonal with respect to the first direction and the second direction.
摘要翻译：提供一种用于形成用于连接设置在第一布线层中的第一配线的多个通孔的掩模版和设置在形成在第一布线层上的第二布线层中的第二布线。第一布线和第二布线沿第一方向和第二方向设置，第一方向和第二方向垂直交叉。掩模版包括用于形成多个通孔的多个通孔开口图案。多个通孔开口图案中的每一个具有矩形形状，并且被布置成使每个通孔开口图案的每一侧相对于第一方向和第二方向成对角线。

6. 发明申请

US20060027931A1 Semiconductor device and method fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20060027931A1
公开(公告)日：2006-02-09
申请号：US11185937
申请日：2005-07-21
申请人： Toshiyuki Takewaki , Hiroyuki Kunishima
发明人： Toshiyuki Takewaki , Hiroyuki Kunishima
IPC分类号： H01L23/48 , H01L23/52 , H01L23/58
CPC分类号： H01L21/76877 , H01L21/2855 , H01L21/2885 , H01L21/76883 , H01L21/76886 , H01L23/528 , H01L23/53228 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a semiconductor substrate; an insulating film provided on the semiconductor substrate; a plurality of copper interconnections provided on the same level in the insulating film. The copper interconnection includes: a first copper interconnection having a relatively narrow width; and a second copper interconnection having a relatively wide width. The first copper interconnection has the top surface thereof principally composed of copper, and the second copper interconnection has the top surface thereof principally composed of copper.
摘要翻译：半导体器件包括：半导体衬底; 设置在半导体基板上的绝缘膜; 在绝缘膜上设置在同一电平上的多个铜互连。铜互连包括：具有相对窄的宽度的第一铜互连; 以及具有相对宽的宽度的第二铜互连。第一铜互连具有主要由铜构成的顶表面，第二铜互连件的顶表面主要由铜组成。

7. 发明申请

US20050095847A1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050095847A1
公开(公告)日：2005-05-05
申请号：US10980596
申请日：2004-11-04
申请人： Hiroyuki Kunishima , Toshiyuki Takewaki
发明人： Hiroyuki Kunishima , Toshiyuki Takewaki
IPC分类号： H01L21/3205 , H01L21/285 , H01L21/288 , H01L21/60 , H01L21/768 , H01L23/52 , H01L23/532 , H01L21/4763
CPC分类号： H01L21/76843 , H01L21/2855 , H01L21/2885 , H01L21/76858 , H01L21/76864 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L21/76883 , H01L21/76886 , H01L23/53238 , H01L24/11 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05567 , H01L2224/05666 , H01L2224/13022 , H01L2224/13099 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/0104 , H01L2924/01041 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04953 , H01L2924/13091 , H01L2924/19043 , H01L2924/3011 , H01L2924/00 , H01L2224/05552 , H01L2924/00014 , H01L2924/013
摘要： An interconnect trench is formed on a dielectric layer 12 and a first HSQ layer 14 formed on a semiconductor substrate, and a tantalum family barrier metal layer 24a is formed all over the substrate. Then a seed copper-containing metal layer 60 and a plated copper layer 62 are formed so as to fill a part of the interconnect trench. After that, a bias-sputtered copper-containing metal layer 64 is formed on the plated copper layer 62 so as to fill the remaining portion of the interconnect trench and then heat treatment is performed. As a result, a dissimilar metal contained in the bias-sputtered copper-containing metal layer 64 diffuses uniformly into the plated copper layer 62.
摘要翻译：在形成在半导体衬底上的电介质层12和第一HSQ层14上形成互连沟槽，并且在整个衬底上形成钽族势垒金属层24a。然后，形成种子含铜金属层60和电镀铜层62，以填充互连沟槽的一部分。之后，在镀铜层62上形成偏置溅射的含铜金属层64，以填充互连槽的剩余部分，然后进行热处理。结果，偏置溅射的含铜金属层64中所含的异种金属均匀地扩散到镀覆铜层62中。

8. 发明授权

US07981574B2 Reticle, and method of laying out wirings and vias 有权
标题翻译：掩模版，布线布线和通孔的方法
公开(公告)号：US07981574B2
公开(公告)日：2011-07-19
申请号：US12318951
申请日：2009-01-13
申请人： Hiroyuki Kunishima
发明人： Hiroyuki Kunishima
IPC分类号： G03F1/00
CPC分类号： H01L23/5226 , G03F1/00 , G03F1/36 , H01L21/31144 , H01L21/76816 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： Provided is a reticle used for forming a plurality of vias for connecting first wirings provided in a first wiring layer and second wirings provided in a second wiring layer formed above the first wiring layer. The first wirings and the second wirings are provided along one of a first direction and a second direction, and the first direction and the second direction perpendicularly cross each other. The reticle includes a plurality of via opening patterns for forming the plurality of vias. Each of the plurality of via opening patterns has a rectangular shape, and is arranged to cause each side of each of the via opening patterns to be diagonal with respect to the first direction and the second direction.
摘要翻译：提供了一种用于形成用于连接设置在第一布线层中的第一配线的多个通孔的掩模版和设置在形成在第一布线层上的第二布线层中的第二布线。第一布线和第二布线沿第一方向和第二方向设置，第一方向和第二方向垂直交叉。掩模版包括用于形成多个通孔的多个通孔开口图案。多个通孔开口图案中的每一个具有矩形形状，并且被布置成使每个通孔开口图案的每一侧相对于第一方向和第二方向成对角线。

9. 发明授权

US07763968B2 Semiconductor device featuring large reinforcing elements in pad area 有权
标题翻译：半导体器件在焊盘区域具有大的增强元件
公开(公告)号：US07763968B2
公开(公告)日：2010-07-27
申请号：US11526572
申请日：2006-09-26
申请人： Hiroyuki Kunishima , Noriaki Oda
发明人： Hiroyuki Kunishima , Noriaki Oda
IPC分类号： H01L23/12 , H01L21/4763
CPC分类号： H01L24/05 , H01L23/528 , H01L2224/05093 , H01L2224/05624 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/13091 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00014 , H01L2924/00
摘要： In a semiconductor device, a plurality of interconnections are formed in an interconnection formation insulating interlayer, and a plurality of reinforcing elements are substantially evenly formed in blank areas of the interconnection insulating interlayer in which no interconnection is formed. A wire-bonding electrode pad is provided above the interconnection formation insulating interlayer so that a pad area, on which the wire-bonding electrode pad is projected, is defined on the interconnection formation insulating interlayer. A part of the reinforcing elements included in the pad area features a larger size than that of the remaining reinforcing elements.
摘要翻译：在半导体器件中，在互连形成绝缘中间层中形成多个互连，并且在互连绝缘中间层的不形成互连的空白区域中大致均匀地形成多个增强元件。在互连形成绝缘中间层上方设置引线接合电极焊盘，使得在互连形成绝缘中间层上限定引线接合电极焊盘的焊盘区域。包括在垫区域中的增强元件的一部分具有比剩余的增强元件的尺寸更大的尺寸。

10. 发明申请

US20070069388A1 Semiconductor device featuring large reinforcing elements in pad area, and pattern design apparatus therefor 有权
标题翻译：在垫区域中具有大的增强元件的半导体器件及其图案设计装置
公开(公告)号：US20070069388A1
公开(公告)日：2007-03-29
申请号：US11526572
申请日：2006-09-26
申请人： Hiroyuki Kunishima , Noriaki Oda
发明人： Hiroyuki Kunishima , Noriaki Oda
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L23/528 , H01L2224/05093 , H01L2224/05624 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/13091 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00014 , H01L2924/00
摘要： In a semiconductor device, a plurality of interconnections are formed in an interconnection formation insulating interlayer, and a plurality of reinforcing elements are substantially evenly formed in blank areas of the interconnection insulating interlayer in which no interconnection is formed. A wire-bonding electrode pad is provided above the interconnection formation insulating interlayer so that a pad area, on which the wire-bonding electrode pad is projected, is defined on the interconnection formation insulating interlayer. A part of the reinforcing elements included in the pad area features a larger size than that of the remaining reinforcing elements.
摘要翻译：在半导体器件中，在互连形成绝缘中间层中形成多个互连，并且在互连绝缘中间层的不形成互连的空白区域中大致均匀地形成多个增强元件。在互连形成绝缘中间层上方设置引线接合电极焊盘，使得在互连形成绝缘中间层上限定引线接合电极焊盘的焊盘区域。包括在垫区域中的增强元件的一部分具有比剩余的增强元件的尺寸更大的尺寸。

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