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1. 发明授权

US5896501A Multiprocessor system and parallel processing method for processing data transferred between processors 失效
标题翻译：用于处理数据之间传输的多处理器系统和并行处理方法
公开(公告)号：US5896501A
公开(公告)日：1999-04-20
申请号：US795689
申请日：1997-02-04
申请人： Masayuki Ikeda , Shigeru Nagasawa , Haruhiko Ueno , Naoki Shinjo , Teruo Utsumi , Kazushige Kobayakawa , Naoki Sueyasu , Kenichi Ishizaka , Masami Dewa , Moriyuki Takamura
发明人： Masayuki Ikeda , Shigeru Nagasawa , Haruhiko Ueno , Naoki Shinjo , Teruo Utsumi , Kazushige Kobayakawa , Naoki Sueyasu , Kenichi Ishizaka , Masami Dewa , Moriyuki Takamura
IPC分类号： G06F12/10 , G06F12/02 , G06F12/06 , G06F15/16 , G06F15/17 , G06F15/177 , G06F15/167
CPC分类号： G06F12/1072 , G06F12/0284 , G06F12/0692 , G06F15/17
摘要： A parallel processing apparatus and method for processing data transferred between a plurality of processors each having a storage. Each of the plurality of processors corresponds a global virtual address in a global virtual memory space where a parallel processing between the plurality of processors is performed and a local virtual address in a local virtual memory space where an individual process in one of the processors is performed to an identical real address. Data is transferred from a first one of the plurality of processors to a second one of the plurality of processors by writing the data into the storage of the second processor according to the global virtual address or the local virtual address of the second processor, the second processor is notified of the global virtual address or the local virtual address of the transferred data, the notified global virtual address or the notified local virtual address is then translated into the real address which corresponds to the notified global virtual address or the notified local virtual address, data is read from the storage of the second processor to the second processor according to the translated real address, and the read data is calculated in the second processor.
摘要翻译：一种用于处理在具有存储器的多个处理器之间传送的数据的并行处理装置和方法。多个处理器中的每一个对应于全局虚拟存储器空间中的全局虚拟地址，其中执行多个处理器之间的并行处理以及执行其中一个处理器中的单独进程的本地虚拟存储器空间中的本地虚拟地址到相同的真实地址。通过根据第二处理器的全局虚拟地址或本地虚拟地址将数据写入第二处理器的存储器中，将数据从多个处理器中的第一处理器传送到多个处理器中的第二处理器，第二处理器处理器被通知全局虚拟地址或传送数据的本地虚拟地址，然后将所通知的全局虚拟地址或通知的本地虚拟地址转换成对应于通知的全局虚拟地址或通知的本地虚拟地址的实际地址根据转换的实际地址将数据从第二处理器的存储器读取到第二处理器，并且在第二处理器中计算读取的数据。

2. 发明授权

US5634071A Synchronous processing method and apparatus for a plurality of processors executing a plurality of programs in parallel 失效
标题翻译：用于并行执行多个程序的多个处理器的同步处理方法和装置
公开(公告)号：US5634071A
公开(公告)日：1997-05-27
申请号：US601705
申请日：1996-02-15
申请人： Masami Dewa , Shigeru Nagasawa , Masayuki Ikeda , Haruhiko Ueno , Naoki Shinjo , Teruo Utsumi , Kazushige Kobayakawa , Kenichi Ishizaka , Moriyuki Takamura
发明人： Masami Dewa , Shigeru Nagasawa , Masayuki Ikeda , Haruhiko Ueno , Naoki Shinjo , Teruo Utsumi , Kazushige Kobayakawa , Kenichi Ishizaka , Moriyuki Takamura
IPC分类号： G06F15/16 , G06F9/45 , G06F9/52 , G06F15/177 , G06F9/00
CPC分类号： G06F8/458
摘要： A synchronous processing system including a plurality of processors and a communications network. Each processor includes a synchronization combination storage element, status storage element, control element, judging element and shifting element. The synchronization combination storage element stores synchronization combination information showing a group of the processors being synchronized during the parallel execution of a program. The synchronous status storage element stores synchronous status information indicating that a synchronous waiting status is reached after the processor has finished its processing. A storage control element transmits the synchronous status information to all other processors. A judging element judges whether the group of processors are in synchronism based on the synchronization combination information and the transmitted status information. A processing shifting element shifts, when the group of processors are judged to be in synchronism, all the processors in the group to the next process of a program.
摘要翻译：一种包括多个处理器和通信网络的同步处理系统。每个处理器包括同步组合存储元件，状态存储元件，控制元件，判断元件和移位元件。同步组合存储单元存储表示在并行执行程序期间同步的一组处理器的同步组合信息。同步状态存储单元存储指示在处理器完成其处理之后到达同步等待状态的同步状态信息。存储控制元件将同步状态信息发送到所有其他处理器。判断单元基于同步组合信息和所发送的状态信息来判断处理器组是否同步。当处理器组被判断为同步时，处理移位元件移动到组中的所有处理器到程序的下一个处理。

3. 发明授权

US4631725A Error correcting and detecting system 失效
标题翻译：错误校正和检测系统
公开(公告)号：US4631725A
公开(公告)日：1986-12-23
申请号：US686815
申请日：1984-12-27
申请人： Moriyuki Takamura , Shigeru Mukasa , Takashi Ibi
发明人： Moriyuki Takamura , Shigeru Mukasa , Takashi Ibi
IPC分类号： G06F11/10 , H03M13/00 , H03M13/19
CPC分类号： G06F11/1028 , H03M13/19
摘要： An error correcting and detecting system using a parity check H-matrix divided into a plurality of block vectors each including four or three column vectors each having eight elements. In the H-matrix, (i) there are no all "0" vectors; (ii) all column vectors are different from each other; (iii) 8 column vectors each having only one "1" is included therein, (iv) each column vector has an odd number of "1's"; (v) the modulo-2 sum of any three column vectors within any block never equals any column vectors of the H-matrix; (vi) the modulo-2 sum of four column vectors within any block never equals an all "0" vector; and (vii) the modulo-2 sum of eight column vectors within any two blocks never equals an all "0" vector.
摘要翻译：使用奇偶校验H矩阵的纠错和检测系统，该奇偶校验H矩阵被分成多个块向量，每个块向量包括每个具有八个元素的四个或三个列向量。在H矩阵中，（i）没有全部“0”向量; （ii）所有列向量彼此不同; （iii）其中包括每个仅具有一个“1”的8个列向量，（iv）每个列向量具有奇数个“1”; （v）任何块中任何三列向量的模-2之和不等于H矩阵的任何列向量; （vi）任何块内的四列向量的模-2之和不等于全“0”向量; 和（vii）任何两个块中的八个列向量的模-2之和从不等于全“0”向量。

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