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1. 发明授权

US07505355B2 Semiconductor memory device with MOS transistors each having floating gate and control gate 有权
标题翻译：具有MOS晶体管的半导体存储器件分别具有浮动栅极和控制栅极
公开(公告)号：US07505355B2
公开(公告)日：2009-03-17
申请号：US11733796
申请日：2007-04-11
申请人： Kazushige Kanda , Akira Umezawa , Kazuhiko Kakizoe , Yoshiaki Hashiba , Yoshiharu Hirata
发明人： Kazushige Kanda , Akira Umezawa , Kazuhiko Kakizoe , Yoshiaki Hashiba , Yoshiharu Hirata
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/08 , G11C11/005 , G11C16/0425 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , H01L27/115
摘要： A semiconductor memory device includes a memory cell array, word lines, and a row decoder. The memory cell array includes memory cells arranged in a matrix. The memory cell includes a first MOS transistor having a charge accumulation layer and a control gate and a second MOS transistor. The word line connects the control gates of the first MOS transistors. The row decoder includes a first address decode circuit, a second address decode circuit, and a transfer gate. The first address decode circuit decodes m bits in a n-bit row address signal (m and n are a natural number satisfying the expression m
摘要翻译：半导体存储器件包括存储单元阵列，字线和行解码器。存储单元阵列包括排列成矩阵的存储单元。存储单元包括具有电荷累积层的第一MOS晶体管和控制栅极和第二MOS晶体管。字线连接第一MOS晶体管的控制栅极。行解码器包括第一地址解码电路，第二地址解码电路和传输门。第一地址解码电路解码n位行地址信号中的m位（m和n是满足表达式m

2. 发明申请

US20070201299A1 SEMICONDUCTOR MEMORY DEVICE WITH MOS TRANSISTORS EACH HAVING FLOATING GATE AND CONTROL GATE 有权
标题翻译：具有浮动门和控制门的MOS晶体管的半导体存储器件
公开(公告)号：US20070201299A1
公开(公告)日：2007-08-30
申请号：US11733796
申请日：2007-04-11
申请人： Kazushige Kanda , Akira Umezawa , Kazuhiko Kakizoe , Yoshiaki Hashiba , Yoshiharu Hirata
发明人： Kazushige Kanda , Akira Umezawa , Kazuhiko Kakizoe , Yoshiaki Hashiba , Yoshiharu Hirata
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/08 , G11C11/005 , G11C16/0425 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , H01L27/115
摘要： A semiconductor memory device includes a memory cell array, word lines, and a row decoder. The memory cell array includes memory cells arranged in a matrix. The memory cell includes a first MOS transistor having a charge accumulation layer and a control gate and a second MOS transistor. The word line connects the control gates of the first MOS transistors. The row decoder includes a first address decode circuit, a second address decode circuit, and a transfer gate. The first address decode circuit decodes m bits in a n-bit row address signal (m and n are a natural number satisfying the expression m
摘要翻译：半导体存储器件包括存储单元阵列，字线和行解码器。存储单元阵列包括排列成矩阵的存储单元。存储单元包括具有电荷累积层的第一MOS晶体管和控制栅极和第二MOS晶体管。字线连接第一MOS晶体管的控制栅极。行解码器包括第一地址解码电路，第二地址解码电路和传输门。第一地址解码电路解码n位行地址信号中的m位（m和n是满足表达式m

3. 发明授权

US07120057B2 Semiconductor memory device with a stacked gate including a floating gate and a control gate 有权
公开(公告)号：US07120057B2
公开(公告)日：2006-10-10
申请号：US11016804
申请日：2004-12-21
申请人： Akira Umezawa , Kazuhiko Kakizoe
发明人： Akira Umezawa , Kazuhiko Kakizoe
IPC分类号： G11C16/04
CPC分类号： H01L27/105 , G11C11/005 , G11C16/0433 , G11C16/0483 , G11C16/08 , H01L27/0629 , H01L27/092 , H01L27/11531
摘要： A semiconductor memory device comprises a first to a fourth semiconductor layer of a first conductivity type which are formed in a fifth semiconductor layer of a second conductivity type in such a manner that they are isolated from one another, memory cells each of which includes a first MOS transistor formed on the first semiconductor layer, a second and a third MOS transistor which are formed on the second and third semiconductor layers, respectively, a first metal wiring layer which connects the gate of the first MOS transistor to the source or drain of at least one of the second and third MOS transistors, and a first contact plug which connects the fourth semiconductor layer to the first metal wiring layer. The first wiring layer is in the lowest layer of the metal wiring lines connected to the gate of the first MOS transistor.

4. 发明申请

US20070020852A1 SEMICONDUCTOR MEMORY DEVICE WITH A STACKED GATE INCLUDING A FLOATING GATE AND A CONTROL GATE 有权
标题翻译：具有包括浮动门和控制门的堆叠门的半导体存储器件
公开(公告)号：US20070020852A1
公开(公告)日：2007-01-25
申请号：US11533051
申请日：2006-09-19
申请人： Akira Umezawa , Kazuhiko Kakizoe
发明人： Akira Umezawa , Kazuhiko Kakizoe
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , G11C11/005 , G11C16/0433 , G11C16/0483 , G11C16/08 , H01L27/0629 , H01L27/092 , H01L27/11531
摘要： A semiconductor memory device comprises a first to a fourth semiconductor layer of a first conductivity type which are formed in a fifth semiconductor layer of a second conductivity type in such a manner that they are isolated from one another, memory cells each of which includes a first MOS transistor formed on the first semiconductor layer, a second and a third MOS transistor which are formed on the second and third semiconductor layers, respectively, a first metal wiring layer which connects the gate of the first MOS transistor to the source or drain of at least one of the second and third MOS transistors, and a first contact plug which connects the fourth semiconductor layer to the first metal wiring layer. The first wiring layer is in the lowest layer of the metal wiring lines connected to the gate of the first MOS transistor.
摘要翻译：半导体存储器件包括第一导电类型的第一至第四半导体层，它们以彼此隔离的方式形成在第二导电类型的第五半导体层中，每个存储单元包括第一形成在第一半导体层上的MOS晶体管，分别形成在第二和第三半导体层上的第二和第三MOS晶体管，分别将第一MOS晶体管的栅极连接到源极或漏极的第一金属布线层第二和第三MOS晶体管中的至少一个以及将第四半导体层连接到第一金属布线层的第一接触插塞。第一布线层位于与第一MOS晶体管的栅极连接的金属布线的最下层。

5. 发明申请

US20050195636A1 Semiconductor memory device with a stacked gate including a floating gate and a control gate 有权
标题翻译：具有包括浮动栅极和控制栅极的堆叠栅极的半导体存储器件
公开(公告)号：US20050195636A1
公开(公告)日：2005-09-08
申请号：US11016804
申请日：2004-12-21
申请人： Akira Umezawa , Kazuhiko Kakizoe
发明人： Akira Umezawa , Kazuhiko Kakizoe
IPC分类号： H01L21/822 , G11C11/24 , H01L21/8234 , H01L21/8247 , H01L27/04 , H01L27/088 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/105 , G11C11/005 , G11C16/0433 , G11C16/0483 , G11C16/08 , H01L27/0629 , H01L27/092 , H01L27/11531
摘要： A semiconductor memory device comprises a first to a fourth semiconductor layer of a first conductivity type which are formed in a fifth semiconductor layer of a second conductivity type in such a manner that they are isolated from one another, memory cells each of which includes a first MOS transistor formed on the first semiconductor layer, a second and a third MOS transistor which are formed on the second and third semiconductor layers, respectively, a first metal wiring layer which connects the gate of the first MOS transistor to the source or drain of at least one of the second and third MOS transistors, and a first contact plug which connects the fourth semiconductor layer to the first metal wiring layer. The first wiring layer is in the lowest layer of the metal wiring lines connected to the gate of the first MOS transistor.
摘要翻译：半导体存储器件包括第一导电类型的第一至第四半导体层，它们以彼此隔离的方式形成在第二导电类型的第五半导体层中，每个存储单元包括第一形成在第一半导体层上的MOS晶体管，分别形成在第二和第三半导体层上的第二和第三MOS晶体管，分别将第一MOS晶体管的栅极连接到源极或漏极的第一金属布线层第二和第三MOS晶体管中的至少一个以及将第四半导体层连接到第一金属布线层的第一接触插塞。第一布线层位于与第一MOS晶体管的栅极连接的金属布线的最下层。

6. 发明授权

US07505324B2 Semiconductor memory device with a stacked gate including a floating gate and a control gate 有权
标题翻译：具有包括浮动栅极和控制栅极的堆叠栅极的半导体存储器件
公开(公告)号：US07505324B2
公开(公告)日：2009-03-17
申请号：US11533051
申请日：2006-09-19
申请人： Akira Umezawa , Kazuhiko Kakizoe
发明人： Akira Umezawa , Kazuhiko Kakizoe
IPC分类号： G11C16/04
CPC分类号： H01L27/105 , G11C11/005 , G11C16/0433 , G11C16/0483 , G11C16/08 , H01L27/0629 , H01L27/092 , H01L27/11531
摘要： A semiconductor memory device comprises a first to a fourth semiconductor layer of a first conductivity type which are formed in a fifth semiconductor layer of a second conductivity type in such a manner that they are isolated from one another, memory cells each of which includes a first MOS transistor formed on the first semiconductor layer, a second and a third MOS transistor which are formed on the second and third semiconductor layers, respectively, a first metal wiring layer which connects the gate of the first MOS transistor to the source or drain of at least one of the second and third MOS transistors, and a first contact plug which connects the fourth semiconductor layer to the first metal wiring layer. The first wiring layer is in the lowest layer of the metal wiring lines connected to the gate of the first MOS transistor.
摘要翻译：半导体存储器件包括第一导电类型的第一至第四半导体层，它们以彼此隔离的方式形成在第二导电类型的第五半导体层中，每个存储单元包括第一形成在第一半导体层上的MOS晶体管，分别形成在第二和第三半导体层上的第二和第三MOS晶体管，分别将第一MOS晶体管的栅极连接到源极或漏极的第一金属布线层第二和第三MOS晶体管中的至少一个以及将第四半导体层连接到第一金属布线层的第一接触插塞。第一布线层位于与第一MOS晶体管的栅极连接的金属布线的最下层。

7. 发明授权

US5210436A Semiconductor device with input protection circuit of high withstand voltage 失效
标题翻译：具有高耐压输入保护电路的半导体器件
公开(公告)号：US5210436A
公开(公告)日：1993-05-11
申请号：US725070
申请日：1991-07-05
申请人： Kazuhiko Kakizoe , Hiroaki Murakami
发明人： Kazuhiko Kakizoe , Hiroaki Murakami
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8234 , H01L21/8247 , H01L27/02 , H01L27/088 , H01L27/115 , H01L29/78
CPC分类号： H01L27/0266
摘要： A semiconductor device equipped with an input protection circuit having a high withstand voltage and an improved reliability. The input protection circuit of the semiconductor device includes a gate insulation film provided on the semiconductor substrate corresponding to a region between the source region and the drain region, having a thickness greater than that of a gate insulation film in the FET of the semiconductor device, where one of the source region and the drain region is connected with an external input terminal for the semiconductor device, while the gate electrode and the other one of the source region and the drain region are connected with a power source for the semiconductor device.

8. 发明授权

US06188610B1 Electrically erasable and programmable nonvolatile semiconductor memory device having data holding function and data holding method 失效
标题翻译：具有数据保持功能和数据保持方法的电可擦除和可编程的非易失性半导体存储器件
公开(公告)号：US06188610B1
公开(公告)日：2001-02-13
申请号：US09497175
申请日：2000-02-03
申请人： Kazuhiko Kakizoe , Toru Okawa
发明人： Kazuhiko Kakizoe , Toru Okawa
IPC分类号： G11C700
CPC分类号： G11C16/3431 , G11C16/3418
摘要： Data of a memory cell in a cell array is read out by a readout circuit by use of a word line potential which is the same as that at the program verify time. After the end of the readout operation, data of the same memory cell is read out by the readout circuit by use of a word line potential (refresh verify potential) which is lower than the word line potential at the program verify time and higher than the word line potential at the read time. Then, data read out by use of the word line potential which is the same as that at the program verify time is compared with data read out by use of the word line potential which is set at the refresh verify potential and whether or not the additional write operation for holding data is effected for the memory cell is determined according to the result of comparison.
摘要翻译：通过使用与程序验证时间相同的字线电位，由读出电路读出单元阵列中的存储单元的数据。在读出操作结束之后，通过使用在程序验证时间比字线电位低的字线电位（刷新验证电位），由读出电路读出同一个存储单元的数据，高于读取时的字线电位。然后，将通过使用与程序验证时间相同的字线电位读出的数据与通过设置在刷新验证电位的字线电位读出的数据进行比较，以及附加根据比较结果确定存储单元的保持数据的写操作。

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