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1. 发明授权

US06697906B1 Semiconductor device supporting integrated data transfer bridging between CPU memory and I/O device 有权
标题翻译：半导体器件支持CPU内存和I / O设备之间的集成数据传输桥接
公开(公告)号：US06697906B1
公开(公告)日：2004-02-24
申请号：US09561340
申请日：2000-04-28
申请人： Kazushige Ayukawa , Jun Sato , Takashi Miyamoto , Kenichiro Omura , Hiroyuki Hamasaki , Hiroshi Takeda , Makoto Takano , Isamu Mochizuki , Yasuhiko Hoshi , Kazuhiro Hirade , Ryuichi Murashima
发明人： Kazushige Ayukawa , Jun Sato , Takashi Miyamoto , Kenichiro Omura , Hiroyuki Hamasaki , Hiroshi Takeda , Makoto Takano , Isamu Mochizuki , Yasuhiko Hoshi , Kazuhiro Hirade , Ryuichi Murashima
IPC分类号： G06F100
CPC分类号： G06F13/4031
摘要： A semiconductor device is connected to a CPU, a memory and I/O devices to serve as a data transfer bridge for efficient data transfer between the memory and the I/O devices. A CPU interface and a plurality of I/O interfaces included in a bridge chip are connected through an internal bus to a memory interface included in the bridge chip. Each I/O interface has a read/write buffer and a DMAC. An arbiter included in the bridge chip determines a bus master for which data transfer is permitted in response to requests for data transfer from each of the CPU interface and the DMAC to the memory. Each of the I/O interfaces has a control function to skip part of areas in the memory when transferring data between the memory and the I/O interface.
摘要翻译：半导体器件连接到CPU，存储器和I / O设备以用作用于在存储器和I / O设备之间进行有效数据传输的数据传输桥。包括在桥芯片中的CPU接口和多个I / O接口通过内部总线连接到包括在桥芯片中的存储器接口。每个I / O接口都有一个读/写缓冲区和一个DMAC。包括在桥芯片中的仲裁器确定响应于从CPU接口和DMAC到存储器的数据传输的请求而允许数据传输的总线主机。当在存储器和I / O接口之间传输数据时，每个I / O接口都具有一个控制功能来跳过存储器中的一部分区域。

2. 发明授权

US6091863A Image processor and data processing system using the same processor 失效
标题翻译：图像处理器和数据处理系统使用相同的处理器
公开(公告)号：US6091863A
公开(公告)日：2000-07-18
申请号：US523509
申请日：1995-09-01
申请人： Keisuke Nakashima , Jun Satoh , Kazushige Yamagishi , Takashi Miyamoto , Kenichiro Omura , Koyo Katsura , Mitsuru Watabe
发明人： Keisuke Nakashima , Jun Satoh , Kazushige Yamagishi , Takashi Miyamoto , Kenichiro Omura , Koyo Katsura , Mitsuru Watabe
IPC分类号： G09G5/00 , G06F12/00 , G06T1/20 , G06T11/00 , G06T15/04 , G06K9/36 , G06F15/00 , G06K9/54
CPC分类号： G06T1/20
摘要： An image processor which is connected to a system bus that connects a processor for forming graphic command related to image processing to a main memory that holds command and original image data, and draws image on the frame buffer based upon said graphic command from said processor, wherein said graphic processor has a data bus change-over unit which connects said system bus to a first data bus that is connected to a graphic data memory holding said graphic command and said original image data, or connects said first data bus to a frame buffer which holds the data to be displayed. The image processor realizes a high-speed processing at a reduced cost by using a graphic memory bus coupled to a graphic processor.
摘要翻译：一种图像处理器，其连接到系统总线，该系统总线将用于形成与图像处理有关的图形命令的处理器连接到保存命令和原始图像数据的主存储器，并且基于来自所述处理器的所述图形命令在所述帧缓冲器上绘制图像，其中所述图形处理器具有数据总线转换单元，其将所述系统总线连接到连接到保存所述图形命令和所述原始图像数据的图形数据存储器的第一数据总线，或将所述第一数据总线连接到帧缓冲器它保存要显示的数据。图像处理器通过使用耦合到图形处理器的图形存储器总线以低成本实现高速处理。

3. 发明授权

US07327371B2 Graphic controller, microcomputer and navigation system 有权
标题翻译：图形控制器，微型计算机和导航系统
公开(公告)号：US07327371B2
公开(公告)日：2008-02-05
申请号：US10716459
申请日：2003-11-20
申请人： Atsushi Nakamura , Kenichiro Omura
发明人： Atsushi Nakamura , Kenichiro Omura
IPC分类号： G06T1/60 , G09G5/39 , G09G5/399 , G06F13/28 , G06F3/038
CPC分类号： G09G5/363 , G09G5/397 , G09G2320/0247 , G09G2340/02
摘要： Image data storage areas of a plurality of pages are allocated for each of a plurality of display planes capable of superimposed display, and display output processing is performed while switching between the image data storage areas is being performed for each display plane. In such a display system, versatile switching between image data storage areas is enabled without heavily loading a central processing unit. Attribute bits of a TRAP command indicating the termination of drawing of one display plane are provided with display switching enable bits indicating whether to perform switching between image data storage areas for each display plane. For display planes corresponding to the display switching enable bits of “1”, switching to an image data storage area from which image data is read is performed at timing synchronous with a next vertical synchronous signal.
摘要翻译：为能够叠加显示的多个显示平面中的每一个分配多页的图像数据存储区域，并且在为每个显示平面执行图像数据存储区域之间切换的同时执行显示输出处理。在这种显示系统中，能够在不大量加载中央处理单元的情况下启用图像数据存储区域之间的通用切换。指示终止一个显示平面的TRAP命令的属性位被提供有指示是否在每个显示平面的图像数据存储区域之间进行切换的显示切换使能位。对于与“1”的显示切换使能位相对应的显示平面，切换到与下一个垂直同步信号同步的定时从其读取图像数据的图像数据存储区域。

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