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1. 发明授权

US06868514B2 FEC frame structuring method and FEC multiplexer 失效
标题翻译： FEC帧结构方法和FEC多路复用器
公开(公告)号：US06868514B2
公开(公告)日：2005-03-15
申请号：US09890858
申请日：2000-12-06
申请人： Kazuo Kubo , Hideo Yoshida , Hiroshi Ichibangase , Hidenori Taga , Eiichi Shibano , Tadami Yasuda
发明人： Kazuo Kubo , Hideo Yoshida , Hiroshi Ichibangase , Hidenori Taga , Eiichi Shibano , Tadami Yasuda
IPC分类号： H03M13/15 , H03M13/27 , H03M13/29 , H04J3/00 , H04L1/00
CPC分类号： H03M13/2921 , H03M13/15 , H03M13/1515 , H03M13/2721 , H03M13/6561
摘要： In an FEC frame structuring method, and an FEC multiplexer, the order of information is changed by a first interleaving circuit 32, a first error correction code is generated by an RS (239, 223) coding circuit 33, the order is returned to the original order by a first deinterleaving circuit 34, and a second error correction code is generated by an RS (255, 239) coding means 5. The second error correction code is decoded by an RS (255, 239) decoding circuit 11 to correct errors in the information, the order of information is changed by a second interleaving circuit 35, the first error correction code is decoded by an RS (239, 223) decoding circuit 36 to correct residual errors in the information, and the order is returned to the original order by a second deinterleaving circuit 37.
摘要翻译：在FEC帧结构方法和FEC多路复用器中，由第一交织电路32改变信息的顺序，由RS（239,223）编码电路33生成第一纠错码，顺序返回到通过第一去交织电路34的原始顺序，并且由RS（255,239）编码装置5产生第二纠错码。第二纠错码由RS（255,239）解码电路11解码以校正错误在信息中，通过第二交错电路35改变信息的顺序，由RS（239,223）解码电路36对第一纠错码进行解码，以校正信息中的残差，并将顺序返回到通过第二去交织电路37的原始顺序。

2. 发明授权

US07043162B2 Optical transmission system, fec multiplexer, fec multiplexer/separator, and error correction method 失效
标题翻译：光传输系统，fec多路复用器，fec多路复用器/分离器和纠错方法
公开(公告)号：US07043162B2
公开(公告)日：2006-05-09
申请号：US10031235
申请日：2001-05-16
申请人： Kazuo Kubo , Hideo Yoshida , Hiroshi Ichibangase
发明人： Kazuo Kubo , Hideo Yoshida , Hiroshi Ichibangase
IPC分类号： H04B10/00
CPC分类号： H03M13/29 , H03M13/03 , H03M13/15 , H03M13/1515 , H03M13/2909 , H04L1/0041 , H04L1/005 , H04L1/0057 , H04L1/0066 , H04L1/0071
摘要： An FEC multiplexing circuit (2) has a configuration in which a first memory circuit (15) is arranged on the input stage of a first RS encoding circuit (16), a second memory circuit (17) is arranged on the input stage of a second RS encoding circuit (18), error correction encoding is performed by a combination of different data having two directions, and thereafter, error correction codes are multiplexed to generate an FEC frame. On the other hand, an FEC demultiplexing circuit (6) has a configuration in which a third memory circuit (42) is arranged on the output stage of a first RS decoding circuit (41), a fourth memory circuit (44) is arranged on the output stage of a second RS decoding circuit (43), error correction is performed by a combination of different data having two directions, and, thereafter, parallel data read from the fourth memory circuit (44) are multiplexed to reproduce original information data.
摘要翻译： FEC复用电路（2）具有第一存储器电路（15）布置在第一RS编码电路（16）的输入级上的配置，第二存储器电路（17）布置在输入级第二RS编码电路（18），通过具有两个方向的不同数据的组合来执行纠错编码，然后对纠错码进行多路复用以产生FEC帧。另一方面，FEC解复用电路（6）具有第三存储电路（42）配置在第一RS解码电路（41）的输出级上的结构，第四存储电路（44）配置在通过具有两个方向的不同数据的组合来执行第二RS解码电路（43）的输出级，然后对从第四存储器电路（44）读取的并行数据进行多路复用以再现原始信息数据。

3. 发明授权

US07992069B2 Error correction coding apparatus and error correction decoding apparatus 有权
标题翻译：纠错编码装置和纠错解码装置
公开(公告)号：US07992069B2
公开(公告)日：2011-08-02
申请号：US11883958
申请日：2006-02-03
申请人： Yoshikuni Miyata , Hideo Yoshida , Kazuo Kubo
发明人： Yoshikuni Miyata , Hideo Yoshida , Kazuo Kubo
IPC分类号： H03M13/00
CPC分类号： H03M13/2906 , H03M13/134 , H04L1/0041 , H04L1/0057 , H04L1/0064 , H04L1/0083
摘要： An error correction coding apparatus divides transmission information sequences in n subframes (n is an arbitrary natural number) into n1 subframes (n1 is a natural number
摘要翻译：纠错编码装置将n个子帧（n为任意自然数）中的发送信息序列分割为n1个子帧（n1为自然数

4. 发明授权

US06658605B1 Multiple coding method and apparatus, multiple decoding method and apparatus, and information transmission system 有权
标题翻译：多重编码方法和装置，多重解码方法和装置以及信息传输系统
公开(公告)号：US06658605B1
公开(公告)日：2003-12-02
申请号：US09703638
申请日：2000-11-02
申请人： Hideo Yoshida , Takahiko Nakamura , Hachiro Fujita , Yoshikuni Miyata , Kazuo Kubo
发明人： Hideo Yoshida , Takahiko Nakamura , Hachiro Fujita , Yoshikuni Miyata , Kazuo Kubo
IPC分类号： G11C2900
CPC分类号： H03M7/30 , H03M13/15 , H03M13/1515 , H03M13/2707 , H03M13/2721 , H03M13/29 , H03M13/6561
摘要： A multiple coding apparatus comprises a first encoder for encoding a plurality of input sequences in parallel so as to generate a plurality of output coded sequences in parallel while adding an error-correcting bit sequence to each of the plurality of input sequences. An interleaving circuit interleaves the plurality of output coded sequences applied thereto in parallel from the first encoder without having to use any memory. The interleaving circuit permutes the plurality of input sequences on a bit-by-bit or symbol-by-symbol basis so as to generate a plurality of interleaved coded sequences in parallel. A second encoder then encodes the plurality of interleaved coded sequences applied thereto in parallel from the interleaving circuit so as to generate a plurality of output coded sequences in parallel while adding an error-correcting bit sequence to each of the plurality of interleaved coded sequences.
摘要翻译：多重编码装置包括：并行地编码多个输入序列的第一编码器，以便并行地产生多个输出编码序列，同时向多个输入序列中的每个输入序列添加纠错位序列。交织电路将从第一编码器并行地施加到其上的多个输出编码序列进行交织，而不必使用任何存储器。交织电路逐位或逐符号地排列多个输入序列，以便并行地生成多个交错编码序列。然后，第二编码器对从交织电路并行施加到其上的多个交错编码序列进行编码，以便并行地产生多个输出编码序列，同时向多个交错编码序列中的每一个添加纠错位序列。

5. 发明授权

US09081677B2 Method and device for estimating input bit error ratio 有权
标题翻译：用于估计输入误码率的方法和装置
公开(公告)号：US09081677B2
公开(公告)日：2015-07-14
申请号：US13982403
申请日：2012-02-20
申请人： Yoshikuni Miyata , Kenya Sugihara , Kiyoshi Onohara , Kazuo Kubo , Hideo Yoshida , Takashi Mizuochi
发明人： Yoshikuni Miyata , Kenya Sugihara , Kiyoshi Onohara , Kazuo Kubo , Hideo Yoshida , Takashi Mizuochi
IPC分类号： G06F11/07 , H04L1/20
CPC分类号： G06F11/076 , H04L1/203
摘要： An input bit error ratio estimating method executed by a communication control unit includes a computing, a condition determining, a first input BER estimating, a second input BER estimating, a third input BER estimating, and an input BER estimation result outputting. In the condition determining, the communication control unit determines which of a plurality of conditions set in advance to be narrowed down to one has been established, based on a post-internal decoding residual error detection ratio. Based on the condition that is determined in the condition determining as one that has been established, the communication control unit selects one out of a plurality of processing procedures for estimating the input BER, namely, selects one of the first input BER estimating to the third input BER estimating and executes the selected processing.
摘要翻译：由通信控制单元执行的输入误码率估计方法包括计算，条件确定，第一输入BER估计，第二输入BER估计，第三输入BER估计和输入BER估计结果输出。在所述条件判定中，所述通信控制部基于所述内部解码剩余错误检测率，确定预先设定为被缩小为一个的条件中的哪一个已被建立。基于在确定为已经建立的条件中确定的条件，通信控制单元从用于估计输入BER的多个处理过程中选择一个，即，选择第三输入BER中的一个，输入BER估计并执行所选择的处理。

6. 发明授权

US08621316B2 Method and device for encoding of error correcting codes, and method and device for decoding of error correcting codes 有权
标题翻译：用于纠错码编码的方法和装置，以及用于解码纠错码的方法和装置
公开(公告)号：US08621316B2
公开(公告)日：2013-12-31
申请号：US12987368
申请日：2011-01-10
申请人： Yoshikuni Miyata , Hideo Yoshida , Kazuo Kubo , Takashi Mizuochi
发明人： Yoshikuni Miyata , Hideo Yoshida , Kazuo Kubo , Takashi Mizuochi
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： H04L1/0071 , H03M13/1102 , H03M13/1515 , H03M13/152 , H03M13/23 , H03M13/271 , H03M13/29 , H03M13/2945 , H03M13/2957 , H03M13/2963 , H03M13/356 , H03M13/6561 , H03M13/6577 , H04L1/0065
摘要： An error correction encoding device includes an outer encoding circuit that performs encoding processing for an outer code and an inner encoding circuit that performs encoding processing for an inner code. The inner encoding circuit includes an inner-encoding input circuit that performs interleaving processing in which a parallel input sequence is divided into lanes and in which a barrel shift is performed for each inner frame in the lanes. Thus, allocation ratios between an information sequence area and a parity sequence area are made uniform.
摘要翻译：纠错编码装置包括对外部码进行编码处理的外部编码电路和对内部码进行编码处理的内部编码电路。内部编码电路包括内部编码输入电路，其执行交织处理，其中并行输入序列被划分为通道，并且其中对车道中的每个内部框架执行桶形移位。因此，使信息序列区域和奇偶序列区域之间的分配比率一致。

7. 发明申请

US20130311847A1 ERROR CORRECTION CODING DEVICE, ERROR CORRECTION DECODING DEVICE AND METHOD THEREFOR 有权
标题翻译：错误校正编码装置，错误校正解码装置及其方法
公开(公告)号：US20130311847A1
公开(公告)日：2013-11-21
申请号：US13982919
申请日：2012-05-30
申请人： Yoshikuni Miyata , Wataru Matsumoto , Hideo Yoshida , Kazuo Kubo
发明人： Yoshikuni Miyata , Wataru Matsumoto , Hideo Yoshida , Kazuo Kubo
IPC分类号： H03M13/29
CPC分类号： H03M13/29 , H03M13/1102 , H03M13/1145 , H03M13/152 , H03M13/2909 , H03M13/356
摘要： Provided is an error correction encoder that performs coding on both a transmission area and a redundancy area of the transmission frame by using a product code, and when excess or deficiency is arisen with respect to allocation of an information sequence area and/or a parity sequence area in a product code frame generated by the coding using the product code, non-uniformly allocate the information sequence area to the parity sequence area, and/or non-uniformly allocate the parity sequence area to the information sequence area, where each of the non-uniform allocations is performed in accordance with the arisen excess or deficiency.
摘要翻译：提供了一种纠错编码器，其通过使用产品代码对发送帧的发送区域和冗余区域两者进行编码，并且当相对于信息序列区域和/或奇偶校验序列的分配产生过多或不足时通过使用产品代码的编码生成的商品代码帧中的区域，将信息序列区域均匀地分配给奇偶校验序列区域，和/或非均匀地将奇偶校验序列区域分配给信息序列区域，其中，根据发生的过量或不足，进行非均匀分配。

8. 发明授权

US09148175B2 Error correction coding device, error correction decoding device and method therefor 有权
标题翻译：纠错编码装置，纠错解码装置及其方法
公开(公告)号：US09148175B2
公开(公告)日：2015-09-29
申请号：US13982919
申请日：2012-05-30
申请人： Yoshikuni Miyata , Wataru Matsumoto , Hideo Yoshida , Kazuo Kubo
发明人： Yoshikuni Miyata , Wataru Matsumoto , Hideo Yoshida , Kazuo Kubo
IPC分类号： H03M13/00 , H03M13/29 , H03M13/11 , H03M13/35 , H03M13/15
CPC分类号： H03M13/29 , H03M13/1102 , H03M13/1145 , H03M13/152 , H03M13/2909 , H03M13/356
摘要： Provided is an error correction encoder that performs coding on both a transmission area and a redundancy area of the transmission frame by using a product code, and when excess or deficiency is arisen with respect to allocation of an information sequence area and/or a parity sequence area in a product code frame generated by the coding using the product code, non-uniformly allocate the information sequence area to the parity sequence area, and/or non-uniformly allocate the parity sequence area to the information sequence area, where each of the non-uniform allocations is performed in accordance with the arisen excess or deficiency.
摘要翻译：提供了一种纠错编码器，其通过使用产品代码对发送帧的发送区域和冗余区域两者进行编码，并且当相对于信息序列区域和/或奇偶校验序列的分配产生过多或不足时通过使用产品代码的编码生成的商品代码帧中的区域，将信息序列区域均匀地分配给奇偶校验序列区域，和/或非均匀地将奇偶校验序列区域分配给信息序列区域，其中，根据发生的过量或不足，进行非均匀分配。

9. 发明授权

US08977927B2 Error-correction coding method, error-correction decoding method, error-correction coding apparatus, and error-correction decoding apparatus 有权
标题翻译：纠错编码方法，纠错解码方法，纠错编码装置和纠错解码装置
公开(公告)号：US08977927B2
公开(公告)日：2015-03-10
申请号：US12778618
申请日：2010-05-12
申请人： Yoshikuni Miyata , Hideo Yoshida , Kazuo Kubo , Takashi Mizuochi
发明人： Yoshikuni Miyata , Hideo Yoshida , Kazuo Kubo , Takashi Mizuochi
IPC分类号： H03M13/00 , H03M13/29
CPC分类号： H03M13/29
摘要： An error-correction coding method that includes outer coding of performing a coding process for an outer code; and inner coding of performing a coding process for an inner code that has an error correction capability adjusted based on an error correction capability of the outer code.
摘要翻译：一种纠错编码方法，包括对外部码进行编码处理的外部编码; 以及对具有基于外部码的纠错能力进行了调整的纠错能力的内部码的编码处理进行内部编码。

10. 发明申请

US20130311840A1 METHOD AND DEVICE FOR ESTIMATING INPUT BIT ERROR RATIO 有权
标题翻译：用于估计输入位错误比率的方法和装置
公开(公告)号：US20130311840A1
公开(公告)日：2013-11-21
申请号：US13982403
申请日：2012-02-20
申请人： Yoshikuni Miyata , Kenya Sugihara , Kiyoshi Onohara , Kazuo Kubo , Hideo Yoshida , Takashi Mizuochi
发明人： Yoshikuni Miyata , Kenya Sugihara , Kiyoshi Onohara , Kazuo Kubo , Hideo Yoshida , Takashi Mizuochi
IPC分类号： G06F11/07
CPC分类号： G06F11/076 , H04L1/203
摘要： An input bit error ratio estimating method executed by a communication control unit includes a computing, a condition determining, a first input BER estimating, a second input BER estimating, a third input BER estimating, and an input BER estimation result outputting. In the condition determining, the communication control unit determines which of a plurality of conditions set in advance to be narrowed down to one has been established, based on a post-internal decoding residual error detection ratio. Based on the condition that is determined in the condition determining as one that has been established, the communication control unit selects one out of a plurality of processing procedures for estimating the input BER, namely, selects one of the first input BER estimating to the third input BER estimating and executes the selected processing.
摘要翻译：由通信控制单元执行的输入误码率估计方法包括计算，条件确定，第一输入BER估计，第二输入BER估计，第三输入BER估计和输入BER估计结果输出。在所述条件判定中，所述通信控制部基于所述内部解码剩余错误检测率，确定预先设定为被缩小为一个的条件中的哪一个已被建立。基于在确定为已经建立的条件中确定的条件，通信控制单元从用于估计输入BER的多个处理过程中选择一个，即，选择第三输入BER中的一个，输入BER估计并执行所选择的处理。

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