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1. 发明授权

US06658605B1 Multiple coding method and apparatus, multiple decoding method and apparatus, and information transmission system 有权
标题翻译：多重编码方法和装置，多重解码方法和装置以及信息传输系统
公开(公告)号：US06658605B1
公开(公告)日：2003-12-02
申请号：US09703638
申请日：2000-11-02
申请人： Hideo Yoshida , Takahiko Nakamura , Hachiro Fujita , Yoshikuni Miyata , Kazuo Kubo
发明人： Hideo Yoshida , Takahiko Nakamura , Hachiro Fujita , Yoshikuni Miyata , Kazuo Kubo
IPC分类号： G11C2900
CPC分类号： H03M7/30 , H03M13/15 , H03M13/1515 , H03M13/2707 , H03M13/2721 , H03M13/29 , H03M13/6561
摘要： A multiple coding apparatus comprises a first encoder for encoding a plurality of input sequences in parallel so as to generate a plurality of output coded sequences in parallel while adding an error-correcting bit sequence to each of the plurality of input sequences. An interleaving circuit interleaves the plurality of output coded sequences applied thereto in parallel from the first encoder without having to use any memory. The interleaving circuit permutes the plurality of input sequences on a bit-by-bit or symbol-by-symbol basis so as to generate a plurality of interleaved coded sequences in parallel. A second encoder then encodes the plurality of interleaved coded sequences applied thereto in parallel from the interleaving circuit so as to generate a plurality of output coded sequences in parallel while adding an error-correcting bit sequence to each of the plurality of interleaved coded sequences.
摘要翻译：多重编码装置包括：并行地编码多个输入序列的第一编码器，以便并行地产生多个输出编码序列，同时向多个输入序列中的每个输入序列添加纠错位序列。交织电路将从第一编码器并行地施加到其上的多个输出编码序列进行交织，而不必使用任何存储器。交织电路逐位或逐符号地排列多个输入序列，以便并行地生成多个交错编码序列。然后，第二编码器对从交织电路并行施加到其上的多个交错编码序列进行编码，以便并行地产生多个输出编码序列，同时向多个交错编码序列中的每一个添加纠错位序列。

2. 发明授权

US06912684B2 Error correction encoding method and apparatus, and error correction decoding method and apparatus 失效
标题翻译：纠错编码方法和装置，以及纠错解码方法和装置
公开(公告)号：US06912684B2
公开(公告)日：2005-06-28
申请号：US10097347
申请日：2002-03-15
申请人： Yoshikuni Miyata , Hachiro Fujita , Takahiko Nakamura , Hideo Yoshida
发明人： Yoshikuni Miyata , Hachiro Fujita , Takahiko Nakamura , Hideo Yoshida
IPC分类号： G06F11/10 , H03M13/23 , H03M13/29 , H03M13/00
CPC分类号： H03M13/2987 , H03M13/2957 , H03M13/2963 , H03M13/2972 , H03M13/2981 , H03M13/3776
摘要： An error correction encoding method and apparatus, and an error correction decoding method and apparatus are provided without requiring transmission of tail bits. A turbo encoding step (ST41-ST45) and a transmission termination processing step (ST46→ST44-ST47) are included. In the turbo encoding step, a transmission information bit sequence is divided into a plurality of frames. Registers in each recursive systematic convolutional encoder are initialized before turbo encoding of a first frame. After turbo encoding of the first frame is carried out, a second frame and following frames are continuously subjected to turbo encoding without initializing the registers in each recursive systematic convolutional encoder before the turbo encoding of the second frame and following frames. In a transmission termination processing step, tail bits for initializing the registers in each recursive systematic convolutional encoder are calculated only after a final frame has been subjected to turbo encoding.
摘要翻译：提供纠错编码方法和装置以及纠错解码方法和装置，而不需要传输尾比特。包括turbo编码步骤（ST 41 -ST 45）和发送终止处理步骤（ST 46-> ST 44 -ST 47）。在turbo编码步骤中，发送信息比特序列被分成多个帧。每个递归系统卷积编码器中的寄存器在第一帧的turbo编码之前被初始化。在执行第一帧的turbo编码之后，在第二帧和后续帧的turbo编码之前，第二帧和后续帧被连续地进行turbo编码，而不在每个递归系统卷积编码器中初始化寄存器。在传输终止处理步骤中，仅在最后一帧已进行turbo编码之后才计算用于初始化每个递归系统卷积编码器中的寄存器的尾比特。

3. 发明授权

US07069496B2 Decoding method, decoding apparatus and digital transmission system of product code 失效
公开(公告)号：US07069496B2
公开(公告)日：2006-06-27
申请号：US10284391
申请日：2002-10-31
申请人： Hachiro Fujita , Yoshikuni Miyata , Takahiko Nakamura , Hideo Yoshida
发明人： Hachiro Fujita , Yoshikuni Miyata , Takahiko Nakamura , Hideo Yoshida
IPC分类号： H03M13/00
CPC分类号： H04L1/0066 , H03M13/136 , H03M13/151 , H03M13/152 , H03M13/19 , H03M13/2909 , H03M13/2927 , H03M13/2948 , H03M13/3738 , H03M13/45 , H03M13/451 , H03M13/6306 , H03M13/6561 , H04L1/005 , H04L1/1835 , H04L1/1874
摘要： A decoding apparatus generates error position sets of data sequence by generating a codeword from positions of soft input values output from a low reliability position detecting circuit and from syndromes computed by a syndrome calculation circuit. The recording apparatus further includes a codeword candidate generating circuit that computes correlation mismatch amounts by adding soft input values at the error positions contained in the error position sets, and updates the correction information according to the error position sets and correlation mismatch amounts. The decoding apparatus can calculate the soft output values accurately by utilizing the generated codeword candidates efficiently, and reduce the circuit scale by decreasing the amount of computation.

4. 发明授权

US07992069B2 Error correction coding apparatus and error correction decoding apparatus 有权
标题翻译：纠错编码装置和纠错解码装置
公开(公告)号：US07992069B2
公开(公告)日：2011-08-02
申请号：US11883958
申请日：2006-02-03
申请人： Yoshikuni Miyata , Hideo Yoshida , Kazuo Kubo
发明人： Yoshikuni Miyata , Hideo Yoshida , Kazuo Kubo
IPC分类号： H03M13/00
CPC分类号： H03M13/2906 , H03M13/134 , H04L1/0041 , H04L1/0057 , H04L1/0064 , H04L1/0083
摘要： An error correction coding apparatus divides transmission information sequences in n subframes (n is an arbitrary natural number) into n1 subframes (n1 is a natural number
摘要翻译：纠错编码装置将n个子帧（n为任意自然数）中的发送信息序列分割为n1个子帧（n1为自然数

5. 发明授权

US09081677B2 Method and device for estimating input bit error ratio 有权
标题翻译：用于估计输入误码率的方法和装置
公开(公告)号：US09081677B2
公开(公告)日：2015-07-14
申请号：US13982403
申请日：2012-02-20
申请人： Yoshikuni Miyata , Kenya Sugihara , Kiyoshi Onohara , Kazuo Kubo , Hideo Yoshida , Takashi Mizuochi
发明人： Yoshikuni Miyata , Kenya Sugihara , Kiyoshi Onohara , Kazuo Kubo , Hideo Yoshida , Takashi Mizuochi
IPC分类号： G06F11/07 , H04L1/20
CPC分类号： G06F11/076 , H04L1/203
摘要： An input bit error ratio estimating method executed by a communication control unit includes a computing, a condition determining, a first input BER estimating, a second input BER estimating, a third input BER estimating, and an input BER estimation result outputting. In the condition determining, the communication control unit determines which of a plurality of conditions set in advance to be narrowed down to one has been established, based on a post-internal decoding residual error detection ratio. Based on the condition that is determined in the condition determining as one that has been established, the communication control unit selects one out of a plurality of processing procedures for estimating the input BER, namely, selects one of the first input BER estimating to the third input BER estimating and executes the selected processing.
摘要翻译：由通信控制单元执行的输入误码率估计方法包括计算，条件确定，第一输入BER估计，第二输入BER估计，第三输入BER估计和输入BER估计结果输出。在所述条件判定中，所述通信控制部基于所述内部解码剩余错误检测率，确定预先设定为被缩小为一个的条件中的哪一个已被建立。基于在确定为已经建立的条件中确定的条件，通信控制单元从用于估计输入BER的多个处理过程中选择一个，即，选择第三输入BER中的一个，输入BER估计并执行所选择的处理。

6. 发明授权

US08621316B2 Method and device for encoding of error correcting codes, and method and device for decoding of error correcting codes 有权
标题翻译：用于纠错码编码的方法和装置，以及用于解码纠错码的方法和装置
公开(公告)号：US08621316B2
公开(公告)日：2013-12-31
申请号：US12987368
申请日：2011-01-10
申请人： Yoshikuni Miyata , Hideo Yoshida , Kazuo Kubo , Takashi Mizuochi
发明人： Yoshikuni Miyata , Hideo Yoshida , Kazuo Kubo , Takashi Mizuochi
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： H04L1/0071 , H03M13/1102 , H03M13/1515 , H03M13/152 , H03M13/23 , H03M13/271 , H03M13/29 , H03M13/2945 , H03M13/2957 , H03M13/2963 , H03M13/356 , H03M13/6561 , H03M13/6577 , H04L1/0065
摘要： An error correction encoding device includes an outer encoding circuit that performs encoding processing for an outer code and an inner encoding circuit that performs encoding processing for an inner code. The inner encoding circuit includes an inner-encoding input circuit that performs interleaving processing in which a parallel input sequence is divided into lanes and in which a barrel shift is performed for each inner frame in the lanes. Thus, allocation ratios between an information sequence area and a parity sequence area are made uniform.
摘要翻译：纠错编码装置包括对外部码进行编码处理的外部编码电路和对内部码进行编码处理的内部编码电路。内部编码电路包括内部编码输入电路，其执行交织处理，其中并行输入序列被划分为通道，并且其中对车道中的每个内部框架执行桶形移位。因此，使信息序列区域和奇偶序列区域之间的分配比率一致。

7. 发明申请

US20130311847A1 ERROR CORRECTION CODING DEVICE, ERROR CORRECTION DECODING DEVICE AND METHOD THEREFOR 有权
标题翻译：错误校正编码装置，错误校正解码装置及其方法
公开(公告)号：US20130311847A1
公开(公告)日：2013-11-21
申请号：US13982919
申请日：2012-05-30
申请人： Yoshikuni Miyata , Wataru Matsumoto , Hideo Yoshida , Kazuo Kubo
发明人： Yoshikuni Miyata , Wataru Matsumoto , Hideo Yoshida , Kazuo Kubo
IPC分类号： H03M13/29
CPC分类号： H03M13/29 , H03M13/1102 , H03M13/1145 , H03M13/152 , H03M13/2909 , H03M13/356
摘要： Provided is an error correction encoder that performs coding on both a transmission area and a redundancy area of the transmission frame by using a product code, and when excess or deficiency is arisen with respect to allocation of an information sequence area and/or a parity sequence area in a product code frame generated by the coding using the product code, non-uniformly allocate the information sequence area to the parity sequence area, and/or non-uniformly allocate the parity sequence area to the information sequence area, where each of the non-uniform allocations is performed in accordance with the arisen excess or deficiency.
摘要翻译：提供了一种纠错编码器，其通过使用产品代码对发送帧的发送区域和冗余区域两者进行编码，并且当相对于信息序列区域和/或奇偶校验序列的分配产生过多或不足时通过使用产品代码的编码生成的商品代码帧中的区域，将信息序列区域均匀地分配给奇偶校验序列区域，和/或非均匀地将奇偶校验序列区域分配给信息序列区域，其中，根据发生的过量或不足，进行非均匀分配。

8. 发明授权

US06757865B1 Turbo-code error correcting decoder, turbo-code error correction decoding method, turbo-code decoding apparatus, and turbo-code decoding system 失效
标题翻译： Turbo码纠错解码器，Turbo码纠错解码方法，Turbo码解码装置和Turbo码解码系统
公开(公告)号：US06757865B1
公开(公告)日：2004-06-29
申请号：US09568163
申请日：2000-05-10
申请人： Takahiko Nakamura , Hachiro Fujita , Hideo Yoshida
发明人： Takahiko Nakamura , Hachiro Fujita , Hideo Yoshida
IPC分类号： H03M1303
CPC分类号： H03M13/4146 , H03M13/2957 , H03M13/3905 , H03M13/3972
摘要： In a conventional turbo-code decoding apparatus, there is a need for calculating a state transition probability for MAP decoding of convolutional codes composing turbo codes in an error correcting decoder and a channel state needs to be measured based on soft decision information to calculate the probability, by which an arithmetic operation amount is enormously increased. Turbo-code error correction decoding is performed by executing operations in a branch metric based forward path metric calculation step of calculating a forward path metric based on a branch metric with calculating the branch metric for a transition to an adjacent time point and a soft decision information calculation step of calculating N bits of soft decision information based on the branch metric, the forward path metric, and a backward path metric with calculating the backward path metric based on the branch metric.
摘要翻译：在常规turbo码解码装置中，需要计算在纠错解码器中构成turbo码的卷积码的MAP解码的状态转移概率，而需要根据软决策信息来测量信道状态，以计算概率通过在基于分支度量的前向路径度量计算步骤中执行基于分支度量计算前向路径量度的操作来执行Turbo码纠错解码，计算分支度量用于过渡到相邻时间点，以及软判决信息计算步骤，基于分支度量，前向路径度量和反向路径度量，基于分支度量计算反向路径度量来计算软判决信息的N位。

9. 发明授权

US06625778B1 Turbo error-correcting decoder and turbo error-correcting decoding method 失效
标题翻译： Turbo纠错解码器和turbo纠错解码方法
公开(公告)号：US06625778B1
公开(公告)日：2003-09-23
申请号：US09654067
申请日：2000-09-01
申请人： Takahiko Nakamura , Hachiro Fujita , Hideo Yoshida
发明人： Takahiko Nakamura , Hachiro Fujita , Hideo Yoshida
IPC分类号： H03M1300
CPC分类号： H03M13/658 , H03M13/2957 , H03M13/2984
摘要： In a conventional turbo error-correcting decoder, the soft-decision information is corrected by using an average value (A) and a variance value (&sgr;2) of reliability of received bits. From the reliability-corrected soft-decision information, the hard-decision information is obtained. This process of calculation is complex, giving rise to a problem of reduced processing speed and complicated circuit. To deal with this problem, an average value of reliability of received information bits is determined and then a ratio between the average value and the soft-decision information is also determined. This ratio is converted by the conversion table into the reliability-corrected soft-decision information, from which the hard-decision information is obtained.
摘要翻译：在传统的turbo纠错解码器中，通过使用接收比特的可靠性的平均值（A）和方差值（sigma <2>）来校正软判决信息。从可靠性校正的软判决信息中，获得硬决策信息。这个计算过程很复杂，导致处理速度降低和电路复杂的问题。为了解决这个问题，确定接收信息比特的可靠性的平均值，然后确定平均值和软判决信息之间的比率。该比率由转换表转换为可靠性校正的软判决信息，从中获得硬决策信息。

10. 发明授权

US08201047B2 Decoding apparatus and communications apparatus 有权
标题翻译：解码装置和通信装置
公开(公告)号：US08201047B2
公开(公告)日：2012-06-12
申请号：US11791996
申请日：2005-12-01
申请人： Rui Sakai , Wataru Matsumoto , Yoshikuni Miyata , Hideo Yoshida , Takahiko Nakamura
发明人： Rui Sakai , Wataru Matsumoto , Yoshikuni Miyata , Hideo Yoshida , Takahiko Nakamura
IPC分类号： H03M13/00
CPC分类号： H03M13/1188 , H03M13/1117 , H03M13/112 , H03M13/1137 , H03M13/114 , H03M13/118 , H03M13/1185 , H03M13/3911 , H03M13/6583 , H04L1/005 , H04L1/0057
摘要： A decoding apparatus includes a row processing unit 5 and a column processing unit 6 for performing a calculation and an update of probability information with row processing and column processing according to a Min-Sum algorithm on a received signal which is low-density parity-check coded in batches of 1 bit or a predetermined number of bits, a decoded result judgment unit 8 for determining a decoded result from a hard decision of a posterior value, for performing a parity check on the decoded result, and for judging whether or not the decoded result is correct, and a control unit for controlling iteration of decoding processing by the row processing unit 5 and column processing unit 6 on the basis of the judgment result of the decoded result judgment unit 8.
摘要翻译：解码装置包括：行处理单元5和列处理单元6，用于对接收到的信号进行低密度奇偶校验，根据最小和算法对行处理和列处理进行概率信息的计算和更新以1比特或预定比特数的批次编码的解码结果判断单元8，用于从后验值的硬判定中确定解码结果，用于对解码结果进行奇偶校验，并判断是否解码结果是正确的，以及控制单元，用于根据解码结果判断单元8的判断结果控制行处理单元5和列处理单元6的解码处理的迭代。

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