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1. 发明授权

US07151025B2 Method of manufacturing a semiconductor device with self-aligned contacts 有权
标题翻译：具有自对准触点的半导体器件的制造方法
公开(公告)号：US07151025B2
公开(公告)日：2006-12-19
申请号：US10388447
申请日：2003-03-17
申请人： Kazuo Itabashi , Osamu Tsuboi , Yuji Yokoyama , Kenichi Inoue , Koichi Hashimoto , Wataru Futo
发明人： Kazuo Itabashi , Osamu Tsuboi , Yuji Yokoyama , Kenichi Inoue , Koichi Hashimoto , Wataru Futo
IPC分类号： H01O21/8242
CPC分类号： H01L27/10852 , H01L21/76897 , H01L27/105 , H01L27/10805 , H01L27/10817 , H01L28/91
摘要： A method of manufacturing a semiconductor device on a semiconductor substrate having a first region and a second region. This method beings by forming a transistor in the first region of said semiconductor substrate. This transistor includes a pair of impurity diffusion regions and a gate electrode. Then forming a first insulating film over the first and second regions with this first insulating film covering the transistor in the first region. Thereafter, patterning the first insulating film to selectively remove the first insulating film in the second region. Then forming a second insulating film over the first and second regions. Thereafter, forming at least one contact hole through the second and first insulating film. The contact hole reaches one of the impurity diffusion regions. Finally, forming a conductive layer in the contact hole.
摘要翻译：一种在具有第一区域和第二区域的半导体衬底上制造半导体器件的方法。该方法通过在所述半导体衬底的第一区域中形成晶体管来实现。该晶体管包括一对杂质扩散区和栅电极。然后在第一和第二区域上形成第一绝缘膜，该第一绝缘膜覆盖第一区域中的晶体管。此后，图案化第一绝缘膜以选择性地去除第二区域中的第一绝缘膜。然后在第一和第二区域上形成第二绝缘膜。此后，通过第二和第一绝缘膜形成至少一个接触孔。接触孔到达杂质扩散区域中的一个。最后，在接触孔中形成导电层。

2. 发明授权

US06936510B2 Semiconductor device with self-aligned contact and its manufacture 有权
标题翻译：具有自对准触点的半导体器件及其制造
公开(公告)号：US06936510B2
公开(公告)日：2005-08-30
申请号：US10388454
申请日：2003-03-17
申请人： Kazuo Itabashi , Osamu Tsuboi , Yuji Yokoyama , Kenichi Inoue , Koichi Hashimoto , Wataru Futo
发明人： Kazuo Itabashi , Osamu Tsuboi , Yuji Yokoyama , Kenichi Inoue , Koichi Hashimoto , Wataru Futo
IPC分类号： H01L21/02 , H01L21/60 , H01L21/8242 , H01L27/105 , H01L27/108 , H01L27/10
CPC分类号： H01L27/10852 , H01L21/76897 , H01L27/105 , H01L27/10805 , H01L27/10817 , H01L28/91
摘要： A semiconductor memory device comprising: a first insulating film covering the upper and side surfaces of a gate electrode; a second insulating film formed on the substrate covering the first insulating film; a pair of contact holes formed through the second insulating film and reaching the impurity diffusion regions; a conductive plug embedded in one of the contact holes; a third insulating film formed on the second insulating film covering the conductive plug, and having a first aperture on the other contact hole; a bit line formed on the third insulating film and connected to the other impurity diffusion region through the first aperture and the other contact hole; a fourth insulating film covering the upper and side surfaces of the bit line; a second aperture formed through the third insulating film in alignment with the fourth insulating film covering the side surface of the bit line; a storage electrode formed to extend over the bit line, insulated from the bit line by the third and fourth insulating films, and electrically connected to the conductive plug through the second aperture.
摘要翻译：一种半导体存储器件，包括：覆盖栅电极的上表面和侧表面的第一绝缘膜; 形成在覆盖所述第一绝缘膜的所述基板上的第二绝缘膜; 形成在所述第二绝缘膜上并到达所述杂质扩散区的一对接触孔; 嵌入在所述接触孔之一中的导电插塞; 第三绝缘膜，形成在覆盖所述导电插塞的所述第二绝缘膜上，并且在所述另一个接触孔上具有第一孔; 形成在第三绝缘膜上并通过第一孔和另一个接触孔连接到另一个杂质扩散区的位线; 覆盖位线的上表面和侧表面的第四绝缘膜; 与覆盖所述位线的侧面的所述第四绝缘膜对准的通过所述第三绝缘膜形成的第二孔; 存储电极，其形成为在所述位线上延伸，通过所述第三和第四绝缘膜与所述位线绝缘，并且通过所述第二孔电连接到所述导电插塞。

3. 发明授权

US06620674B1 Semiconductor device with self-aligned contact and its manufacture 有权
标题翻译：具有自对准触点的半导体器件及其制造
公开(公告)号：US06620674B1
公开(公告)日：2003-09-16
申请号：US09638139
申请日：2000-08-15
申请人： Kazuo Itabashi , Osamu Tsuboi , Yuji Yokoyama , Kenichi Inoue , Koichi Hashimoto , Wataru Futo
发明人： Kazuo Itabashi , Osamu Tsuboi , Yuji Yokoyama , Kenichi Inoue , Koichi Hashimoto , Wataru Futo
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L21/76897 , H01L27/105 , H01L27/10805 , H01L27/10817 , H01L28/91
摘要： A semiconductor memory device comprising: a first insulating film covering the upper and side surfaces of a gate electrode; a second insulating film formed on the substrate covering the first insulating film; a pair of contact holes formed through the second insulating film and reaching the impurity diffusion regions; a conductive plug embedded in one of the contact holes; a third insulating film formed on the second insulating film covering the conductive plug, and having a first aperture on the other contact hole; a bit line formed on the third insulating film and connected to the other impurity diffusion region through the first aperture and the other contact hole; a fourth insulating film covering the upper and side surfaces of the bit line; a second aperture formed through the third insulating film in alignment with the fourth insulating film covering the side surface of the bit line; a storage electrode formed to extend over the bit line, insulated from the bit line by the third and fourth insulating films, and electrically connected to the conductive plug through the second aperture.
摘要翻译：一种半导体存储器件，包括：覆盖栅电极的上表面和侧表面的第一绝缘膜; 形成在覆盖所述第一绝缘膜的所述基板上的第二绝缘膜; 形成在所述第二绝缘膜上并到达所述杂质扩散区的一对接触孔; 嵌入在所述接触孔之一中的导电插塞; 第三绝缘膜，形成在覆盖所述导电插塞的所述第二绝缘膜上，并且在所述另一个接触孔上具有第一孔; 形成在第三绝缘膜上并通过第一孔和另一个接触孔连接到另一个杂质扩散区的位线; 覆盖位线的上表面和侧表面的第四绝缘膜; 与覆盖所述位线的侧面的所述第四绝缘膜对准的通过所述第三绝缘膜形成的第二孔; 存储电极，其形成为在所述位线上延伸，通过所述第三和第四绝缘膜与所述位线绝缘，并且通过所述第二孔电连接到所述导电插塞。

4. 发明授权

US5932901A Semiconductor device with self-aligned contact and its manufacture 失效
公开(公告)号：US5932901A
公开(公告)日：1999-08-03
申请号：US890991
申请日：1997-07-10
申请人： Kazuo Itabashi , Osamu Tsuboi , Yuji Yokoyama , Kenichi Inoue , Koichi Hashimoto , Wataru Futo
发明人： Kazuo Itabashi , Osamu Tsuboi , Yuji Yokoyama , Kenichi Inoue , Koichi Hashimoto , Wataru Futo
IPC分类号： H01L21/02 , H01L21/60 , H01L21/8242 , H01L27/105 , H01L27/108 , H01L27/10
CPC分类号： H01L27/10852 , H01L21/76897 , H01L27/105 , H01L27/10805 , H01L27/10817 , H01L28/91
摘要： A semiconductor memory device comprising: a first insulating film covering the upper and side surfaces of a gate electrode; a second insulating film formed on the substrate covering the first insulating film; a pair of contact holes formed through the second insulating film and reaching the impurity diffusion regions; a conductive plug embedded in one of the contact holes; a third insulating film formed on the second insulating film covering the conductive plug, and having a first aperture on the other contact hole; a bit line formed on the third insulating film and connected to the other impurity diffusion region through the first aperture and the other contact hole; a fourth insulating film covering the upper and side surfaces of the bit line; a second aperture formed through the third insulating film in alignment with the fourth insulating film covering the side surface of the bit line; a storage electrode formed to extend over the bit line, insulated from the bit line by the third and fourth insulating films, and electrically connected to the conductive plug through the second aperture.

5. 发明授权

US06285045B1 Semiconductor device with self-aligned contact and its manufacture 失效
标题翻译：具有自对准触点的半导体器件及其制造
公开(公告)号：US06285045B1
公开(公告)日：2001-09-04
申请号：US08890991
申请日：1997-07-10
申请人： Kazuo Itabashi , Osamu Tsuboi , Yuji Yokoyama , Kenichi Inoue , Koichi Hashimoto , Wataru Futo
发明人： Kazuo Itabashi , Osamu Tsuboi , Yuji Yokoyama , Kenichi Inoue , Koichi Hashimoto , Wataru Futo
IPC分类号： H01L2710
CPC分类号： H01L27/10852 , H01L21/76897 , H01L27/105 , H01L27/10805 , H01L27/10817 , H01L28/91
摘要： A semiconductor memory device comprising: a first insulating film covering the upper and side surfaces of a gate electrode; a second insulating film formed on the substrate covering the first insulating film; a pair of contact holes formed through the second insulating film and reaching the impurity diffusion regions; a conductive plug embedded in one of the contact holes; a third insulating film formed on the second insulating film covering the conductive plug, and having a first aperture on the other contact hole; a bit line formed on the third insulating film and connected to the other impurity diffusion region through the first aperture and the other contact hole; a fourth insulating film covering the upper and side surfaces of the bit line; a second aperture formed through the third insulating film in alignment with the fourth insulating film covering the side surface of the bit line; a storage electrode formed to extend over the bit line, insulated from the bit line by the third and fourth insulating films, and electrically connected to the conductive plug through the second aperture.
摘要翻译：一种半导体存储器件，包括：覆盖栅电极的上表面和侧表面的第一绝缘膜; 形成在覆盖所述第一绝缘膜的所述基板上的第二绝缘膜; 形成在所述第二绝缘膜上并到达所述杂质扩散区的一对接触孔; 嵌入在所述接触孔之一中的导电插塞; 第三绝缘膜，形成在覆盖所述导电插塞的所述第二绝缘膜上，并且在所述另一个接触孔上具有第一孔; 形成在第三绝缘膜上并通过第一孔和另一个接触孔连接到另一个杂质扩散区的位线; 覆盖位线的上表面和侧表面的第四绝缘膜; 与覆盖所述位线的侧面的所述第四绝缘膜对准的通过所述第三绝缘膜形成的第二孔; 存储电极，其形成为在所述位线上延伸，通过所述第三和第四绝缘膜与所述位线绝缘，并且通过所述第二孔电连接到所述导电插塞。

6. 发明授权

US6130482A Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US6130482A
公开(公告)日：2000-10-10
申请号：US721637
申请日：1996-09-26
申请人： Hiroki Iio , Koichi Hashimoto , Wataru Futo
发明人： Hiroki Iio , Koichi Hashimoto , Wataru Futo
IPC分类号： H01L21/60 , H01L21/768 , H01L23/485 , H01L23/522 , H01L29/34 , H01L21/44
CPC分类号： H01L21/76855 , H01L21/76802 , H01L21/7682 , H01L21/76829 , H01L21/76843 , H01L21/76852 , H01L21/76868 , H01L21/76877 , H01L21/76895 , H01L21/76897 , H01L23/485 , H01L23/5226 , H01L21/2855 , H01L21/28556 , H01L2924/0002
摘要： The present invention relates to a metallization technique of a semiconductor device, more specifically to a semiconductor device having a wiring or plug of a suitable structure for high integration and a method for fabrication of the semiconductor device. The semiconductor device comprises a base substrate 10; an inter-layer insulation film 20 including a first insulation film 16 formed on the base substrate and a second insulation film 18 formed on the base substrate, and having a contact hole 22 which reaches the base substrate 10; and a conducting film 24 formed on an inside wall and a bottom of the contact hole 22, a width of the contact hole in the first insulation film 16 being larger than a width of the contact hole 22 in the second insulation film 18. The conducting film 24 on the inside wall of the contact hole 22, and the conducting film 24 on the bottom of the contact hole 22 is uninterrupted on a boundary.
摘要翻译：本发明涉及一种半导体器件的金属化技术，更具体地涉及具有用于高集成度的合适结构的布线或插头的半导体器件以及半导体器件的制造方法。半导体器件包括基底10; 包括形成在基底基板上的第一绝缘膜16和形成在基底基板上的第二绝缘膜18，并具有到达基底基板10的接触孔22的层间绝缘膜20; 以及形成在接触孔22的内壁和底部上的导电膜24，第一绝缘膜16中的接触孔的宽度大于第二绝缘膜18中的接触孔22的宽度。导电膜接触孔22的内壁上的薄膜24和接触孔22的底部的导电薄膜24在边界上不间断。

7. 发明授权

US09230872B2 Lead-free glass for semiconductor encapsulation 有权
标题翻译：无铅玻璃用于半导体封装
公开(公告)号：US09230872B2
公开(公告)日：2016-01-05
申请号：US13805039
申请日：2011-06-17
申请人： Koichi Hashimoto
发明人： Koichi Hashimoto
IPC分类号： H01L23/29 , C03C8/02 , C03C3/068 , C03C3/095 , C03C8/24 , H01L33/56
CPC分类号： H01L23/291 , C03C3/068 , C03C3/095 , C03C8/24 , H01L33/56 , H01L2924/0002 , H01L2924/00
摘要： The technical task of the present invention is to provide a lead-free glass for semiconductor encapsulation, which is easy to automate an appearance inspection, and furthermore, has excellent refinability and encapsulatability of semiconductor devices. In the lead-free glass for semiconductor encapsulation according to the present invention, a temperature at which the viscosity of glass is 106 dPa·s is 670° C. or lower, and, as a glass composition, the content of CeO2 is from 0.01 to 6% by mass, and the content of Sb2O3 is 0.1% by mass or less.
摘要翻译：本发明的技术任务是提供一种用于半导体封装的无铅玻璃，其容易自动进行外观检查，此外，具有优异的可熔性和半导体器件的可封装性。在本发明的半导体封装用无铅玻璃中，玻璃粘度为106dPa·s的温度为670℃以下，作为玻璃组合物，CeO 2的含量为0.01 〜6质量％，Sb 2 O 3的含量为0.1质量％以下。

8. 发明授权

US08933463B2 Semiconductor element, semiconductor device, and power converter 有权
标题翻译：半导体元件，半导体器件和功率转换器
公开(公告)号：US08933463B2
公开(公告)日：2015-01-13
申请号：US13780876
申请日：2013-02-28
申请人： Kazuhiro Adachi , Osamu Kusumoto , Masao Uchida , Koichi Hashimoto , Shun Kazama
发明人： Kazuhiro Adachi , Osamu Kusumoto , Masao Uchida , Koichi Hashimoto , Shun Kazama
IPC分类号： H01L29/16 , H01L29/66 , H01L29/78 , H03K17/14 , H01L29/45
CPC分类号： H01L29/1608 , H01L29/45 , H01L29/66068 , H01L29/7805 , H01L29/7827 , H01L29/7828 , H03K17/145
摘要： A semiconductor element including an MISFET exhibits diode characteristics in a reverse direction through an epitaxial channel layer. The semiconductor element includes: a silicon carbide semiconductor substrate of a first conductivity type, semiconductor layer of the first conductivity type, body region of a second conductivity type, source region of the first conductivity type, epitaxial channel layer in contact with the body region, source electrode, gate insulating film, gate electrode and drain electrode. If the voltage applied to the gate electrode is smaller than a threshold voltage, the semiconductor element functions as a diode wherein current flows from the source electrode to the drain electrode through the epitaxial channel layer. The absolute value of the turn-on voltage of this diode is smaller than the turn-on voltage of a body diode that is formed of the body region and the first silicon carbide semiconductor layer.
摘要翻译：包括MISFET的半导体元件通过外延沟道层在相反方向上表现出二极管特性。半导体元件包括：第一导电类型的碳化硅半导体衬底，第一导电类型的半导体层，第二导电类型的主体区域，第一导电类型的源极区域，与身体区域接触的外延沟道层，源电极，栅极绝缘膜，栅电极和漏电极。如果施加到栅电极的电压小于阈值电压，则半导体元件用作二极管，其中电流从源电极通过外延沟道层流到漏电极。该二极管的导通电压的绝对值小于由体区和第一碳化硅半导体层形成的体二极管的导通电压。

9. 发明申请

US20130058029A1 MODULAR DATA CENTER 审中-公开
标题翻译：模块化数据中心
公开(公告)号：US20130058029A1
公开(公告)日：2013-03-07
申请号：US13557635
申请日：2012-07-25
申请人： Hideyoshi Ootani , Kazuhide Sato , Makoto Honda , Koichi Hashimoto , Tomoyuki Kinoshita , Masaaki Yamamoto , Kobun Takahashi , Hiroshi Morimoto
发明人： Hideyoshi Ootani , Kazuhide Sato , Makoto Honda , Koichi Hashimoto , Tomoyuki Kinoshita , Masaaki Yamamoto , Kobun Takahashi , Hiroshi Morimoto
IPC分类号： G06F1/20
CPC分类号： F24F3/044 , H05K7/1497 , H05K7/20745
摘要： A data center is disclosed that includes a container; a server; a rack installed within the container and storing the server; and a curtain fixed to at least one point of the rack or the container and separating an internal space of the container between a cold side and a hot side; wherein the rack is configured to enable the circulation of air from the cold side to the hot side. The curtain is fixed by a removable clamping mechanism. The data center further includes a modular refrigeration unit configured to attach to the container and direct cold air into the cold area. At least one prop is positioned below a bottom of the housing and connected to a container bottom, the prop is configured to absorb vibration of the container or housing.
摘要翻译：公开了一种包括容器的数据中心; 一个服务器安装在容器内并存储服务器的机架; 以及窗帘，其固定在所述架子或所述容器的至少一个点上，并且在所述冷侧和所述热侧之间分离所述容器的内部空间; 其中，所述支架构造成能够使空气从所述冷侧循环到所述热侧。窗帘通过可拆卸的夹紧机构固定。数据中心还包括模块化制冷单元，其被配置为附接到容器并将冷空气引导到冷区域中。至少一个支柱位于壳体的底部下方并连接到容器底部，支撑构造成吸收容器或壳体的振动。

10. 发明授权

US08283973B2 Semiconductor element, semiconductor device, and electric power converter 有权
标题翻译：半导体元件，半导体器件和电力转换器
公开(公告)号：US08283973B2
公开(公告)日：2012-10-09
申请号：US13389555
申请日：2010-08-09
申请人： Koichi Hashimoto , Kazuhiro Adachi , Osamu Kusumoto , Masao Uchida , Shun Kazama
发明人： Koichi Hashimoto , Kazuhiro Adachi , Osamu Kusumoto , Masao Uchida , Shun Kazama
IPC分类号： G05F3/02
CPC分类号： H01L29/7828 , H01L29/1608 , H01L29/66068 , H01L29/78 , H01L29/7838 , H02M7/5387 , Y02B70/1483
摘要： A semiconductor element 100 including an MISFET according to the present invention is characterized by having diode characteristics in a reverse direction through an epitaxial channel layer 50. The semiconductor element 100 includes a semiconductor layer 20 of a first conductivity type, a body region 30 of a second conductivity type, source and drain regions 40 and 75 of the first conductivity type, an epitaxial channel layer 50 in contact with the body region, source and drain electrodes 45 and 70, a gate insulating film 60, and a gate electrode 65. If the voltage applied to the gate electrode of the MISFET is smaller than a threshold voltage, the semiconductor element 100 functions as a diode in which current flows from the source electrode 45 to the drain electrode 70 through the epitaxial channel layer 50. The absolute value of the turn-on voltage of this diode is smaller than that of the turn-on voltage of a body diode that is formed of the body region and the first silicon carbide semiconductor layer.
摘要翻译：包括根据本发明的MISFET的半导体元件100的特征在于通过外延沟道层50在相反方向上具有二极管特性。半导体元件100包括第一导电类型的半导体层20，第一导电类型的体区30 第二导电类型，第一导电类型的源极和漏极区域40和75，与主体区域接触的外延沟道层50，源极和漏极电极45和70，栅极绝缘膜60和栅电极65.如果施加到MISFET的栅电极的电压小于阈值电压，半导体元件100用作二极管，其中电流通过外延沟道层50从源电极45流到漏极70。绝对值该二极管的导通电压小于由体区和第一硅碳化物形成的体二极管的导通电压的导通电压 e半导体层。

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