专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06620674B1 Semiconductor device with self-aligned contact and its manufacture 有权
标题翻译：具有自对准触点的半导体器件及其制造
公开(公告)号：US06620674B1
公开(公告)日：2003-09-16
申请号：US09638139
申请日：2000-08-15
申请人： Kazuo Itabashi , Osamu Tsuboi , Yuji Yokoyama , Kenichi Inoue , Koichi Hashimoto , Wataru Futo
发明人： Kazuo Itabashi , Osamu Tsuboi , Yuji Yokoyama , Kenichi Inoue , Koichi Hashimoto , Wataru Futo
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L21/76897 , H01L27/105 , H01L27/10805 , H01L27/10817 , H01L28/91
摘要： A semiconductor memory device comprising: a first insulating film covering the upper and side surfaces of a gate electrode; a second insulating film formed on the substrate covering the first insulating film; a pair of contact holes formed through the second insulating film and reaching the impurity diffusion regions; a conductive plug embedded in one of the contact holes; a third insulating film formed on the second insulating film covering the conductive plug, and having a first aperture on the other contact hole; a bit line formed on the third insulating film and connected to the other impurity diffusion region through the first aperture and the other contact hole; a fourth insulating film covering the upper and side surfaces of the bit line; a second aperture formed through the third insulating film in alignment with the fourth insulating film covering the side surface of the bit line; a storage electrode formed to extend over the bit line, insulated from the bit line by the third and fourth insulating films, and electrically connected to the conductive plug through the second aperture.
摘要翻译：一种半导体存储器件，包括：覆盖栅电极的上表面和侧表面的第一绝缘膜; 形成在覆盖所述第一绝缘膜的所述基板上的第二绝缘膜; 形成在所述第二绝缘膜上并到达所述杂质扩散区的一对接触孔; 嵌入在所述接触孔之一中的导电插塞; 第三绝缘膜，形成在覆盖所述导电插塞的所述第二绝缘膜上，并且在所述另一个接触孔上具有第一孔; 形成在第三绝缘膜上并通过第一孔和另一个接触孔连接到另一个杂质扩散区的位线; 覆盖位线的上表面和侧表面的第四绝缘膜; 与覆盖所述位线的侧面的所述第四绝缘膜对准的通过所述第三绝缘膜形成的第二孔; 存储电极，其形成为在所述位线上延伸，通过所述第三和第四绝缘膜与所述位线绝缘，并且通过所述第二孔电连接到所述导电插塞。

2. 发明授权

US5932901A Semiconductor device with self-aligned contact and its manufacture 失效
公开(公告)号：US5932901A
公开(公告)日：1999-08-03
申请号：US890991
申请日：1997-07-10
申请人： Kazuo Itabashi , Osamu Tsuboi , Yuji Yokoyama , Kenichi Inoue , Koichi Hashimoto , Wataru Futo
发明人： Kazuo Itabashi , Osamu Tsuboi , Yuji Yokoyama , Kenichi Inoue , Koichi Hashimoto , Wataru Futo
IPC分类号： H01L21/02 , H01L21/60 , H01L21/8242 , H01L27/105 , H01L27/108 , H01L27/10
CPC分类号： H01L27/10852 , H01L21/76897 , H01L27/105 , H01L27/10805 , H01L27/10817 , H01L28/91
摘要： A semiconductor memory device comprising: a first insulating film covering the upper and side surfaces of a gate electrode; a second insulating film formed on the substrate covering the first insulating film; a pair of contact holes formed through the second insulating film and reaching the impurity diffusion regions; a conductive plug embedded in one of the contact holes; a third insulating film formed on the second insulating film covering the conductive plug, and having a first aperture on the other contact hole; a bit line formed on the third insulating film and connected to the other impurity diffusion region through the first aperture and the other contact hole; a fourth insulating film covering the upper and side surfaces of the bit line; a second aperture formed through the third insulating film in alignment with the fourth insulating film covering the side surface of the bit line; a storage electrode formed to extend over the bit line, insulated from the bit line by the third and fourth insulating films, and electrically connected to the conductive plug through the second aperture.

3. 发明授权

US07151025B2 Method of manufacturing a semiconductor device with self-aligned contacts 有权
标题翻译：具有自对准触点的半导体器件的制造方法
公开(公告)号：US07151025B2
公开(公告)日：2006-12-19
申请号：US10388447
申请日：2003-03-17
申请人： Kazuo Itabashi , Osamu Tsuboi , Yuji Yokoyama , Kenichi Inoue , Koichi Hashimoto , Wataru Futo
发明人： Kazuo Itabashi , Osamu Tsuboi , Yuji Yokoyama , Kenichi Inoue , Koichi Hashimoto , Wataru Futo
IPC分类号： H01O21/8242
CPC分类号： H01L27/10852 , H01L21/76897 , H01L27/105 , H01L27/10805 , H01L27/10817 , H01L28/91
摘要： A method of manufacturing a semiconductor device on a semiconductor substrate having a first region and a second region. This method beings by forming a transistor in the first region of said semiconductor substrate. This transistor includes a pair of impurity diffusion regions and a gate electrode. Then forming a first insulating film over the first and second regions with this first insulating film covering the transistor in the first region. Thereafter, patterning the first insulating film to selectively remove the first insulating film in the second region. Then forming a second insulating film over the first and second regions. Thereafter, forming at least one contact hole through the second and first insulating film. The contact hole reaches one of the impurity diffusion regions. Finally, forming a conductive layer in the contact hole.
摘要翻译：一种在具有第一区域和第二区域的半导体衬底上制造半导体器件的方法。该方法通过在所述半导体衬底的第一区域中形成晶体管来实现。该晶体管包括一对杂质扩散区和栅电极。然后在第一和第二区域上形成第一绝缘膜，该第一绝缘膜覆盖第一区域中的晶体管。此后，图案化第一绝缘膜以选择性地去除第二区域中的第一绝缘膜。然后在第一和第二区域上形成第二绝缘膜。此后，通过第二和第一绝缘膜形成至少一个接触孔。接触孔到达杂质扩散区域中的一个。最后，在接触孔中形成导电层。

4. 发明授权

US06936510B2 Semiconductor device with self-aligned contact and its manufacture 有权
标题翻译：具有自对准触点的半导体器件及其制造
公开(公告)号：US06936510B2
公开(公告)日：2005-08-30
申请号：US10388454
申请日：2003-03-17
申请人： Kazuo Itabashi , Osamu Tsuboi , Yuji Yokoyama , Kenichi Inoue , Koichi Hashimoto , Wataru Futo
发明人： Kazuo Itabashi , Osamu Tsuboi , Yuji Yokoyama , Kenichi Inoue , Koichi Hashimoto , Wataru Futo
IPC分类号： H01L21/02 , H01L21/60 , H01L21/8242 , H01L27/105 , H01L27/108 , H01L27/10
CPC分类号： H01L27/10852 , H01L21/76897 , H01L27/105 , H01L27/10805 , H01L27/10817 , H01L28/91
摘要： A semiconductor memory device comprising: a first insulating film covering the upper and side surfaces of a gate electrode; a second insulating film formed on the substrate covering the first insulating film; a pair of contact holes formed through the second insulating film and reaching the impurity diffusion regions; a conductive plug embedded in one of the contact holes; a third insulating film formed on the second insulating film covering the conductive plug, and having a first aperture on the other contact hole; a bit line formed on the third insulating film and connected to the other impurity diffusion region through the first aperture and the other contact hole; a fourth insulating film covering the upper and side surfaces of the bit line; a second aperture formed through the third insulating film in alignment with the fourth insulating film covering the side surface of the bit line; a storage electrode formed to extend over the bit line, insulated from the bit line by the third and fourth insulating films, and electrically connected to the conductive plug through the second aperture.
摘要翻译：一种半导体存储器件，包括：覆盖栅电极的上表面和侧表面的第一绝缘膜; 形成在覆盖所述第一绝缘膜的所述基板上的第二绝缘膜; 形成在所述第二绝缘膜上并到达所述杂质扩散区的一对接触孔; 嵌入在所述接触孔之一中的导电插塞; 第三绝缘膜，形成在覆盖所述导电插塞的所述第二绝缘膜上，并且在所述另一个接触孔上具有第一孔; 形成在第三绝缘膜上并通过第一孔和另一个接触孔连接到另一个杂质扩散区的位线; 覆盖位线的上表面和侧表面的第四绝缘膜; 与覆盖所述位线的侧面的所述第四绝缘膜对准的通过所述第三绝缘膜形成的第二孔; 存储电极，其形成为在所述位线上延伸，通过所述第三和第四绝缘膜与所述位线绝缘，并且通过所述第二孔电连接到所述导电插塞。

5. 发明授权

US06285045B1 Semiconductor device with self-aligned contact and its manufacture 失效
标题翻译：具有自对准触点的半导体器件及其制造
公开(公告)号：US06285045B1
公开(公告)日：2001-09-04
申请号：US08890991
申请日：1997-07-10
申请人： Kazuo Itabashi , Osamu Tsuboi , Yuji Yokoyama , Kenichi Inoue , Koichi Hashimoto , Wataru Futo
发明人： Kazuo Itabashi , Osamu Tsuboi , Yuji Yokoyama , Kenichi Inoue , Koichi Hashimoto , Wataru Futo
IPC分类号： H01L2710
CPC分类号： H01L27/10852 , H01L21/76897 , H01L27/105 , H01L27/10805 , H01L27/10817 , H01L28/91
摘要： A semiconductor memory device comprising: a first insulating film covering the upper and side surfaces of a gate electrode; a second insulating film formed on the substrate covering the first insulating film; a pair of contact holes formed through the second insulating film and reaching the impurity diffusion regions; a conductive plug embedded in one of the contact holes; a third insulating film formed on the second insulating film covering the conductive plug, and having a first aperture on the other contact hole; a bit line formed on the third insulating film and connected to the other impurity diffusion region through the first aperture and the other contact hole; a fourth insulating film covering the upper and side surfaces of the bit line; a second aperture formed through the third insulating film in alignment with the fourth insulating film covering the side surface of the bit line; a storage electrode formed to extend over the bit line, insulated from the bit line by the third and fourth insulating films, and electrically connected to the conductive plug through the second aperture.
摘要翻译：一种半导体存储器件，包括：覆盖栅电极的上表面和侧表面的第一绝缘膜; 形成在覆盖所述第一绝缘膜的所述基板上的第二绝缘膜; 形成在所述第二绝缘膜上并到达所述杂质扩散区的一对接触孔; 嵌入在所述接触孔之一中的导电插塞; 第三绝缘膜，形成在覆盖所述导电插塞的所述第二绝缘膜上，并且在所述另一个接触孔上具有第一孔; 形成在第三绝缘膜上并通过第一孔和另一个接触孔连接到另一个杂质扩散区的位线; 覆盖位线的上表面和侧表面的第四绝缘膜; 与覆盖所述位线的侧面的所述第四绝缘膜对准的通过所述第三绝缘膜形成的第二孔; 存储电极，其形成为在所述位线上延伸，通过所述第三和第四绝缘膜与所述位线绝缘，并且通过所述第二孔电连接到所述导电插塞。

6. 发明授权

US5521859A Semiconductor memory device having thin film transistor and method of producing the same 失效
标题翻译：具有薄膜晶体管的半导体存储器件及其制造方法
公开(公告)号：US5521859A
公开(公告)日：1996-05-28
申请号：US373502
申请日：1995-01-17
申请人： Taiji Ema , Kazuo Itabashi
发明人： Taiji Ema , Kazuo Itabashi
IPC分类号： B41J2/16 , H01L27/11 , G11C11/412
CPC分类号： H01L27/1108
摘要： A thin film transistor (TFT) load type static random access memory (SRAM) which includes a memory capacitor in addition to the stray capacitance. The SRAM includes a semiconductor substrate and a memory cell provided on the semiconductor substrate. The memory cell includes first and second transfer transistors, first and second driver transistors, first and second thin film transistor loads and first and second memory capacitors. The first and second memory capacitors include a storage electrode, a dielectric layer which covers the storage electrode, and an opposing electrode formed on the dielectric layer. A connection region is provided in which the storage electrode of the first memory capacitor, the drain region of the second thin film transistor load and the gate electrode of the first driver transistor are connected.
摘要翻译：薄膜晶体管（TFT）负载型静态随机存取存储器（SRAM），其除了杂散电容之外还包括存储电容器。 SRAM包括半导体衬底和设置在半导体衬底上的存储单元。存储单元包括第一和第二转移晶体管，第一和第二驱动晶体管，第一和第二薄膜晶体管负载以及第一和第二存储电容器。第一和第二存储电容器包括存储电极，覆盖存储电极的电介质层和形成在电介质层上的相对电极。提供了连接区域，其中第一存储电容器的存储电极，第二薄膜晶体管负载的漏极区域和第一驱动晶体管的栅极电极连接。

7. 发明授权

US5570311A SRAM semiconductor device 失效
标题翻译： SRAM半导体器件
公开(公告)号：US5570311A
公开(公告)日：1996-10-29
申请号：US189142
申请日：1994-01-31
申请人： Taiji Ema , Kazuo Itabashi , Kazuhiro Mizutani
发明人： Taiji Ema , Kazuo Itabashi , Kazuhiro Mizutani
IPC分类号： G11C11/412 , H01L21/8244 , H01L27/11 , G11C11/00
CPC分类号： H01L27/11 , G11C11/412 , Y10S257/904
摘要： An SRAM semiconductor device having a parallel connection of two series circuits each having a driver transistor and a load connected in series, a wiring for connecting an interconnection point between the driver transistor and load of each of the two series circuits to a control terminal of the driver transistor of the other of the two series circuits, and a transfer transistor connected to each interconnection point, wherein the driver transistor and transfer transistor each are an insulating gate field effect transistor having a channel region formed on the surface of a semiconductor substrate at a predetermined area, source/drain regions on both sides of the channel region, and an insulated gate above the channel region, and the transfer transistor has a resistor region having an impurity concentration lower than the source/drain regions on both sides of the channel region of the driver transistor, the resistor region being contiguous to the channel region of the transfer transistor.
摘要翻译：一种SRAM半导体器件，具有并联连接的两个串联电路，每个串联电路各自具有驱动晶体管和串联的负载;布线，用于将驱动晶体管和两个串联电路中的每一个的负载连接到控制端所述两个串联电路中的另一个的驱动晶体管和连接到每个互连点的传输晶体管，其中所述驱动晶体管和传输晶体管都是绝缘栅场效应晶体管，其具有在半导体衬底的表面上形成的沟道区沟道区两侧的预定区域，源极/漏极区域以及沟道区域上方的绝缘栅极，并且传输晶体管具有杂质浓度低于沟道区两侧的源极/漏极区域的电阻器区域驱动晶体管的电阻区域与转移转移体的沟道区域相邻 r。

8. 发明授权

US5323046A Semiconductor device and method for producing semiconductor device 失效
标题翻译：半导体装置及半导体装置的制造方法
公开(公告)号：US5323046A
公开(公告)日：1994-06-21
申请号：US910001
申请日：1992-07-07
申请人： Taiji Ema , Kazuo Itabashi
发明人： Taiji Ema , Kazuo Itabashi
IPC分类号： H01L27/10 , H01L27/11 , H01L29/417 , H01L29/04 , H01L21/469
CPC分类号： H01L29/41725 , H01L27/1108 , H01L27/1112
摘要： Semiconductor devices and methods for producing semiconductor devices to be produced by conducting a combination of a step for producing a gate elctrode of a first conductor layer which is piled on a gate insulator, a step for producing a drain region which is connected with an n.sup.+ -region located under the gate electrode by employing the gate electrode as a part of the mask, and a step for piling, on or over the gate electrode, a second conductor layer connected with the n.sup.+ -region through a contact hole produced in the gate electrode.
摘要翻译：用于制造半导体器件的半导体器件和方法，所述半导体器件通过进行叠层在栅极绝缘体上的第一导体层的栅极电极的制造步骤和用于制造与n + 通过使用栅电极作为掩模的一部分，位于栅电极下方的区域，以及在栅电极上或上方堆叠通过在栅电极中产生的接触孔与n +区连接的第二导体层的步骤。

9. 发明授权

US5612247A Method for fabricating isolation region for a semiconductor device 失效
标题翻译：制造半导体器件的隔离区域的方法
公开(公告)号：US5612247A
公开(公告)日：1997-03-18
申请号：US503823
申请日：1995-07-18
申请人： Kazuo Itabashi
发明人： Kazuo Itabashi
IPC分类号： H01L21/316 , H01L21/318 , H01L21/32 , H01L21/76 , H01L21/762 , H01L27/08
CPC分类号： H01L21/32 , H01L21/76216
摘要： The method for fabricating a semiconductor device comprising the steps of: forming a first oxide film 12 on a surface of a semiconductor substrate 10 and forming a first nitride film 14 on a surface of the first oxide film 12, the first nitride film 14 having a predetermined pattern; isotropically etching the first oxide film 12, with the first nitride film 14 as a mask, to partially expose the surface of the semiconductor substrate 10 and form a hollow 16 just under an end portion of the first nitride film 14; forming a second oxide film 18, thinner than the first oxide film 12, at least on the surface of the semiconductor substrate 10 exposed at the outside of the first nitride film 14 and on a inner surface of the hollow 16; depositing a second silicon nitride film 20 on at least the second oxide film 18, the second silicon nitride film 20 being more liable to oxidation than the first silicon nitride film 14; and oxidizing a region where the first silicon nitride film 14 is absent, with the first silicon nitride film 14 as a mask, to form a device isolation film 24. The second silicon nitride film 20 is formed of a silicon nitride film which is more liable to oxidation, so that when the device isolation film 24 is formed by oxidizing away the second silicon nitride film 20, thickness disuniformity can be decreased.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：在半导体衬底10的表面上形成第一氧化物膜12并在第一氧化膜12的表面上形成第一氮化物膜14，第一氮化物膜14具有预定图案; 对第一氧化膜12进行各向同性蚀刻，以第一氮化物膜14为掩模，部分地露出半导体衬底10的表面，并形成正好在第一氮化物膜14的端部下方的中空部16; 形成比第一氧化物膜12薄的第二氧化物膜18，至少在半导体衬底10的在第一氮化物膜14的外部暴露的表面上和中空部16的内表面上; 在至少第二氧化膜18上沉积第二氮化硅膜20，第二氮化硅膜20比第一氮化硅膜14更容易氧化; 并且以第一氮化硅膜14为掩模来氧化第一氮化硅膜14不存在的区域，以形成器件隔离膜24.第二氮化硅膜20由更容易形成的氮化硅膜形成使得当通过氧化掉第二氮化硅膜20来形成器件隔离膜24时，可以减小厚度不均匀性。

10. 发明授权

US5514615A Method of producing a semiconductor memory device having thin film transistor load 失效
标题翻译：制造具有薄膜晶体管负载的半导体存储器件的方法
公开(公告)号：US5514615A
公开(公告)日：1996-05-07
申请号：US441441
申请日：1995-05-15
申请人： Taiji Ema , Kazuo Itabashi
发明人： Taiji Ema , Kazuo Itabashi
IPC分类号： H01L27/11 , H01L21/70 , H01L27/00
CPC分类号： H01L27/1108
摘要： A method of producing a memory cell on a semiconductor substrate. The memory cell includes two transfer transistors, two driver transistors, two thin film transistor loads, and two memory capacitors. A field insulator layer is formed on the semiconductor substrate. A gate insulator layer is formed above the field insulator layer. A gate electrode of a driver transistor is produced by forming a first conductor layer above the gate insulator layer. Impurity regions are formed in the semiconductor substrate using the field insulator layer and the first conductor layer as masks. A first insulator layer is then formed. Source, drain and channel regions of a thin film transistor load are produced by forming a second conductor layer and injecting impurities into the second conductor layer. A second insulator layer is formed above the second conductor layer. A contact hole is formed to extend from the second insulator layer, through the second conductor layer, and to the first conductor layer. A storage electrode of a memory capacitor is produced by forming a third conductor layer which makes contact with the first conductor layer and the second conductor layer through the contact hole. A dielectric layer covering the storage electrode of the memory capacitor and a fourth conductor layer forming an opposing electrode of the memory capacitor are then successively produced.
摘要翻译：一种在半导体衬底上制造存储单元的方法。存储单元包括两个传输晶体管，两个驱动晶体管，两个薄膜晶体管负载和两个存储电容器。在半导体衬底上形成场绝缘体层。栅极绝缘体层形成在场绝缘体层的上方。通过在栅极绝缘体层上形成第一导体层来制造驱动晶体管的栅电极。使用场绝缘体层和第一导体层作为掩模在半导体衬底中形成杂质区域。然后形成第一绝缘体层。通过形成第二导体层并将杂质注入到第二导体层中来制造薄膜晶体管负载的源极，漏极和沟道区域。第二绝缘体层形成在第二导体层的上方。形成从第二绝缘体层穿过第二导电层延伸到第一导体层的接触孔。通过形成通过接触孔与第一导体层和第二导体层接触的第三导体层来制造存储电容器的存储电极。然后连续地制造覆盖存储电容器的存储电极的介质层和形成存储电容器的相对电极的第四导体层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式