专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07145215B2 Semiconductor device with a cavity therein and a method of manufacturing the same 失效
标题翻译：其中具有空腔的半导体器件及其制造方法
公开(公告)号：US07145215B2
公开(公告)日：2006-12-05
申请号：US11315796
申请日：2005-12-22
申请人： Kazumi Inoh , Hidemi Ishiuchi , Satoshi Matsuda , Ichiro Mizushima , Tsutomu Sato
发明人： Kazumi Inoh , Hidemi Ishiuchi , Satoshi Matsuda , Ichiro Mizushima , Tsutomu Sato
IPC分类号： H01L29/00
CPC分类号： H01L27/10894 , H01L21/76283 , H01L21/76289 , H01L21/764 , H01L21/84 , H01L27/0218 , H01L27/105 , H01L27/10829 , H01L27/1087 , H01L27/10885 , H01L27/10897 , H01L27/11 , H01L27/115 , H01L27/11502 , H01L27/1203 , H01L29/0649 , H01L29/66181 , H01L29/7841
摘要： A semiconductor device includes a semiconductor substrate, cavities, and an element isolating region. The cavities, which are each shaped like a flat plate, are made in the semiconductor substrate. The element isolating region is formed in the surface of the semiconductor substrate and located at the sides of the cavities.
摘要翻译：半导体器件包括半导体衬底，腔体和元件隔离区域。在半导体衬底中制造各自形状为平板的空腔。元件隔离区域形成在半导体衬底的表面并且位于空腔的侧面。

2. 发明申请

US20060157789A1 Semiconductor device with a cavity therein and a method of manufacturing the same 失效
公开(公告)号：US20060157789A1
公开(公告)日：2006-07-20
申请号：US11315796
申请日：2005-12-22
申请人： Kazumi Inoh , Hidemi Ishiuchi , Satoshi Matsuda , Ichiro Mizushima , Tsutomu Sato
发明人： Kazumi Inoh , Hidemi Ishiuchi , Satoshi Matsuda , Ichiro Mizushima , Tsutomu Sato
IPC分类号： H01L27/12
CPC分类号： H01L27/10894 , H01L21/76283 , H01L21/76289 , H01L21/764 , H01L21/84 , H01L27/0218 , H01L27/105 , H01L27/10829 , H01L27/1087 , H01L27/10885 , H01L27/10897 , H01L27/11 , H01L27/115 , H01L27/11502 , H01L27/1203 , H01L29/0649 , H01L29/66181 , H01L29/7841
摘要： A semiconductor device includes a semiconductor substrate, cavities, and an element isolating region. The cavities, which are each shaped like a flat plate, are made in the semiconductor substrate. The element isolating region is formed in the surface of the semiconductor substrate and located at the sides of the cavities.

3. 发明授权

US07009273B2 Semiconductor device with a cavity therein and a method of manufacturing the same 失效
公开(公告)号：US07009273B2
公开(公告)日：2006-03-07
申请号：US10665614
申请日：2003-09-19
申请人： Kazumi Inoh , Hidemi Ishiuchi , Satoshi Matsuda , Ichiro Mizushima , Tsutomu Sato
发明人： Kazumi Inoh , Hidemi Ishiuchi , Satoshi Matsuda , Ichiro Mizushima , Tsutomu Sato
IPC分类号： H01L29/00
CPC分类号： H01L27/10894 , H01L21/76283 , H01L21/76289 , H01L21/764 , H01L21/84 , H01L27/0218 , H01L27/105 , H01L27/10829 , H01L27/1087 , H01L27/10885 , H01L27/10897 , H01L27/11 , H01L27/115 , H01L27/11502 , H01L27/1203 , H01L29/0649 , H01L29/66181 , H01L29/7841
摘要： A semiconductor device includes a semiconductor substrate, cavities, and an element isolating region. The cavities, which are each shaped like a flat plate, are made in the semiconductor substrate. The element isolating region is formed in the surface of the semiconductor substrate and located at the sides of the cavities.

4. 发明授权

US06717251B2 Stacked type semiconductor device 有权
标题翻译：堆叠型半导体器件
公开(公告)号：US06717251B2
公开(公告)日：2004-04-06
申请号：US09961332
申请日：2001-09-25
申请人： Mie Matsuo , Nobuo Hayasaka , Tsunetoshi Arikado , Hidemi Ishiuchi , Koji Sakui , Chiaki Takubo
发明人： Mie Matsuo , Nobuo Hayasaka , Tsunetoshi Arikado , Hidemi Ishiuchi , Koji Sakui , Chiaki Takubo
IPC分类号： H01L2302
CPC分类号： H01L25/0657 , H01L25/0652 , H01L25/16 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2224/17181 , H01L2225/06513 , H01L2225/0652 , H01L2225/06541 , H01L2225/06572 , H01L2225/06596 , H01L2924/00014 , H01L2924/1627 , H01L2224/0401
摘要： Provided is a stacked type semiconductor device formed of a plurality of semiconductor integrated circuit devices stacked, each having a specification and including a semiconductor integrated circuit chip, wherein at least three of the semiconductor integrated circuit devices are stacked in the order of a value of the specification.
摘要翻译：本发明提供一种层叠型半导体器件，其由堆叠的多个半导体集成电路器件形成，每个半导体集成电路器件具有规格并且包括半导体集成电路芯片，其中至少三个半导体集成电路器件按照规范。

5. 发明授权

US4975754A Trench dual-gate MOSFET 失效
标题翻译：沟槽双栅极MOSFET
公开(公告)号：US4975754A
公开(公告)日：1990-12-04
申请号：US373059
申请日：1989-06-29
申请人： Hidemi Ishiuchi , Toshiharu Watanabe , Kinuyo Tanaka
发明人： Hidemi Ishiuchi , Toshiharu Watanabe , Kinuyo Tanaka
IPC分类号： H01L29/78
CPC分类号： H01L29/7827 , H01L29/7831
摘要： A trench dual-gate MOSFET comprises a projection which is bent to enclose a predetermined region on a semiconductor substrate of a first conductivity type. This projection is defined by a trench formed by selectively removing the surface region of the semiconductor substrate. A gate insulation film is formed on the side wall of the projection and on the semiconductor substrate portion located around the base of the projection. A gate electrode is formed on the side wall of the projection and on the semiconductor substrate portion located around the base of the projection, with the gate insulation film interposed and in a manner to surround the projection. A first impurity region of a second conductivity type, which serves as either a source or drain region, is formed in the top portion of the projection. A second impurity region of the second conductivity, which serves as either a drain or source region, is formed in the surface region of that portion of the semiconductor substrate which is located around the base of the projection.
摘要翻译：沟槽双栅极MOSFET包括弯曲以包围第一导电类型的半导体衬底上的预定区域的突起。该突起由通过选择性地去除半导体衬底的表面区域形成的沟槽限定。在突起的侧壁和位于突起的基部周围的半导体基板部分上形成栅极绝缘膜。在突起的侧壁和位于突起的基部周围的半导体基板部分上形成有栅电极，栅极绝缘膜以介于突起的方式插入。在突起的顶部形成有用作源极或漏极区域的第二导电类型的第一杂质区域。第二导电性的第二杂质区域，其用作漏极或源极区域，形成在半导体衬底的位于突起的基部周围的部分的表面区域中。

6. 发明授权

US4731342A Method of manufacturing a memory cell for a dynamic type random access memory 失效
标题翻译：制造用于动态型随机存取存储器的存储单元的方法
公开(公告)号：US4731342A
公开(公告)日：1988-03-15
申请号：US901520
申请日：1986-08-28
申请人： Hidemi Ishiuchi
发明人： Hidemi Ishiuchi
IPC分类号： H01L27/10 , H01L21/265 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L27/088 , H01L27/108 , H01L29/78 , H01L21/425
CPC分类号： H01L27/10861 , H01L21/2654 , H01L21/8238
摘要： A method of manufacturing a MOS semiconductor device which comprises a first step of forming a p-type well region in the surface of an n-type silicon substrate, a second step of forming a field oxide layer surrounding part of the surface of the well region, a third step of ion-implanting a n-type impurity into the surface of the well region, to reduce the carrier density of the well region in the vicinity of the ion-implanted without changing the conductivity type of the well region, a fourth step of forming a gate electrode insulatively on the ion-implanted surface of the well region, and a fifth step of forming the n.sup.+ -type source and drain regions in the ion-implanted surface of the well region. The third step of this manufacturing method uses the field oxide layer for implanting the n-type impurity, as a mask.
摘要翻译：一种制造MOS半导体器件的方法，包括在n型硅衬底的表面中形成p型阱区的第一步骤，形成围绕阱区表面的一部分的场氧化物层的第二步骤将n型杂质离子注入到阱区的表面的第3工序中，为了降低离子注入附近的阱区的载流子密度，不改变阱区的导电类型，在阱区的离子注入表面上绝缘地形成栅电极的步骤，以及在阱区的离子注入表面中形成n +型源区和漏区的第五步骤。该制造方法的第三步骤是使用场氧化物层作为掩模来注入n型杂质。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式