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1. 发明申请

US20060031724A1 Interleaving method and apparatus, de-interleaving method and apparatus, and interleaving/de-interleaving system and apparatus 有权
标题翻译：交错方法和装置，解交织方法和装置以及交织/解交织系统和装置
公开(公告)号：US20060031724A1
公开(公告)日：2006-02-09
申请号：US11246382
申请日：2005-10-07
申请人： Kazuhisa Ohbuchi , Takaharu Nakamura , Kazuo Kawabata
发明人： Kazuhisa Ohbuchi , Takaharu Nakamura , Kazuo Kawabata
IPC分类号： G06F11/00
CPC分类号： H03M13/2764 , H03M13/2703 , H03M13/2742
摘要： An interleaving apparatus comprises a first storing unit for storing data to be transmitted and a first control unit for controlling the first storing unit so that the data to be transmitted is outputted from the first storing unit with the data to be transmitted arranged in a matrix and at least either columns or rows of the data to be transmitted randomly rearranged, facilitating the interleaving. The result is that biased distribution of data, which leads to degradation of the transmission quality, can be prevented relatively easily in a simple structure.
摘要翻译：交织装置包括：第一存储单元，用于存储要发送的数据;以及第一控制单元，用于控制第一存储单元，使得待发送的数据从第一存储单元输出，要发送的数据以矩阵形式排列; 要传输的数据的至少一列或多行被随机重排，便于交织。结果是在简单的结构中可以相对容易地防止导致传输质量下降的数据偏置分布。

2. 发明授权

US06971050B1 Interleaving method and apparatus, de-interleaving method and apparatus, and interleaving/ de-interleaving system and apparatus 有权
标题翻译：交错方法和装置，解交织方法和装置以及交织/解交织系统和装置
公开(公告)号：US06971050B1
公开(公告)日：2005-11-29
申请号：US09301853
申请日：1999-04-29
申请人： Kazuhisa Ohbuchi , Takaharu Nakamura , Kazuo Kawabata
发明人： Kazuhisa Ohbuchi , Takaharu Nakamura , Kazuo Kawabata
IPC分类号： H04L1/00 , H03M13/27 , G06F11/00
CPC分类号： H03M13/2764 , H03M13/2703 , H03M13/2742
摘要： An interleaving apparatus comprises a first storing unit for storing data to be transmitted and a first control unit for controlling the first storing unit so that the data to be transmitted is outputted from the first storing unit with the data to be transmitted arranged in a matrix and at least either columns or rows of the data to be transmitted randomly rearranged, facilitating the interleaving. The result is that biased distribution of data, which leads to degradation of the transmission quality, can be prevented relatively easily in a simple structure.
摘要翻译：交织装置包括：第一存储单元，用于存储要发送的数据;以及第一控制单元，用于控制第一存储单元，使得待发送的数据从第一存储单元输出，要发送的数据以矩阵形式排列; 要传输的数据的至少一列或多行被随机重排，便于交织。结果是在简单的结构中可以相对容易地防止导致传输质量下降的数据偏置分布。

3. 发明授权

US07146545B2 Interleaving method and apparatus, de-interleaving method and apparatus, and interleaving/de-interleaving system and apparatus 有权
公开(公告)号：US07146545B2
公开(公告)日：2006-12-05
申请号：US11246382
申请日：2005-10-07
申请人： Kazuhisa Ohbuchi , Takaharu Nakamura , Kazuo Kawabata
发明人： Kazuhisa Ohbuchi , Takaharu Nakamura , Kazuo Kawabata
IPC分类号： G06F11/00
CPC分类号： H03M13/2764 , H03M13/2703 , H03M13/2742
摘要： An interleaving apparatus comprises a first storing unit for storing data to be transmitted and a first control unit for controlling the first storing unit so that the data to be transmitted is outputted from the first storing unit with the data to be transmitted arranged in a matrix and at least either columns or rows of the data to be transmitted randomly rearranged, facilitating the interleaving. The result is that biased distribution of data, which leads to degradation of the transmission quality, can be prevented relatively easily in a simple structure.

4. 发明授权

US06636549B1 Method for calculating phase shift coefficients of an M sequence 失效
标题翻译：用于计算M序列的相移系数的方法
公开(公告)号：US06636549B1
公开(公告)日：2003-10-21
申请号：US09154496
申请日：1998-09-16
申请人： Takaharu Nakamura , Kazuo Kawabata , Kazuhisa Ohbuchi
发明人： Takaharu Nakamura , Kazuo Kawabata , Kazuhisa Ohbuchi
IPC分类号： H04B169
CPC分类号： H04J13/0074 , G06F7/584 , G06F7/724 , H04B1/69 , H04J13/0025 , H04L9/0662
摘要： An n-bit binary value corresponding to an amount of phase shift d is assigned to an SREG, and a shift operation is performed. An n-bit vector value corresponding to a decimal value “1” is assigned to an LAT as an initial value. Thereafter, the input from an SW is sequentially stored. An MUL performs a square operation within a Galois field GF (2n) for the output of the LAT. A DBL performs a double operation within the Galois field GF (2n) for the output of the MUL. The SW selects either of the outputs of the MUL and the DBL according to the output value from the MSB side of the SREG. After the shift operation and the latch operation are performed a number of times n, the n-bit output of the LAT is output as respective phase shift coefficients b0 through bn−1.
摘要翻译：对应于相移量d的n位二进制值被分配给SREG，并且执行移位操作。将对应于十进制值“1”的n位向量值分配给LAT作为初始值。此后，依次存储来自SW的输入。 MUL在Galois域GF（2 ）内执行LAT的输出的平方运算。 DBL在Galois域GF（2 ）中执行双重操作以输出MUL。 SW根据SREG的MSB侧的输出值选择MUL和DBL的任一输出。在移位操作和锁存操作执行次数n之后，输出LAT的n位输出作为各自的相移系数b0至bn-1。

5. 发明授权

US07533306B2 Turbo decoding apparatus and interleave-deinterleave apparatus 有权
标题翻译： Turbo解码装置和交错解交织装置
公开(公告)号：US07533306B2
公开(公告)日：2009-05-12
申请号：US11296678
申请日：2005-12-07
申请人： Kazuhisa Obuchi , Tetsuya Yano , Kazuo Kawabata , Takaharu Nakamura
发明人： Kazuhisa Obuchi , Tetsuya Yano , Kazuo Kawabata , Takaharu Nakamura
IPC分类号： H03M13/27
CPC分类号： H03M13/2984 , H03M13/2707 , H03M13/275 , H03M13/2764 , H03M13/2767 , H03M13/2771 , H03M13/2782 , H03M13/2785 , H03M13/6505 , H04L1/005 , H04L1/0066 , H04L1/0071
摘要： In an apparatus such as a turbo decoding apparatus in which it is necessary to carry out interleave operation and deinterleave operation, there are provided a memory unit (5) and a memory control unit (12) capable of changing data writing order and data reading order with respect to the memory unit (5) depending on whether data is to be interleaved or deinterleaved. With this arrangement, the single unit of memory (5) can function as an interleaver and a deinterleaver, thereby reducing the size and cost the device.
摘要翻译：在需要执行交错操作和解交织操作的Turbo解码装置等装置中，设置有能够改变数据写入顺序和数据读取顺序的存储器单元（5）和存储器控制单元（12）相对于存储器单元（5），取决于数据是交织还是解交织。通过这种布置，单个存储器单元（5）可以用作交织器和解交织器，从而减小设备的尺寸和成本。

6. 发明授权

US06574766B2 Turbo decoding apparatus and interleave-deinterleave apparatus 有权
公开(公告)号：US06574766B2
公开(公告)日：2003-06-03
申请号：US09823564
申请日：2001-03-30
申请人： Kazuhisa Obuchi , Tetsuya Yano , Kazuo Kawabata , Takaharu Nakamura
发明人： Kazuhisa Obuchi , Tetsuya Yano , Kazuo Kawabata , Takaharu Nakamura
IPC分类号： H03M1329
CPC分类号： H03M13/2984 , H03M13/2707 , H03M13/275 , H03M13/2764 , H03M13/2767 , H03M13/2771 , H03M13/2782 , H03M13/2785 , H03M13/6505 , H04L1/005 , H04L1/0066 , H04L1/0071
摘要： In an apparatus such as a turbo decoding apparatus in which it is necessary to carry out interleave operation and deinterleave operation, there are provided a memory unit (5) and a memory control unit (12) capable of changing data writing order and data reading order with respect to the memory unit (5) depending on whether data is to be interleaved or deinterleaved. With this arrangement, the single unit of memory (5) can function as an interleaver and a deinterleaver, thereby reducing the size and cost the device.

7. 发明授权

US06993699B2 Turbo decoding apparatus and interleave-deinterleave apparatus 失效
标题翻译： Turbo解码装置和交错解交织装置
公开(公告)号：US06993699B2
公开(公告)日：2006-01-31
申请号：US10352515
申请日：2003-01-28
申请人： Kazuhisa Obuchi , Tetsuya Yano , Kazuo Kawabata , Takaharu Nakamura
发明人： Kazuhisa Obuchi , Tetsuya Yano , Kazuo Kawabata , Takaharu Nakamura
IPC分类号： H03M13/27 , H03M13/29
CPC分类号： H03M13/2984 , H03M13/2707 , H03M13/275 , H03M13/2764 , H03M13/2767 , H03M13/2771 , H03M13/2782 , H03M13/2785 , H03M13/6505 , H04L1/005 , H04L1/0066 , H04L1/0071
摘要： In an apparatus such as a turbo decoding apparatus in which it is necessary to carry out interleave operation and deinterleave operation, there are provided a memory unit (5) and a memory control unit (12) capable of changing data writing order and data reading order with respect to the memory unit (5) depending on whether data is to be interleaved or deinterleaved. With this arrangement, the single unit of memory (5) can function as an interleaver and a deinterleaver, thereby reducing the size and cost the device.
摘要翻译：在需要执行交错操作和解交织操作的Turbo解码装置等装置中，设置有能够改变数据写入顺序和数据读取顺序的存储器单元（5）和存储器控制单元（12）相对于存储器单元（5），取决于数据是交织还是解交织。通过这种布置，单个存储器单元（5）可以用作交织器和解交织器，从而减小设备的尺寸和成本。

8. 发明申请

US20060107163A1 Turbo decoding apparatus and interleave-deinterleave apparatus 有权
公开(公告)号：US20060107163A1
公开(公告)日：2006-05-18
申请号：US11296678
申请日：2005-12-07
申请人： Kazuhisa Obuchi , Tetsuya Yano , Kazuo Kawabata , Takaharu Nakamura
发明人： Kazuhisa Obuchi , Tetsuya Yano , Kazuo Kawabata , Takaharu Nakamura
IPC分类号： H04L1/00 , H03M13/00 , G08C25/00 , G06F11/00 , G06F11/30
CPC分类号： H03M13/2984 , H03M13/2707 , H03M13/275 , H03M13/2764 , H03M13/2767 , H03M13/2771 , H03M13/2782 , H03M13/2785 , H03M13/6505 , H04L1/005 , H04L1/0066 , H04L1/0071
摘要： In an apparatus such as a turbo decoding apparatus in which it is necessary to carry out interleave operation and deinterleave operation, there are provided a memory unit (5) and a memory control unit (12) capable of changing data writing order and data reading order with respect to the memory unit (5) depending on whether data is to be interleaved or deinterleaved. With this arrangement, the single unit of memory (5) can function as an interleaver and a deinterleaver, thereby reducing the size and cost the device.

9. 发明授权

US06320852B1 Base station host apparatus used in mobile communication system which employs a site diversity receiving method and a signal processing method 失效
标题翻译：在采用现场分集接收方式和信号处理方法的移动通信系统中使用的基站主机装置
公开(公告)号：US06320852B1
公开(公告)日：2001-11-20
申请号：US09033175
申请日：1998-03-02
申请人： Kazuhisa Obuchi , Takaharu Nakamura , Kazuo Kawabata , Hiroaki Iwamoto , Yoshiharu Tajima , Kenji Suda , Tetsuya Yano
发明人： Kazuhisa Obuchi , Takaharu Nakamura , Kazuo Kawabata , Hiroaki Iwamoto , Yoshiharu Tajima , Kenji Suda , Tetsuya Yano
IPC分类号： G08C1500
CPC分类号： H04L1/0059 , H04L1/0047 , H04L1/0061 , H04L1/06
摘要： A technique used in a mobile communications system. A mobile terminal station transmits a signal subjected to an error-correction encoding processing. Each of a plurality of base stations receives the signal transmitted from the mobile terminal station via the wireless line, performs an error-correction decoding processing for the received signal, and transmits an error-correction decoded signal to a base-station host apparatus via the wired line. The base-station host apparatus performs an error-correction encoding processing for each of the signals received from the base stations, composes the thus error-correction encoded signals into one signal, and performs an error-correction decoding processing for the composed signal. The technique can improve the error rate of a received signal without increasing the amount of signal data flowing between the base stations and the base-station host apparatus.
摘要翻译：用于移动通信系统的技术。移动终端发送经过纠错编码处理的信号。多个基站中的每一个基站经由无线线路接收从移动终端发送的信号，对接收到的信号进行纠错解码处理，并通过该基站主机装置向纠错解码信号发送纠错解码信号有线线。基站主机装置对从基站接收的每个信号执行纠错编码处理，将由此纠错编码的信号组成一个信号，并对合成信号进行纠错解码处理。该技术可以提高接收信号的错误率，而不会增加在基站和基站主机设备之间流动的信号数据量。

10. 发明授权

US06275520B1 Pseudo-noise generating apparatus 有权
标题翻译：伪噪声发生装置
公开(公告)号：US06275520B1
公开(公告)日：2001-08-14
申请号：US09198199
申请日：1998-11-23
申请人： Takaharu Nakamura , Kazuo Kawabata , Kazuhisa Obuchi , Hajime Hamada
发明人： Takaharu Nakamura , Kazuo Kawabata , Kazuhisa Obuchi , Hajime Hamada
IPC分类号： H04B1707
CPC分类号： H04J13/0022 , H04B1/707 , H04J13/10
摘要： A pseudo-noise generating apparatus capable of starting a pseudo-noise sequence from an arbitrary phase using compact processing circuitry. Tap selection patterns corresponding to a plurality of phase shift amounts are stored in advance in a ROM. By giving a phase shift amount to the ROM and setting the corresponding tap selection pattern in AND gates, the pseudo-noise sequence generated by the pseudo-noise generator is shifted in phase, and is loaded into a shift register. After setting a new phase amount in the ROM, the contents of the shift register are transferred into a shift register in the pseudo-noise generator. By repeating this operation, the desired phase shift is accomplished as a sum of a plurality of phase shift amounts.
摘要翻译：一种伪噪声发生装置，其能够使用紧凑的处理电路从任意相位开始伪噪声序列。将与多个相移量相对应的抽头选择模式预先存储在ROM中。通过给予ROM的相移量并将对应的抽头选择模式设置在与门中，由伪噪声发生器产生的伪噪声序列同相移位，并被加载到移位寄存器中。在ROM中设置新的相位量之后，移位寄存器的内容被传送到伪噪声发生器中的移位寄存器中。通过重复该操作，期望的相移作为多个相移量的总和来完成。

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