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1. 发明申请

US20060220667A1 Testing device and testing method of a semiconductor device 有权
公开(公告)号：US20060220667A1
公开(公告)日：2006-10-05
申请号：US11211094
申请日：2005-08-25
申请人： Kazuhiro Tashiro , Yasuyuki Itou , Shigeyuki Maruyama , Yoshikazu Arisaka
发明人： Kazuhiro Tashiro , Yasuyuki Itou , Shigeyuki Maruyama , Yoshikazu Arisaka
IPC分类号： G01R31/02
CPC分类号： G01R31/2887
摘要： A testing device can perform a test on an arbitrary one of a plurality of semiconductor devices by pressing the semiconductor devices onto a contactor from a back side of the semiconductor device. A test circuit board has a contactor provided with contact pieces corresponding to external connection terminals of semiconductor devices to be tested. A support board is capable of mounting the semiconductor devices thereon in an aligned state. A stage supports the support board. A press head presses the semiconductor devices to be tested mounted on the support board so as to cause external connection terminals of the semiconductor devices to be tested to contact with the contact pieces of the contactor. The stage is movable to a position at which at least one of the semiconductor devices to be tested, which are mounted on the support board, faces the contactor.

2. 发明授权

US07129726B2 Testing device and testing method of a semiconductor device 有权
标题翻译：半导体器件的测试装置和测试方法
公开(公告)号：US07129726B2
公开(公告)日：2006-10-31
申请号：US11211094
申请日：2005-08-25
申请人： Kazuhiro Tashiro , Yasuyuki Itou , Shigeyuki Maruyama , Yoshikazu Arisaka
发明人： Kazuhiro Tashiro , Yasuyuki Itou , Shigeyuki Maruyama , Yoshikazu Arisaka
IPC分类号： G01R31/02
CPC分类号： G01R31/2887
摘要： A testing device can perform a test on an arbitrary one of a plurality of semiconductor devices by pressing the semiconductor devices onto a contactor from a back side of the semiconductor device. A test circuit board has a contactor provided with contact pieces corresponding to external connection terminals of semiconductor devices to be tested. A support board is capable of mounting the semiconductor devices thereon in an aligned state. A stage supports the support board. A press head presses the semiconductor devices to be tested mounted on the support board so as to cause external connection terminals of the semiconductor devices to be tested to contact with the contact pieces of the contactor. The stage is movable to a position at which at least one of the semiconductor devices to be tested, which are mounted on the support board, faces the contactor.
摘要翻译：测试装置可以通过将半导体器件从半导体器件的背面按压到接触器上来对多个半导体器件中的任意一个进行测试。测试电路板具有接触器，该接触器具有与待测试的半导体器件的外部连接端子相对应的接触片。支撑板能够以对准状态将半导体器件安装在其上。舞台支持支持板。压头按压待安装在支撑板上的待测试的半导体器件，以便使半导体器件的外部连接端子被测试以与接触器的接触片接触。舞台可移动到安装在支撑板上的要测试的半导体器件中的至少一个面向接触器的位置。

3. 发明申请

US20060097356A1 Semiconductor substrate, manufacturing method of a semiconductor device and testing method of a semiconductor device 审中-公开
标题翻译：半导体衬底，半导体器件的制造方法和半导体器件的测试方法
公开(公告)号：US20060097356A1
公开(公告)日：2006-05-11
申请号：US11062488
申请日：2005-02-23
申请人： Shigeru Fujii , Yoshikazu Arisaka , Hitoshi Izuru , Kazuhiro Tashiro , Shigeyuki Maruyama
发明人： Shigeru Fujii , Yoshikazu Arisaka , Hitoshi Izuru , Kazuhiro Tashiro , Shigeyuki Maruyama
IPC分类号： H01L23/544
CPC分类号： H01L21/78 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor substrate eliminates a restriction caused by a width of scribe lines so as to increase a number of semiconductor elements formed on the semiconductor substrate. A plurality of semiconductor element areas are formed by forming a plurality of unit exposed and printed areas, each of which contains the semiconductor element areas. A first scribe line extends between the semiconductor element areas formed within the unit exposed and printed area. A second scribe line extends between the unit exposed and printed areas. A width of the first scribe line is different from a width of the second scribe line.
摘要翻译：半导体衬底消除了由划线的宽度引起的限制，从而增加形成在半导体衬底上的半导体元件的数量。多个半导体元件区域通过形成多个单位曝光和印刷区域而形成，每个单元暴露和印刷区域都包含半导体元件区域。第一刻划线在形成在单元曝光和印刷区域内的半导体元件区域之间延伸。第二划线在单元曝光和打印区域之间延伸。第一划线的宽度与第二划线的宽度不同。

4. 发明申请

US20080227226A1 Semiconductor substrate, manufacturing method of a semiconductor device and testing method of a semiconductor device 审中-公开
标题翻译：半导体衬底，半导体器件的制造方法和半导体器件的测试方法
公开(公告)号：US20080227226A1
公开(公告)日：2008-09-18
申请号：US12153481
申请日：2008-05-20
申请人： Shigeru Fujii , Yoshikazu Arisaka , Hitoshi Izuru , Kazuhiro Tashiro , Shigeyuki Maruyama
发明人： Shigeru Fujii , Yoshikazu Arisaka , Hitoshi Izuru , Kazuhiro Tashiro , Shigeyuki Maruyama
IPC分类号： H01L21/66 , H01L21/304
CPC分类号： H01L21/78 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor substrate eliminates a restriction caused by a width of scribe lines so as to increase a number of semiconductor elements formed on the semiconductor substrate. A plurality of semiconductor element areas are formed by forming a plurality of unit exposed and printed areas, each of which contains the semiconductor element areas. A first scribe line extends between the semiconductor element areas formed within the unit exposed and printed area. A second scribe line extends between the unit exposed and printed areas. A width of the first scribe line is different from a width of the second scribe line.
摘要翻译：半导体衬底消除了由划线的宽度引起的限制，从而增加形成在半导体衬底上的半导体元件的数量。多个半导体元件区域通过形成多个单位曝光和印刷区域而形成，每个单元暴露和印刷区域都包含半导体元件区域。第一刻划线在形成在单元曝光和印刷区域内的半导体元件区域之间延伸。第二划线在单元曝光和打印区域之间延伸。第一划线的宽度与第二划线的宽度不同。

5. 发明授权

US07355421B2 Semiconductor apparatus testing arrangement and semiconductor apparatus testing method 有权
标题翻译：半导体装置测试装置和半导体装置测试方法
公开(公告)号：US07355421B2
公开(公告)日：2008-04-08
申请号：US11339826
申请日：2006-01-26
申请人： Shigeyuki Maruyama , Yoshikazu Arisaka , Kazuhiro Tashiro , Takayuki Katayama , Tetsu Ozawa , Yuushin Kimura
发明人： Shigeyuki Maruyama , Yoshikazu Arisaka , Kazuhiro Tashiro , Takayuki Katayama , Tetsu Ozawa , Yuushin Kimura
IPC分类号： G01R31/02 , G01R31/26 , G06K5/04
CPC分类号： G01R1/0433
摘要： A semiconductor apparatus testing arrangement for testing a plurality of semiconductor devices produced on a semiconductor substrate, has a substrate on which a plurality of testing units are arranged, each unit comprising a probe needles corresponding to electrode terminals of the semiconductor device and electric conductor parts connected with the probe needles.
摘要翻译：一种用于测试在半导体衬底上制造的多个半导体器件的半导体器件测试装置，具有布置有多个测试单元的衬底，每个单元包括与半导体器件的电极端子相对应的探针和连接的导体部件用探针。

6. 发明申请

US20070096761A1 Semiconductor apparatus testing arrangement and semiconductor apparatus testing method 有权
标题翻译：半导体装置测试装置和半导体装置测试方法
公开(公告)号：US20070096761A1
公开(公告)日：2007-05-03
申请号：US11339826
申请日：2006-01-26
申请人： Shigeyuki Maruyama , Yoshikazu Arisaka , Kazuhiro Tashiro , Takayuki Katayama , Tetsu Ozawa , Yuushin Kimura
发明人： Shigeyuki Maruyama , Yoshikazu Arisaka , Kazuhiro Tashiro , Takayuki Katayama , Tetsu Ozawa , Yuushin Kimura
IPC分类号： G01R31/26
CPC分类号： G01R1/0433
摘要： A semiconductor apparatus testing arrangement for testing a plurality of semiconductor devices produced on a semiconductor substrate, has a substrate on which a plurality of testing units are arranged, each unit comprising a probe needles corresponding to electrode terminals of the semiconductor device and electric conductor parts connected with the probe needles.
摘要翻译：一种用于测试在半导体衬底上制造的多个半导体器件的半导体器件测试装置，具有布置有多个测试单元的衬底，每个单元包括与半导体器件的电极端子相对应的探针和连接的导体部件用探针。

7. 发明授权

US08671557B2 Tray in combination with electronic component attaching tool attached to the tray 失效
标题翻译：托盘与附在托盘上的电子元件连接工具组合
公开(公告)号：US08671557B2
公开(公告)日：2014-03-18
申请号：US13242647
申请日：2011-09-23
申请人： Daisuke Koizumi , Shigeyuki Maruyama , Kazuhiro Tashiro , Naoyuki Watanabe
发明人： Daisuke Koizumi , Shigeyuki Maruyama , Kazuhiro Tashiro , Naoyuki Watanabe
IPC分类号： B23P19/00
CPC分类号： B25B27/14 , H05K7/1061 , Y10T29/4913 , Y10T29/53174 , Y10T29/53178 , Y10T29/53183 , Y10T29/53187 , Y10T29/53191 , Y10T29/53943
摘要： A tray is provided in combination with an electronic component attaching tool attached to the tray and includes an attachment depression part that includes an inner wall and to which an electronic component is attached, wherein forming of the inner wall of the attachment depression part does not substantially depend on an external shape of the electronic component, and a standard part formed in the inner wall of the attachment depression part and engaging with a first structure part of the electronic component attaching tool to align a position of the electronic component attaching tool to the standard part when a position of the electronic component is aligned to a first position of the tray using the electronic component attaching tool, the standard part having a shape which does not substantially depend on the external shape of the electronic component.
摘要翻译：托盘与附接到托盘上的电子部件连接工具组合地提供，并且包括附接凹陷部分，该附件凹陷部分包括内壁并且附接有电子部件，其中，附接凹陷部分的内壁的形成基本上不取决于电子部件的外部形状，以及形成在安装凹部的内壁中的标准部分，并与电子部件安装工具的第一结构部分接合，以将电子部件安装工具的位置对准到标准当使用电子部件安装工具将电子部件的位置与托盘的第一位置对准时，标准部件具有基本上不依赖于电子部件的外形的形状。

8. 发明授权

US08164181B2 Semiconductor device packaging structure 有权
标题翻译：半导体器件封装结构
公开(公告)号：US08164181B2
公开(公告)日：2012-04-24
申请号：US12872131
申请日：2010-08-31
申请人： Kazuhiro Tashiro , Keisuke Fukuda , Naohito Kohashi , Shigeyuki Maruyama
发明人： Kazuhiro Tashiro , Keisuke Fukuda , Naohito Kohashi , Shigeyuki Maruyama
IPC分类号： H01L23/12
CPC分类号： H01L21/67333 , H01L21/50 , H01L22/20 , H01L23/04 , H01L23/544 , H01L25/0655 , H01L2223/54473 , H01L2924/0002 , H01L2924/014 , H01L2924/15311 , H01L2924/16153 , H01L2924/1616 , H01L2924/166 , Y10T29/49826 , H01L2924/00
摘要： A semiconductor device packaging structure is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device.
摘要翻译：公开了一种半导体器件封装结构，其可以提高半导体器件的性能测试的可靠性，并防止在运输或包装期间对半导体器件的损坏。由于包含半导体芯片和具有不同高度的电气部件，所以具有高度不均匀性的半导体器件附着IC盖。 IC盖包括突出部分和基部。在安装到半导体器件之后，突出部分位于半导体器件中的自由区域中，并且基底部分由与半导体芯片和半导体器件中的电气部件分离的突起支撑。 IC盖可拆卸地附接到半导体器件。

9. 发明申请

US20080203558A1 Method of semiconductor device protection, package of semiconductor device 有权
标题翻译：半导体器件保护方法，半导体器件封装
公开(公告)号：US20080203558A1
公开(公告)日：2008-08-28
申请号：US12081961
申请日：2008-04-24
申请人： Kazuhiro Tashiro , Keisuke Fukuda , Naohito Kohashi , Shigeyuki Maruyama
发明人： Kazuhiro Tashiro , Keisuke Fukuda , Naohito Kohashi , Shigeyuki Maruyama
IPC分类号： H01L23/12 , H01L21/00
CPC分类号： H01L21/67333 , H01L21/50 , H01L22/20 , H01L23/04 , H01L23/544 , H01L25/0655 , H01L2223/54473 , H01L2924/0002 , H01L2924/014 , H01L2924/15311 , H01L2924/16153 , H01L2924/1616 , H01L2924/166 , Y10T29/49826 , H01L2924/00
摘要： A method for protecting a semiconductor device is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device.
摘要翻译：公开了一种用于保护半导体器件的方法，其可以提高半导体器件的性能测试的可靠性，并防止在运输或包装期间对半导体器件的损坏。由于包含半导体芯片和具有不同高度的电气部件，所以具有高度不均匀性的半导体器件附着IC盖。 IC盖包括突出部分和基部。在安装到半导体器件之后，突出部分位于半导体器件中的自由区域中，并且基底部分由与半导体芯片和半导体器件中的电气部件分离的突起支撑。 IC盖可拆卸地附接到半导体器件。

10. 发明授权

US07161370B2 Semiconductor testing device 有权
标题翻译：半导体测试装置
公开(公告)号：US07161370B2
公开(公告)日：2007-01-09
申请号：US11046883
申请日：2005-02-01
申请人： Shigeyuki Maruyama , Kazuhiro Tashiro , Makoto Haseyama
发明人： Shigeyuki Maruyama , Kazuhiro Tashiro , Makoto Haseyama
IPC分类号： G01R31/26
CPC分类号： G01R31/308 , G01R31/302 , H01L2924/0002 , H05K3/326 , H01L2924/00
摘要： A semiconductor testing device is used for testing a semiconductor device which has at least one spherical connection terminal. The testing device includes an insulating substrate having an opening formed therein at a position corresponding to the position of the spherical connection terminal, and a contact member, formed on the insulating substrate, including a connection portion which is connected with the spherical connection terminal, at least the connection portion being deformable and extending into the opening.
摘要翻译：半导体测试装置用于测试具有至少一个球形连接端子的半导体器件。该测试装置包括：绝缘基板，其在与球形连接端子的位置对应的位置处形成有开口;以及接触部件，形成在绝缘基板上，包括与球形连接端子连接的连接部，所述连接部分至少可变形并延伸到所述开口中。

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