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1. 发明授权

US08533560B2 Controller, data storage device and program product 有权
标题翻译：控制器，数据存储设备和程序产品
公开(公告)号：US08533560B2
公开(公告)日：2013-09-10
申请号：US13218812
申请日：2011-08-26
申请人： Kazuhiro Fukutomi , Shinichi Kanno , Shigehiro Asano
发明人： Kazuhiro Fukutomi , Shinichi Kanno , Shigehiro Asano
IPC分类号： H03M13/00
CPC分类号： G06F11/1048
摘要： According to an embodiment of a controller, a bit string manipulating unit manipulates a bit string of manipulation target data based on a predetermined rule. A special data setting unit generates a magic number based on a special data setting request from a host interface, obtains an error detecting code for the magic number, and sends the magic number and the error detecting code as manipulation target data to the bit string manipulating unit to obtain a manipulated manipulation target data. The special data setting unit also extracts logical block address information from the special data setting request, and instructs an access unit to write the magic number in the manipulated manipulation target data to a user data storage area and to write the error detecting code in the manipulated manipulation target data to a redundant area in a storage area located by the logical block address information.
摘要翻译：根据控制器的实施例，位串操作单元基于预定规则来操纵操作对象数据的位串。专用数据设定部基于来自主机接口的特殊数据设定请求生成魔术数，获得魔术数的错误检测码，将魔术号码和错误检测码作为操作对象数据发送到位串操作单位以获得操纵的操纵目标数据。特殊数据设定单元还从特殊数据设定请求中提取逻辑块地址信息，并指示访问单元将操作操作目标数据中的魔术数字写入用户数据存储区域，并将错误检测码写入被操纵的将操作对象数据提供给由逻辑块地址信息定位的存储区域中的冗余区域。

2. 发明授权

US08812774B2 Memory system and computer program product 有权
标题翻译：内存系统和计算机程序产品
公开(公告)号：US08812774B2
公开(公告)日：2014-08-19
申请号：US13217461
申请日：2011-08-25
申请人： Shigehiro Asano , Shinichi Kanno , Kazuhiro Fukutomi , Akira Yamaga
发明人： Shigehiro Asano , Shinichi Kanno , Kazuhiro Fukutomi , Akira Yamaga
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F11/1068
摘要： According to an embodiment, a memory system includes semiconductor memories each having a plurality of blocks; a first table; a receiving unit; a generating unit; a second table; and a writing unit. The first table includes a plurality of memory areas each associated with each block and in each of which defect information is stored. The generating unit generates a set of blocks by selecting one block to which data are to be written in each semiconductor memory based on an index number indicating one of a plurality of rows in the first table and the first table. In the second table, an index number and a channel number are stored for each logical block address in association with one another. When a write command is received by the receiving unit, the writing unit writes data to a block associated with a selected channel number among blocks constituting the set.
摘要翻译：根据一个实施例，存储器系统包括每个具有多个块的半导体存储器; 第一张桌子接收单元; 发电机组; 第二个表和书写单位。第一表包括多个存储区，每个存储区与每个块相关联，并且每个存储区存储缺陷信息。生成单元基于指示第一表和第一表中的多行的索引号，选择要在每个半导体存储器中写入数据的一个块来生成一组块。在第二表中，对于每个逻辑块地址彼此相关联地存储索引号和通道号。当接收单元接收到写入命令时，写入单元将数据写入与构成该组的块中的所选频道号相关联的块。

3. 发明授权

US08397017B2 Controller and data storage device 有权
标题翻译：控制器和数据存储设备
公开(公告)号：US08397017B2
公开(公告)日：2013-03-12
申请号：US12723846
申请日：2010-03-15
申请人： Kenichiro Yoshii , Kazuhiro Fukutomi , Shinichi Kanno , Shigehiro Asano
发明人： Kenichiro Yoshii , Kazuhiro Fukutomi , Shinichi Kanno , Shigehiro Asano
IPC分类号： G06F13/00
CPC分类号： G06F12/0246 , G06F3/061 , G06F3/064 , G06F3/0679 , G06F2212/7207
摘要： A volatile management memory stores management information for managing a use state of a storage medium. A management information storing unit divides the management information into plural division pieces and individually stores them in the storage medium. A main controller receives a command from a host device while the division pieces are being stored, performs data processing for the storage medium in response to the command between each division piece is stored, updates the management information divided into the division pieces according to the data processing content, and creates a log representing an update content of the management information. A log storing unit stores the log in the storage medium. A restoring unit reads the division pieces stored in the storage medium to the management memory as the management information, updates the management information according to the log stored in the storage medium, and restores the updated management information.
摘要翻译：易失性管理存储器存储用于管理存储介质的使用状态的管理信息。管理信息存储单元将管理信息分成多个分割片，并将它们分别存储在存储介质中。主控制器在存储分割片的同时从主机装置接收命令，根据存储各分割片之间的命令对存储介质执行数据处理，根据数据更新分割成分割片的管理信息处理内容，并创建表示管理信息的更新内容的日志。日志存储单元将日志存储在存储介质中。恢复单元将存储在存储介质中的分割信息作为管理信息读取到管理存储器，根据存储在存储介质中的日志更新管理信息，并恢复更新的管理信息。

4. 发明申请

US20120072811A1 CONTROLLER, STORAGE APPARATUS, AND COMPUTER PROGRAM PRODUCT 有权
标题翻译：控制器，存储设备和计算机程序产品
公开(公告)号：US20120072811A1
公开(公告)日：2012-03-22
申请号：US13035194
申请日：2011-02-25
申请人： Kazuhiro FUKUTOMI , Hiroshi Yao , Shinichi Kanno , Shigehiro Asano , Toshikatsu Hida , Yasuhiro Kimura
发明人： Kazuhiro FUKUTOMI , Hiroshi Yao , Shinichi Kanno , Shigehiro Asano , Toshikatsu Hida , Yasuhiro Kimura
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： G06F11/108 , G06F2211/1059 , G06F2211/1073 , G06F2211/1092
摘要： According to one embodiment, a controller controls writing into and reading from a storage apparatus that includes a first data-storage unit and a second data-storage unit. The second data-storage unit stores user data and parity data of the user data. The first data-storage unit stores the parity data. The controller includes a parity updating unit and a parity writing unit. When parity data is updated, the parity updating unit writes the updated parity data into the first data-storage unit. When a certain requirement is satisfied, the parity writing unit reads the parity data written in the first data-storage unit, and writes the parity data thus read into the second data-storage unit.
摘要翻译：根据一个实施例，控制器控制对包括第一数据存储单元和第二数据存储单元的存储装置的写入和读取。第二数据存储单元存储用户数据和用户数据的奇偶校验数据。第一数据存储单元存储奇偶校验数据。控制器包括奇偶校验更新单元和奇偶校验写入单元。当更新奇偶校验数据时，奇偶校验更新单元将更新的奇偶校验数据写入第一数据存储单元。当满足特定要求时，奇偶写入单元读取写入第一数据存储单元中的奇偶校验数据，并将读出的奇偶校验数据写入第二数据存储单元。

5. 发明授权

US07984325B2 Storage control device, data recovery device, and storage system 有权
标题翻译：存储控制装置，数据恢复装置和存储系统
公开(公告)号：US07984325B2
公开(公告)日：2011-07-19
申请号：US12398608
申请日：2009-03-05
申请人： Kazuhiro Fukutomi , Hideaki Sato , Shinichi Kanno , Shigehiro Asano
发明人： Kazuhiro Fukutomi , Hideaki Sato , Shinichi Kanno , Shigehiro Asano
IPC分类号： G06F11/00
CPC分类号： G06F11/108 , G06F11/1068
摘要： When data in one semiconductor memory device is corrupted during a padding process by a padding unit and the data cannot be recovered even by using an error correcting code for correcting a data error, a storage control device issues a data recovery request to a data recovery device. The data recovery device reads the data from other semiconductor memory device in response to the data recovery request to recover the data, and returns a recovery result to the padding unit in the storage control device to perform the padding process.
摘要翻译：当一个半导体存储器件中的数据在填补单元的填充处理期间被破坏时，即使通过使用用于校正数据错误的纠错码也不能恢复数据，存储控制装置向数据恢复装置发出数据恢复请求。数据恢复装置响应于数据恢复请求从其他半导体存储装置读取数据以恢复数据，并将恢复结果返回到存储控制装置中的填充单元以执行填充处理。

6. 发明申请

US20100223531A1 SEMICONDUCTOR STORAGE 失效
标题翻译：半导体存储
公开(公告)号：US20100223531A1
公开(公告)日：2010-09-02
申请号：US12713631
申请日：2010-02-26
申请人： Kazuhiro FUKUTOMI , Hideaki Sato , Shinichi Kanno , Shigehiro Asano
发明人： Kazuhiro FUKUTOMI , Hideaki Sato , Shinichi Kanno , Shigehiro Asano
IPC分类号： H03M13/05 , G06F12/16 , G06F11/10
CPC分类号： G06F11/108 , G06F11/1052
摘要： A semiconductor storage includes a receiver configured to receive a write request from a host device; a storage unit configured to hold redundancy data generation/non-generation information; a writing unit configured to write data in a semiconductor memory array and write redundancy data generation/non-generation information of the written data in the storage unit; a first data extracting unit configured to extract data whose redundancy data is not generated from among the data held by the semiconductor memory array; a first redundancy data generating unit configured to generate redundancy data; a first redundancy data writing unit configured to write the generated redundancy data in the semiconductor memory array; and a first redundancy data generation/non-generation information updating unit configured to update the redundancy data generation/non-generation information of the data whose redundancy data held by the storage unit is generated.
摘要翻译：半导体存储器包括被配置为从主机设备接收写请求的接收器; 存储单元，被配置为保存冗余数据生成/非生成信息; 写入单元，被配置为在半导体存储器阵列中写入数据，并将写入的数据的冗余数据生成/非生成信息写入存储单元中; 第一数据提取单元，被配置为从半导体存储器阵列保存的数据中提取不产生冗余数据的数据; 第一冗余数据生成单元，被配置为生成冗余数据; 第一冗余数据写入单元，被配置为将所生成的冗余数据写入所述半导体存储器阵列中; 以及第一冗余数据生成/非生成信息更新单元，被配置为更新由所述存储单元保持的冗余数据生成的数据的冗余数据生成/非生成信息。

7. 发明授权

US08549388B2 Controller, storage apparatus, and computer program product 有权
标题翻译：控制器，存储设备和计算机程序产品
公开(公告)号：US08549388B2
公开(公告)日：2013-10-01
申请号：US13035194
申请日：2011-02-25
申请人： Kazuhiro Fukutomi , Hiroshi Yao , Shinichi Kanno , Shigehiro Asano , Toshikatsu Hida , Yasuhiro Kimura
发明人： Kazuhiro Fukutomi , Hiroshi Yao , Shinichi Kanno , Shigehiro Asano , Toshikatsu Hida , Yasuhiro Kimura
IPC分类号： H03M13/00
CPC分类号： G06F11/108 , G06F2211/1059 , G06F2211/1073 , G06F2211/1092
摘要： According to one embodiment, a controller controls writing into and reading from a storage apparatus that includes a first data-storage unit and a second data-storage unit. The second data-storage unit stores user data and parity data of the user data. The first data-storage unit stores the parity data. The controller includes a parity updating unit and a parity writing unit. When parity data is updated, the parity updating unit writes the updated parity data into the first data-storage unit. When a certain requirement is satisfied, the parity writing unit reads the parity data written in the first data-storage unit, and writes the parity data thus read into the second data-storage unit.
摘要翻译：根据一个实施例，控制器控制对包括第一数据存储单元和第二数据存储单元的存储装置的写入和读取。第二数据存储单元存储用户数据和用户数据的奇偶校验数据。第一数据存储单元存储奇偶校验数据。控制器包括奇偶校验更新单元和奇偶校验写入单元。当更新奇偶校验数据时，奇偶校验更新单元将更新的奇偶校验数据写入第一数据存储单元。当满足特定要求时，奇偶写入单元读取写入第一数据存储单元中的奇偶校验数据，并将读出的奇偶校验数据写入第二数据存储单元。

8. 发明申请

US20130238838A1 CONTROLLER, STORAGE DEVICE, AND COMPUTER PROGRAM PRODUCT 审中-公开
标题翻译：控制器，存储设备和计算机程序产品
公开(公告)号：US20130238838A1
公开(公告)日：2013-09-12
申请号：US13603989
申请日：2012-09-05
申请人： Kazuhiro FUKUTOMI , Shinichi Kanno , Shigehiro Asano
发明人： Kazuhiro FUKUTOMI , Shinichi Kanno , Shigehiro Asano
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F12/02 , G06F12/0802 , G06F12/0859 , G06F12/0868 , G06F12/0871 , G06F12/0873 , G06F2212/604 , G06F2212/7202 , G06F2212/7203
摘要： According to an embodiment, a controller is connected to an external storage device and controls access to a semiconductor storage device including blocks each including memory cell groups each having memory cells. The block includes pages associated with each memory cell group. A writing process for each memory cell group includes writing stages. The controller includes a determining unit configured to determine data to be transferred to the page required in the writing process for a first memory cell group before the writing stage first starts when the writing stage is performed; a reading unit configured to read the determined data from the semiconductor storage device and to store the read data in the external storage device before the writing stage starts; and a writing unit configured to perform the writing process using the data stored in the external storage device when the writing stage is performed.
摘要翻译：根据实施例，控制器连接到外部存储装置，并且控制对包括各自包含存储单元的存储单元组的块的半导体存储装置的访问。该块包括与每个存储器单元组相关联的页面。每个存储单元组的写入过程包括写入阶段。控制器包括：确定单元，被配置为在执行写入阶段时，在写入阶段首先开始之前，确定要传送到第一存储单元组的写入处理所需的页面的数据; 读取单元，其被配置为从所述半导体存储装置读取所确定的数据，并且在所述写入阶段开始之前将读取的数据存储在所述外部存储装置中; 以及写入单元，被配置为当执行写入阶段时，使用存储在外部存储装置中的数据执行写入处理。

9. 发明授权

US08453033B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08453033B2
公开(公告)日：2013-05-28
申请号：US12885962
申请日：2010-09-20
申请人： Kenichiro Yoshii , Kazuhiro Fukutomi , Shinichi Kanno , Shigehiro Asano
发明人： Kenichiro Yoshii , Kazuhiro Fukutomi , Shinichi Kanno , Shigehiro Asano
IPC分类号： H03M13/09
CPC分类号： G06F11/1048
摘要： According to one embodiment, a semiconductor memory device includes semiconductor memory chips having writable storage regions in which data is written. The data has one or more pieces of first data, and one or more pieces of the first data includes second data. The device includes a determining unit that determines a prescribed number or fewer of semiconductor memory chips to which the first data is written; a write controller that writes the the first data and redundant information calculated from the second data and used for correcting an error in the second data into the writable storage regions in the determined semiconductor memory chips; and a storage unit that stores identification information and region specifying information associated with each other. The identification information associates the second data and the redundant information, and the region specifying information specifies the storage regions in the semiconductor memory chips to which the first data included in the second data and the redundant information are written.
摘要翻译：根据一个实施例，半导体存储器件包括具有可写入存储区域的数据被写入的半导体存储器芯片。数据具有一个或多个第一数据，并且一个或多个第一数据包括第二数据。该装置包括：确定单元，其确定写入第一数据的半导体存储器芯片的规定数量以下; 写入控制器，其将从第二数据计算出的第一数据和冗余信息写入第二数据中的错误，并将其写入到所确定的半导体存储器芯片中的可写入存储区域中; 以及存储单元，其存储彼此相关联的识别信息和区域指定信息。所述识别信息将所述第二数据和所述冗余信息相关联，并且所述区域指定信息指定在所述第二数据中包含的所述第一数据和所述冗余信息被写入的所述半导体存储器芯片中的存储区域。

10. 发明授权

US08392476B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08392476B2
公开(公告)日：2013-03-05
申请号：US12885941
申请日：2010-09-20
申请人： Shigehiro Asano , Kenichiro Yoshii , Kazuhiro Fukutomi , Shinichi Kanno
发明人： Shigehiro Asano , Kenichiro Yoshii , Kazuhiro Fukutomi , Shinichi Kanno
IPC分类号： G06F17/30
CPC分类号： G06F12/0246 , G06F2212/7205
摘要： According to one embodiment, a semiconductor memory device performs writing of data to a semiconductor memory element in response to a request to write the data with a specified logical block address from a host and performs writing of valid data to the semiconductor memory element for compaction according to a log-structured method. The semiconductor memory device adjusts a frequency of the writing response to a request from the host and a frequency of the writing for compaction according to a predetermined ratio.
摘要翻译：根据一个实施例，半导体存储器件响应于从主机以指定的逻辑块地址写入数据的请求，执行将数据写入到半导体存储器元件，并且执行将有效数据写入半导体存储元件以进行压缩以日志结构的方式。半导体存储器装置根据预定的比例调整来自主机的请求的写入响应的频率和用于压缩的写入频率。

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