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1. 发明授权

US5367490A Semiconductor integrated circuit device with two variable delay lines in writing circuit control 失效
标题翻译：半导体集成电路器件具有两个可变延迟线，用于写入电路控制
公开(公告)号：US5367490A
公开(公告)日：1994-11-22
申请号：US967133
申请日：1992-10-27
申请人： Kazuhiro Akimoto , Masami Usami , Katsumi Ogiue , Hiroshi Murayama , Hitoshi Abe , Masamori Kashiyama , Yoshikuni Kobayashi , Satoru Isomura , Kinya Mitsumoto
发明人： Kazuhiro Akimoto , Masami Usami , Katsumi Ogiue , Hiroshi Murayama , Hitoshi Abe , Masamori Kashiyama , Yoshikuni Kobayashi , Satoru Isomura , Kinya Mitsumoto
IPC分类号： G11C5/02 , G11C7/10 , G11C7/22 , H03K5/24 , G11C7/00
CPC分类号： G11C7/22 , G11C5/025 , G11C7/10 , H03K5/2418
摘要： Disclosed is a semiconductor integrated circuit wherein a logic circuit for exchanging signals with RAMS, with the RAMS being disposed centrally on the semiconductor chip or substrate, is divided into a plurality of logic circuits in accordance with the kind of signals and the divided logic circuits are disposed around the RAM in such a manner as to minimize the distance of signal transmission paths with the RAM and in order to attain high speed access to RAMS.
摘要翻译：公开了一种半导体集成电路，其中用于与RAMS交换信号的逻辑电路，其中RAMS被布置在半导体芯片或基板上的中心处，根据信号的种类被分成多个逻辑电路，并且分开的逻辑电路是以使得与RAM的信号传输路径的距离最小化的方式设置在RAM周围，并且为了实现对RAMS的高速访问。

2. 发明授权

US5014242A Semiconductor device for a ram disposed on chip so as to minimize distances of signal paths between the logic circuits and memory circuit 失效
标题翻译：设置在芯片上的RAM的半导体器件，以便最小化逻辑电路和存储器电路之间的信号路径的距离
公开(公告)号：US5014242A
公开(公告)日：1991-05-07
申请号：US281399
申请日：1988-12-08
申请人： Kazuhiro Akimoto , Masami Usami , Katsumi Ogiue , Hiroshi Murayama , Hitoshi Abe , Masamori Kashiyama , Yoshikuni Kobayashi , Satoru Isomura , Kinya Mitsumoto
发明人： Kazuhiro Akimoto , Masami Usami , Katsumi Ogiue , Hiroshi Murayama , Hitoshi Abe , Masamori Kashiyama , Yoshikuni Kobayashi , Satoru Isomura , Kinya Mitsumoto
IPC分类号： G11C5/02 , G11C7/10 , G11C7/22 , H03K5/24
CPC分类号： G11C7/22 , G11C5/025 , G11C7/10 , H03K5/2418
摘要： Disclosed is a semiconductor integrated circuit wherein a logic circuit for exchanging signals with RAMS, with the RAMS being disposed centrally on the semiconductor chip or substrate, is divided into a plurality of logic circuits in accordance with the kind of signals and the divided logic circuits are disposed around the RAM in such a manner as to minimize the distance of signal transmission paths with the RAM and in order to attain high speed access to RAMS.
摘要翻译：公开了一种半导体集成电路，其中用于与RAMS交换信号的逻辑电路，其中RAMS被布置在半导体芯片或基板上的中心处，根据信号的种类被分成多个逻辑电路，并且分开的逻辑电路是以使得与RAM的信号传输路径的距离最小化的方式设置在RAM周围，并且为了实现对RAMS的高速访问。

3. 发明授权

US5646897A Logic gate circuit and parallel bit test circuit for semiconductor memory devices, capable of operation at low power source levels 失效
标题翻译：用于半导体存储器件的逻辑门电路和并行位测试电路，能够在低电源电平下工作
公开(公告)号：US5646897A
公开(公告)日：1997-07-08
申请号：US426384
申请日：1995-04-21
申请人： Seigou Yukutake , Masahiro Iwamura , Kinya Mitsumoto , Takashi Akioka , Noboru Akiyama
发明人： Seigou Yukutake , Masahiro Iwamura , Kinya Mitsumoto , Takashi Akioka , Noboru Akiyama
IPC分类号： G11C7/10 , G11C29/34 , G11C29/50 , G11C7/00
CPC分类号： G11C29/028 , G11C29/50 , G11C7/1051 , G11C11/41 , G11C2029/5004 , G11C29/34
摘要： A logic circuit is provided for a memory device which can be operated at a high speed with a lower voltage power source level than conventional devices. This logic circuit can be used in a multi-bit test circuit executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, receiving the output of the wired-OR-logic operation by an emitter follower using a bipolar transistor, and outputting an AND signal of the complementary logic signals by a level comparing circuit. A sense amplifier is also provided for executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, raising the level of the output of the wired-OR-logic operation by a level shift circuit having a semiconductor element for applying an inverse bias potential to an input signal, executing the wired-OR-operation of the shifted up output and outputs from other blocks, and receiving and amplifying the output of the wired-OR-logic operation.
摘要翻译：提供了一种用于存储器件的逻辑电路，其可以以比传统器件更低的电压电源电平在高速下操作。该逻辑电路可以用于执行来自多个预读取放大器的互补逻辑信号的有线或逻辑运算的多位测试电路，通过射极跟随器接收有线或逻辑运算的输出，使用双极晶体管，并通过电平比较电路输出互补逻辑信号的“与”信号。还提供读出放大器，用于执行来自多个预读放大器的互补逻辑信号的有线或逻辑运算，通过具有半导体的电平移位电路提高布线或逻辑运算的输出电平元件，用于对输入信号施加反向偏置电位，执行移位上升输出的线或运算和其他块的输出，以及接收和放大有线逻辑运算的输出。

4. 发明授权

US07623397B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07623397B2
公开(公告)日：2009-11-24
申请号：US11514101
申请日：2006-09-01
申请人： Noriyuki Itano , Kinya Mitsumoto
发明人： Noriyuki Itano , Kinya Mitsumoto
IPC分类号： G11C7/00 , G11C5/06 , G11C8/00 , H01L25/00
CPC分类号： H03L7/0812 , G06F1/04 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C7/222 , H01L2224/04105 , H01L2224/12105 , H01L2224/20
摘要： A semiconductor device with a packaging circuit portion connected to a semiconductor chip therein. The semiconductor chip includes a plurality of pad electrodes, and the packaging circuit portion includes wiring connected to the pad electrodes on the semiconductor chip, mounting terminals, and a first signal path for receiving a signal output from the predetermined one of the pad electrodes and transmitting the signal to other one of the pad electrodes. The first signal path includes delay elements comparable to delays in a second signal path extending from the predetermined one of the mounting terminals to the other one of the mounting terminals through the semiconductor chip, and is disposed on a feedback path for phase comparison for synchronizing the phase of an output signal from the second signal path to the phase of an input signal to the second signal path.
摘要翻译：一种具有与其中的半导体芯片连接的封装电路部分的半导体器件。半导体芯片包括多个焊盘电极，封装电路部分包括连接到半导体芯片上的焊盘电极的布线，安装端子，以及用于接收从预定的一个焊盘电极输出的信号的第一信号路径，信号到另一个焊盘电极。第一信号路径包括延迟元件，该延迟元件与从安装端子中的预定安装端子到另一个安装端子延伸穿过半导体芯片的第二信号路径中的延迟相比较，并且设置在用于相位比较的反馈路径上用于使从第二信号路径到输入信号到第二信号路径的相位的输出信号的相位。

5. 发明授权

US07068551B2 Semiconductor memory device 失效
公开(公告)号：US07068551B2
公开(公告)日：2006-06-27
申请号：US11046690
申请日：2005-02-01
申请人： Hiroki Ueno , Takashi Akioka , Kinya Mitsumoto , Akihisa Aoyama , Masao Shinozaki
发明人： Hiroki Ueno , Takashi Akioka , Kinya Mitsumoto , Akihisa Aoyama , Masao Shinozaki
IPC分类号： G11C7/00
CPC分类号： G11C5/063 , G11C7/02 , G11C7/1048 , G11C7/18 , G11C11/419 , H01L27/11
摘要： Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.

6. 发明授权

US5761150A Synchronous memory with pipelined write operation 失效
标题翻译：具有流水线写入操作的同步存储器
公开(公告)号：US5761150A
公开(公告)日：1998-06-02
申请号：US651873
申请日：1996-05-21
申请人： Seigoh Yukutake , Kinya Mitsumoto , Takashi Akioka , Masahiro Iwamura , Noboru Akiyama
发明人： Seigoh Yukutake , Kinya Mitsumoto , Takashi Akioka , Masahiro Iwamura , Noboru Akiyama
IPC分类号： G11C11/413 , G06F12/00 , G11C7/10 , G11C8/06 , G11C11/401 , G11C11/407 , G11C11/418 , G11C8/00 , G11C7/00
CPC分类号： G11C8/06 , G11C11/418 , G11C7/1072 , G11C2207/2218
摘要： There is provided a method of controlling an internal address signal of an RAM in which a late-write method is realized on a chip. Two sets of address registers for reading and writing are provided for each address and further a middle register is provided between the two sets of address registers. The middle register is controlled by a signal formed by obtaining the AND result of a clock signal and a write enable signal and the two sets of address registers for reading and writing are controlled only by the clock signal. A selection circuit selects outputs of the two sets of address registers as an input in accordance with the write enable signal to control an internal address.
摘要翻译：提供了一种控制RAM的内部地址信号的方法，其中在芯片上实现了后期写入方法。为每个地址提供两组用于读取和写入的地址寄存器，并且还在两组地址寄存器之间提供中间寄存器。中间寄存器由通过获得时钟信号和写入使能信号的AND结果而形成的信号控制，并且用于读取和写入的两组地址寄存器仅由时钟信号控制。选择电路根据写使能信号选择两组地址寄存器的输出作为输入，以控制内部地址。

7. 发明授权

US5654931A High-speed semiconductor memory device and data processing system using the same 失效
标题翻译：高速半导体存储器件和数据处理系统使用相同
公开(公告)号：US5654931A
公开(公告)日：1997-08-05
申请号：US213531
申请日：1994-03-16
申请人： Akihiro Tamba , Masahiro Iwamura , Yutaka Kobayashi , Kinya Mitsumoto , Tatsumi Yamauchi , Shuko Yamauchi , Takashi Akioka
发明人： Akihiro Tamba , Masahiro Iwamura , Yutaka Kobayashi , Kinya Mitsumoto , Tatsumi Yamauchi , Shuko Yamauchi , Takashi Akioka
IPC分类号： G11C7/22 , G11C13/00
CPC分类号： G11C7/22
摘要： A semiconductor integrated circuit device is divided into a plurality of blocks, which are individually equipped with signal generate units such that the signal generate units are distributed in the semiconductor integrated circuit device. The semiconductor integrated circuit device is preferably constructed to generate the pulse signal by the pulse generate units which are provided for the individual blocks, after all initial logic operations on the data and control signals have been taken. Thanks to this construction, an SRAM, for example, can have its write recovery time minimized to 0 so that it can achieve high-speed operations. Moreover, since predecoders are provided for the individual blocks, the wiring line number and area in the chip can be reduced to improve the degree of integration of the semiconductor integrated circuit device. Still moreover, signal delay and skew can be reduced in the chip so that high-speed can be achieved. Another feature is that either the input/output pads of the data into or out of the semiconductor integrated circuit device or their accompanying circuit units are distributed in the semiconductor integrated circuit device. The individual features described above can be used solely or in combination, if necessary, to achieve the above-specified objects.
摘要翻译：半导体集成电路器件被分成多个块，它们分别配备有信号生成单元，使得信号生成单元分布在半导体集成电路器件中。优选地，半导体集成电路器件被构造为在对数据和控制信号进行了所有初始逻辑运算之后，通过针对各个块提供的脉冲产生单元产生脉冲信号。由于这种结构，例如，SRAM可以将其写恢复时间最小化为0，从而可以实现高速操作。此外，由于为每个块提供预编码器，所以可以减少芯片中的布线数量和面积，以提高半导体集成电路器件的集成度。此外，芯片中的信号延迟和偏斜可以降低，从而可以实现高速度。另一个特征是将半导体集成电路器件的数据的输入/输出焊盘或其相应的电路单元分布在半导体集成电路器件中。如果需要，可以单独地或组合地使用上述各个特征来实现上述目的。

8. 发明授权

US5631600A Reference current generating circuit for generating a constant current 失效
标题翻译：用于产生恒定电流的基准电流产生电路
公开(公告)号：US5631600A
公开(公告)日：1997-05-20
申请号：US361722
申请日：1994-12-23
申请人： Takashi Akioka , Kinya Mitsumoto , Yutaka Kobayashi
发明人： Takashi Akioka , Kinya Mitsumoto , Yutaka Kobayashi
IPC分类号： G05F3/26 , G05F3/02
CPC分类号： G05F3/267
摘要： A constant current generating circuit is provided with a first current generating circuit unit which generates a first current having a positive temperature dependency and includes a pair of first and second bipolar transistors, a first current mirror circuit comprised of a plurality of first MOS transistors which regulates a current density ratio of the currents fed to the first and second bipolar transistors to be constant and derives the first current and a first circuit disposed between the first and second bipolar transistors and the first current mirror circuit for limiting dependency of the currents flowing through the first and second bipolar transistors on a voltage of a power source applied to the first current mirror circuit, a second current generating circuit unit is also provided which generates a second current having as negative temperature dependency and which includes a third bipolar transistor and a second resistor through which the second current is derived. Also, a summing current generating circuit unit is provided which sums the first current and the second current and generates a constant current with substantially no temperature dependency representing the summed current. This summary current generating circuit unit includes a second current mirror circuit comprised of a plurality of second MOS transistors which generates the constant current representing the summed current.
摘要翻译：恒定电流产生电路具有产生具有正温度依赖性的第一电流并包括一对第一和第二双极晶体管的第一电流产生电路单元，由多个第一MOS晶体管组成的第一电流镜电路，第一MOS晶体管调节馈送到第一和第二双极晶体管的电流的电流密度比恒定并导出第一电流，以及设置在第一和第二双极晶体管与第一电流镜电路之间的第一电路，用于限制流经在施加到第一电流镜电路的电源的电压上的第一和第二双极晶体管，还提供产生具有负温度依赖性的第二电流的第二电流产生电路单元，并且包括第三双极晶体管和第二电阻通过其导出第二电流。此外，提供了一个求和电流产生电路单元，其将第一电流和第二电流相加，并产生一个恒定电流，基本上没有表示总和电流的温度依赖性。该汇总电流产生电路单元包括由多个第二MOS晶体管组成的第二电流镜电路，该第二MOS晶体管产生表示总和电流的恒定电流。

9. 发明授权

US5392250A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5392250A
公开(公告)日：1995-02-21
申请号：US5219
申请日：1993-01-15
申请人： Kinya Mitsumoto , Yoshikazu Iida , Hiroki Miyashita , Kazunori Onozawa
发明人： Kinya Mitsumoto , Yoshikazu Iida , Hiroki Miyashita , Kazunori Onozawa
IPC分类号： G11C11/417 , G11C11/409 , G11C11/419 , H01L21/8244 , H01L27/11 , G11C7/00 , G11C11/40
CPC分类号： G11C11/419 , H01L27/11
摘要： In a semiconductor memory device of the present invention, data read from a memory cell to a pair of complementary data lines or a pair of common data lines are fed directly to an output circuit not through any sense amplifier. As a result, the delay time of the sense amplifier itself is omitted from the address access time of the conventional semiconductor memory device using the sense amplifier, so that the semi-conductor memory device of the present invention can have its address access time made shorter than that of the conventional semiconductor memory device.
摘要翻译：在本发明的半导体存储器件中，从存储单元读取到一对互补数据线或一对公共数据线的数据直接通过任何读出放大器直接馈送到输出电路。结果，使用读出放大器的传统半导体存储器件的地址访问时间省略了读出放大器本身的延迟时间，使得本发明的半导体存储器件可以使其地址访问时间缩短比传统的半导体存储器件。

10. 发明授权

US07397880B2 Synchronization circuit and synchronization method 有权
标题翻译：同步电路和同步方法
公开(公告)号：US07397880B2
公开(公告)日：2008-07-08
申请号：US11156473
申请日：2005-06-21
申请人： Kinya Mitsumoto
发明人： Kinya Mitsumoto
IPC分类号： H04L25/40
CPC分类号： H03L7/0805 , H03L7/0812 , H03L7/087 , H03L7/0891 , H03L7/095 , H03L7/0995 , H03L7/191
摘要： In a synchronization circuit and a synchronization method, a first variable delay circuit generates a first pulse to be synchronized with a reference pulse, a second pulse which is leading in the phase to the first pulse, and a third pulse which is delayed in the phase from the first pulse. The reference pulse and the first pulse are compared by a first phase comparing circuit, and the reference pulse, second pulse and third pulse are compared by a second phase comparing circuit. A control voltage generating circuit forms a control voltage by giving priority to a comparison output of the second phase comparing circuit against a comparison output of the first phase comparing circuit. Delay time of the first variable delay circuit is controlled after the phases are matched by forming the control voltage with the comparison output of the first phase comparing circuit.
摘要翻译：在同步电路和同步方法中，第一可变延迟电路产生与参考脉冲同步的第一脉冲，在第一脉冲的相位中引出的第二脉冲和相位延迟的第三脉冲从第一脉冲。参考脉冲和第一脉冲通过第一相位比较电路进行比较，并且通过第二相位比较电路比较参考脉冲，第二脉冲和第三脉冲。控制电压产生电路通过优先考虑第二相位比较电路的比较输出与第一相位比较电路的比较输出而形成控制电压。通过用第一相位比较电路的比较输出形成控制电压，在相位匹配之后，控制第一可变延迟电路的延迟时间。

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