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1. 发明授权

US06560148B2 Semiconductor memory having mirroring function 失效
公开(公告)号：US06560148B2
公开(公告)日：2003-05-06
申请号：US09978006
申请日：2001-10-17
申请人： Kazuhiko Takami , Yoshito Nakaoka
发明人： Kazuhiko Takami , Yoshito Nakaoka
IPC分类号： G11C700
CPC分类号： G11C7/1006 , G11C2207/002
摘要： Data of a plurality of memory cells are read on a plurality of first data lines and combined by a combination/rewrite circuit and transmitted on a second data line and the combined data is written back to the first data line. In combining data, the combination/rewrite circuit performs an addition. Mirrored data can be improved in reliability and a function of correcting an error of the mirror data can also be implemented.

2. 发明授权

US5757711A Amplifier circuit and complementary amplifier circuit with limiting function for output lower limit 失效
标题翻译：放大器电路和互补放大器电路，具有输出下限的限制功能
公开(公告)号：US5757711A
公开(公告)日：1998-05-26
申请号：US681431
申请日：1996-07-23
申请人： Yoshito Nakaoka , Kiyohiro Furutani , Mikio Asakura
发明人： Yoshito Nakaoka , Kiyohiro Furutani , Mikio Asakura
IPC分类号： G11C11/409 , G11C7/06 , G11C7/10 , G11C7/02
CPC分类号： G11C7/06 , G11C7/1048
摘要： The potential of a data line is precharged to an H level by a P channel MOS transistor rendered conductive by a precharge signal. The potential of the data line is not driven by a differential amplifier circuit until the difference between the potential of the output of the differential amplifier circuit providing a corresponding signal and the potential (H level) of the data line become the level of a threshold voltage Vth(n) of an N channel MOS transistor. Therefore, erroneous data will not be provided to the data line even in the case of insufficient equalization of an I/O line pair or when there is an offset in the differential amplifier circuit.
摘要翻译：通过预充电信号导通的P沟道MOS晶体管将数据线的电位预充电至H电平。数据线的电位不是由差分放大器电路驱动，直到提供相应信号的差分放大器电路的输出的电位和数据线的电位（H电平）之间的差成为阈值电压的电平 Vth（n）为N沟道MOS晶体管。因此，即使在I / O线对均衡不足或差分放大电路中存在偏移的情况下，也不会向数据线提供错误的数据。

3. 发明授权

US5991210A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5991210A
公开(公告)日：1999-11-23
申请号：US138409
申请日：1998-08-24
申请人： Yoshito Nakaoka
发明人： Yoshito Nakaoka
IPC分类号： G11C11/409 , G11C7/10 , G11C11/407 , G11C11/4096 , G11C7/00
CPC分类号： G11C11/4096 , G11C7/1048
摘要： A semiconductor integrated circuit having a standard pair of complementary data lines subjected to ternary control, through which data complementary to each other are transmitted when valid data are transmitted, single data lines subjected to binary control, through which data of the same system as that of the pair of complementary data lines are transmitted and a circuit for detecting valid data in a standard intermediate latch circuit which detects an event that the data transmitted through the standard pair of complementary data lines are changed to data complementary to each other, wherein the circuit for detecting valid data confirms arrival of the valid data and controls data corresponding to the data transmitted through the single data lines, to thereby reduce the number of pairs of data lines for narrowing an wiring area of the data lines and reducing a chip size while maintaining a high speed operation.
摘要翻译：具有进行三进制控制的标准对互补数据线的半导体集成电路，当发送有效数据时，互相互补的数据被发送，经受二进制控制的单个数据线，与之相同的系统的数据与发送一对互补数据线，以及用于检测标准中间锁存电路中的有效数据的电路，该标准中间锁存电路检测通过标准的互补数据线对发送的数据被改变为彼此互补的数据的事件，其中，检测有效数据确认有效数据的到达并且控制与通过单个数据线传输的数据相对应的数据，从而减少用于使数据线的布线区域变窄的数据线对数，并且在保持数据线的同时减小芯片尺寸高速运行。

4. 发明授权

US5583460A Output driver circuit for restraining generation of noise and semiconductor memory device utilizing such circuit 失效
标题翻译：用于抑制噪声产生的输出驱动电路和利用这种电路的半导体存储器件
公开(公告)号：US5583460A
公开(公告)日：1996-12-10
申请号：US331240
申请日：1994-10-28
申请人： Yoshitsugu Dohi , Toru Shiomi , Yoshito Nakaoka
发明人： Yoshitsugu Dohi , Toru Shiomi , Yoshito Nakaoka
IPC分类号： G11C11/417 , H03K4/00 , H03K17/16 , H03K17/687 , H03K19/003 , H03K17/30
CPC分类号： H03K4/00 , H03K17/164
摘要： An improved output driver circuit for a semiconductor integrated circuit device, wherein a stepped control voltage generation circuit is connected to the gate of a driving transistor for driving an output terminal DQ. The stepped control voltage generation circuit responds to an applied input data signal to provide a stepped control voltage changing in a stepped form including a plurality of steps to the gate of the driving transistor. The driving transistor therefore changes its state on a step by step basis from a cut off state to a conduction state. Thus, sharp change in output current flowing through the output terminal can be prevented, and noise caused by a parasitic inductance can be avoided, thus preventing an erroneous operation in the device.
摘要翻译：一种用于半导体集成电路器件的改进的输出驱动器电路，其中阶梯式控制电压产生电路连接到用于驱动输出端子DQ的驱动晶体管的栅极。阶梯式控制电压产生电路响应于所施加的输入数据信号，以提供以逐步形式改变的阶梯式控制电压，包括多个步骤到驱动晶体管的栅极。因此，驱动晶体管因此从断开状态到导通状态一步一步地改变其状态。因此，可以防止流过输出端子的输出电流的急剧变化，并且可以避免由寄生电感引起的噪声，从而防止装置中的错误操作。

5. 发明授权

US06349064B1 Semiconductor memory device capable of independent selection of normal and redundant memory cells after programming of redundant address 失效
标题翻译：半导体存储器件能够在编程冗余地址后独立选择正常和冗余存储单元
公开(公告)号：US06349064B1
公开(公告)日：2002-02-19
申请号：US09760642
申请日：2001-01-17
申请人： Yoshito Nakaoka
发明人： Yoshito Nakaoka
IPC分类号： G11C700
CPC分类号： G11C29/785 , G11C29/24 , G11C29/838
摘要： A redundancy determining unit pre-stores a defective memory cell address in a normal memory cell array, and selects a redundant memory cell instead of a normal memory cell in a normal operational mode. The redundancy determining unit selects a designated redundant memory cell row in response to an address signal when a test mode signal and a redundancy identification address signal are activated. If the test mode signal is activated whereas the redundancy identification address signal is inactivated, a replacement operation for the normal memory cell and the redundant memory cell is stopped.
摘要翻译：冗余确定单元将正常存储单元阵列中的有缺陷的存储单元地址预存储，并且在正常操作模式中选择代替正常存储单元的冗余存储单元。当激活测试模式信号和冗余识别地址信号时，冗余确定单元响应于地址信号选择指定的冗余存储单元行。如果测试模式信号被激活而冗余识别地址信号被去激活，则停止对正常存储器单元和冗余存储单元的替换操作。

6. 发明授权

US06335902B1 Semiconductor memory device provided with generating means for internal clock signal for special mode 失效
标题翻译：具有用于特殊模式的内部时钟信号的发生装置的半导体存储器件
公开(公告)号：US06335902B1
公开(公告)日：2002-01-01
申请号：US09618751
申请日：2000-07-18
申请人： Yoshito Nakaoka
发明人： Yoshito Nakaoka
IPC分类号： G11C800
CPC分类号： G11C7/109 , G11C7/1045 , G11C7/1078 , G11C7/222 , G11C7/225 , G11C8/18
摘要： A semiconductor memory device is provided for reducing or preventing any switching to a special mode from a normal mode operation due to noise on an external clock without affecting any access time of the semiconductor memory device. In the semiconductor memory device, input buffer amplifiers converts a plurality of external clock signals into a plurality of internal clock signals each having an internal signal level, respectively, and then, a control clock signal generating circuit generates a control clock signal for controlling an operation of the semiconductor memory device in accordance with the plurality of internal clock signals. At least one of special mode input buffer amplifiers and noise filters has a time response characteristic gently changing according to a change in an input signal, and generates an internal clock signal for a different special mode from a normal mode associated with either one of reading and writing of data from and in the semiconductor memory device in accordance with at least one of the plurality of external clock signals.
摘要翻译：提供一种半导体存储器件，用于减少或防止由于外部时钟上的噪声而从正常模式操作切换到特殊模式，而不影响半导体存储器件的任何访问时间。在半导体存储器件中，输入缓冲放大器将多个外部时钟信号分别转换为分别具有内部信号电平的多个内部时钟信号，然后控制时钟信号发生电路产生用于控制操作的控制时钟信号根据多个内部时钟信号的半导体存储器件。特殊模式输入缓冲放大器和噪声滤波器中的至少一个具有根据输入信号的变化而轻微变化的时间响应特性，并且产生用于不同特殊模式的内部时钟信号，该正常模式与读取和根据多个外部时钟信号中的至少一个从半导体存储器件中写出数据。

7. 发明授权

US5793686A Semiconductor memory device having data input/output circuit of small occupied area capable of high-speed data input/output 失效
公开(公告)号：US5793686A
公开(公告)日：1998-08-11
申请号：US755930
申请日：1996-11-25
申请人： Kiyohiro Furutani , Tsukasa Ooishi , Mikio Asakura , Hideto Hidaka , Kei Hamade , Yoshito Nakaoka
发明人： Kiyohiro Furutani , Tsukasa Ooishi , Mikio Asakura , Hideto Hidaka , Kei Hamade , Yoshito Nakaoka
IPC分类号： G11C11/41 , G11C7/10 , G11C11/401 , G11C29/00 , G11C29/14 , G11C29/34 , G11C29/38 , G11C7/00
CPC分类号： G11C29/38 , G11C29/34 , G11C7/1051 , G11C7/1078
摘要： Read drivers which are provided in correspondence to simultaneously selected plural bits of memory cells are wired-OR connected to internal read data buses which in turn are provided in correspondence to a plurality of memory cell arrays respectively. A test mode circuit is provided for the internal read data buses for detecting coincidence/incoincidence of logics of signal potentials on these internal read data bus lines. In a test operation, all read drivers are activated to read selected memory cell data on the corresponding internal read data bus lines.

8. 发明授权

US5408140A Substrate potential generating circuit generating substrate potential of lower level and semiconductor device including the same 失效
标题翻译：产生下层的衬底电位的衬底电位产生电路和包括其的半导体器件
公开(公告)号：US5408140A
公开(公告)日：1995-04-18
申请号：US139670
申请日：1993-10-22
申请人： Shinji Kawai , Masaki Tsukude , Yoshito Nakaoka
发明人： Shinji Kawai , Masaki Tsukude , Yoshito Nakaoka
IPC分类号： G11C11/413 , G05F3/20 , G11C5/14 , G11C11/408 , H03K19/094 , H03K3/01
CPC分类号： G11C5/146 , G05F3/205
摘要： A substrate potential generating circuit can generate a lower substrate potential. The substrate potential generating circuit includes a clock signal generating circuit and first and second charge pump circuits. The first charge pump circuit including a p-channel MOS transistor having its source electrode connected to the semiconductor substrate applies a first negative potential to the drain electrode by capacitive coupling of a capacitor. The second charge pump circuit including first and second sub-charge pump circuit applies a third negative potential to the gate electrode when the first negative potential is applied to the drain electrode, and thereafter provides a second potential by lowering the third potential. As a result, the p-channel MOS transistor is turned on until a substrate potential is brought into a potential equal to the first potential applied to the drain electrode, lowering the substrate potential to the first potential.
摘要翻译：衬底电位产生电路可以产生较低的衬底电位。衬底电位产生电路包括时钟信号发生电路和第一和第二电荷泵电路。包括其源电极连接到半导体衬底的p沟道MOS晶体管的第一电荷泵电路通过电容器的电容耦合向漏电极施加第一负电位。包括第一和第二副电荷泵电路的第二电荷泵电路当第一负电位施加到漏电极时向栅电极施加第三负电位，然后通过降低第三电位而提供第二电位。结果，p沟道MOS晶体管导通，直到衬底电位变成等于施加到漏电极的第一电位的电位，将衬底电位降低到第一电位。

9. 发明授权

US06785143B2 Semiconductor memory module 失效
公开(公告)号：US06785143B2
公开(公告)日：2004-08-31
申请号：US10337344
申请日：2003-01-07
申请人： Yoshito Nakaoka
发明人： Yoshito Nakaoka
IPC分类号： H05K700
CPC分类号： H01L24/85 , G11C5/06 , G11C29/70 , H01L23/50 , H01L24/06 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/02166 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/48091 , H01L2224/4813 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/181 , H01L2224/78 , H01L2224/45099 , H01L2924/00
摘要： A bare chip includes a first semiconductor storage part and a second semiconductor storage part, formed in the stage of a wafer serving as a semiconductor material, capable of storing data independently of each other, and an electric wire serving as a semiconductor storage part employment/nonemployment selection circuit setting each of the first semiconductor storage part and the second semiconductor storage part in either a mode capable of inputting/outputting data or a mode incapable of inputting/outputting the data. Thus obtained is a semiconductor memory module formed by a plurality of bare chips integrally coated with molding resin, having a function of replacing a bare chip detected as defective with a spare chip.

10. 发明授权

US06504776B1 Semiconductor memory device having sense amplifier 失效
标题翻译：具有读出放大器的半导体存储器件
公开(公告)号：US06504776B1
公开(公告)日：2003-01-07
申请号：US10175905
申请日：2002-06-21
申请人： Yoshito Nakaoka
发明人： Yoshito Nakaoka
IPC分类号： G11C700
CPC分类号： G11C7/18 , G11C11/4097
摘要： A sense amplifier is connected to a pair of folded bit lines via selection gates. At the time of reading data in a memory cell connected to the bit line, the pair of folded bit lines enter a floating state. At this time, the selection gate is turned off to disconnect the bit line from a sense node. After that, a potential is supplied to the bit line from an equalizer. Consequently, a semiconductor memory device of the invention can suppress deterioration in charge holding capability of a memory cell and prevent erroneous operation.
摘要翻译：读出放大器通过选择门连接到一对折叠位线。在连接到位线的存储单元读取数据时，该对折叠位线进入浮置状态。此时，选择门被关闭以将位线与感测节点断开连接。之后，从均衡器向位线提供电位。因此，本发明的半导体存储器件能够抑制存储单元的电荷保持能力的劣化，防止误操作。

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