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1. 发明授权

US07774397B2 FFT/IFFT processor 有权
标题翻译： FFT / IFFT处理器
公开(公告)号：US07774397B2
公开(公告)日：2010-08-10
申请号：US11003924
申请日：2004-12-03
申请人： Kaushik Saha , Srijib Narayan Maiti , Marco Cornero
发明人： Kaushik Saha , Srijib Narayan Maiti , Marco Cornero
IPC分类号： G06F17/14
CPC分类号： G06F17/142
摘要： An FFT/IFFT processor having computation logic capable of processing butterfly operations, and storage for storing the operands of butterfly operations, including a mechanism for storing the operands of multiple consecutive butterfly operations in contiguous storage locations and wherein the computation logic is capable of simultaneously accessing and processing said multiple butterfly operations.
摘要翻译：具有能够处理蝶形运算的计算逻辑的FFT / IFFT处理器和用于存储蝶形运算操作数的存储器，包括用于在连续的存储位置存储多个连续的蝶形运算的操作数的机构，并且其中计算逻辑能够同时存取并处理所述多个蝴蝶操作。

2. 发明授权

US07983342B2 Macro-block level parallel video decoder 有权
标题翻译：宏块级并行视频解码器
公开(公告)号：US07983342B2
公开(公告)日：2011-07-19
申请号：US11191613
申请日：2005-07-28
申请人： Kaushik Saha , Abhik Sarkar , Srijib Narayan Maiti
发明人： Kaushik Saha , Abhik Sarkar , Srijib Narayan Maiti
IPC分类号： H04N7/12 , H04N11/02 , H04N11/04 , H04B1/66
CPC分类号： H04N19/436 , H04N19/433 , H04N19/44 , H04N19/51 , H04N19/61
摘要： A macro-block level parallel video decoder for a parallel processing environment is provided. The video decoder includes a Variable Length Decoding (VLD) block for decoding the encoded Discrete Cosine Transform (DCT) coefficients, a master node that receives the decoded DCT coefficients, and multiple slave nodes/processors for parallel implementation of Inverse Discrete Cosine Transform (IDCT) and motion compensation at the macro-block level. Also provided is a method for macro-block level video decoding in a parallel processing system.
摘要翻译：提供了用于并行处理环境的宏块级并行视频解码器。视频解码器包括用于对编码的离散余弦变换（DCT）系数进行解码的可变长度解码（VLD）块，接收解码的DCT系数的主节点和用于并行执行逆离散余弦变换（IDCT）的多个从节点/处理器）和宏块级的运动补偿。还提供了一种用于并行处理系统中的宏块级视频解码的方法。

3. 发明申请

US20050138098A1 FFT/IFFT processor 有权
标题翻译： FFT / IFFT处理器
公开(公告)号：US20050138098A1
公开(公告)日：2005-06-23
申请号：US11003924
申请日：2004-12-03
申请人： Kaushik Saha , Srijib Maiti , Marco Cornero
发明人： Kaushik Saha , Srijib Maiti , Marco Cornero
IPC分类号： G06F17/14 , G06F15/00
CPC分类号： G06F17/142
摘要： An FFT/IFFT processor having computation logic capable of processing butterfly operations, and storage for storing the operands of butterfly operations, including a mechanism for storing the operands of multiple consecutive butterfly operations in contiguous storage locations and wherein the computation logic is capable of simultaneously accessing and processing said multiple butterfly operations.
摘要翻译：具有能够处理蝶形运算的计算逻辑的FFT / IFFT处理器和用于存储蝶形运算操作数的存储器，包括用于在连续的存储位置存储多个连续的蝶形运算的操作数的机构，并且其中计算逻辑能够同时存取并处理所述多个蝴蝶操作。

4. 发明授权

US08520958B2 Parallelization of variable length decoding 有权
公开(公告)号：US08520958B2
公开(公告)日：2013-08-27
申请号：US12702497
申请日：2010-02-09
申请人： Surinder Pal Singh , Aneesh Bhasin , Kaushik Saha
发明人： Surinder Pal Singh , Aneesh Bhasin , Kaushik Saha
IPC分类号： G06K9/36
CPC分类号： G06T9/005 , H03M7/40 , H04N19/436 , H04N19/44 , H04N19/46 , H04N19/91
摘要： Parallelization of decoding of a data stream encoded with a variable length code includes determining one or more markers, each of which indicates a position within the encoded data stream. The determined markers are included into the encoded data stream together with the encoded data. At the decoder side, the markers are parsed from the encoded data stream and based on the extracted markers. The encoded data is separated into partitions, which are decoded separately and in parallel.

5. 发明授权

US08456197B2 Differential data sensing 有权
标题翻译：差分数据传感
公开(公告)号：US08456197B2
公开(公告)日：2013-06-04
申请号：US13118858
申请日：2011-05-31
申请人： Prashant Dubey , Navneet Gupta , Shailesh Kumar Pathak , Kaushik Saha , Gagandeep Singh Sachdev
发明人： Prashant Dubey , Navneet Gupta , Shailesh Kumar Pathak , Kaushik Saha , Gagandeep Singh Sachdev
IPC分类号： G01R19/00 , G11C7/00 , H03F3/45
CPC分类号： G11C7/065 , H04L25/0274
摘要： A first sensing circuit has input terminals coupled to a true differential signal line and a complementary differential signal line. A second sensing circuit also has input terminals coupled to said true signal and said complementary signal. Each sensing circuit has a true signal sensing path and a complementary signal sensing path. The first sensing circuit has an imbalance that is biased towards the complementary signal sensing path, while the second sensing circuit has an imbalance that is biased towards the true signal sensing path. Outputs from the first and second sensing circuits are processed by a logic circuit producing an output signal that is indicative of whether there a sufficient differential signal for sensing has been developed between the true differential signal line and the complementary differential signal line.
摘要翻译：第一感测电路具有耦合到真实差分信号线和互补差分信号线的输入端。第二感测电路还具有耦合到所述真实信号和所述互补信号的输入端子。每个感测电路具有真实的信号感测路径和互补信号感测路径。第一感测电路具有偏置于互补信号感测路径的不平衡，而第二感测电路具有被偏置到真实信号感测路径的不平衡。来自第一和第二感测电路的输出由逻辑电路处理，该逻辑电路产生一个输出信号，该输出信号指示在真实差分信号线和互补差分信号线之间是否存在足够的用于感测的差分信号。

6. 发明授权

US07489742B2 System and method for clock recovery in digital video communication 有权
标题翻译：数字视频通信中时钟恢复的系统和方法
公开(公告)号：US07489742B2
公开(公告)日：2009-02-10
申请号：US11254069
申请日：2005-10-19
申请人： Kaushik Saha , Chiranjib Chakraborty , Subrata Chatterjee
发明人： Kaushik Saha , Chiranjib Chakraborty , Subrata Chatterjee
IPC分类号： H04L27/00
CPC分类号： H04N21/4305
摘要： A system for clock recovery in digital video communication includes a delay measurement block for generating PCR input signals and for continuously determining the time interval between successive PCR input signals. The system also includes a first storage device for generating a first PCR signal corresponding to the time interval between arrival of successive PCR input signals and a PCR inter-arrival time computation filtering device to determine the average time of arrival difference between successive PCR packets. The system further includes an error correction device for minimizing error in the average PCR difference between successive PCR packets, a controlled system clock generator coupled to the output of the error correction device to generate system clock, a second storage device for generating a first system clock output, and a controlled clock period difference computation element for computing the clock period difference between the first and second system clock outputs. The controlled clock period difference computation element is coupled at its output to the error correction device to form a feedback circuit to minimize error between the system clock output and successive PCR differences.
摘要翻译：一种用于数字视频通信中的时钟恢复的系统包括用于产生PCR输入信号并连续地确定连续PCR输入信号之间的时间间隔的延迟测量块。该系统还包括：第一存储装置，用于产生对应于连续PCR输入信号到达之间的时间间隔的第一PCR信号和PCR到达间时间计算滤波装置，以确定连续PCR分组之间的平均到达时间差。所述系统还包括用于使连续的PCR分组之间的平均PCR差异的误差最小化的纠错装置，耦合到纠错装置的输出以产生系统时钟的受控系统时钟发生器，用于生成第一系统时钟的第二存储装置输出和用于计算第一和第二系统时钟输出之间的时钟周期差的受控时钟周期差计算元件。受控时钟周期差计算元件在其输出端耦合到纠错装置以形成反馈电路，以最小化系统时钟输出和连续PCR差异之间的误差。

7. 发明授权

US08624623B2 Apparatus having error detection in sequential logic 有权
标题翻译：在顺序逻辑中具有错误检测的装置
公开(公告)号：US08624623B2
公开(公告)日：2014-01-07
申请号：US13340674
申请日：2011-12-30
申请人： Navneet Gupta , Prashant Dubey , Kaushik Saha , AtulKumar Kashyap
发明人： Navneet Gupta , Prashant Dubey , Kaushik Saha , AtulKumar Kashyap
IPC分类号： H03K19/003 , H03K19/173
CPC分类号： H03K3/356156 , H03K3/0375
摘要： According to an embodiment, an apparatus includes: a first node configured to receive a data input signal of a data latch; a second node configured to receive a data output signal of the data latch; process and hold circuitry configured to process a difference between a value of the data input signal received at the first node and a value of the data output signal received at the second node and hold respective values at the first and second nodes responsive to the difference; and comparison circuitry configured to compare the value held at the first node and a value of the data output signal of the data latch; wherein the process and hold circuitry is configured to be biased toward the signal received at one of the first node and the second node.
摘要翻译：根据实施例，一种装置包括：被配置为接收数据锁存器的数据输入信号的第一节点; 第二节点，被配置为接收数据锁存器的数据输出信号; 处理和保持电路，被配置为处理在第一节点处接收的数据输入信号的值与在第二节点处接收到的数据输出信号的值之间的差异，并响应于该差异保持第一和第二节点处的相应值; 以及比较电路，被配置为比较在第一节点处保持的值和数据锁存器的数据输出信号的值; 其中所述处理和保持电路被配置为朝向在所述第一节点和所述第二节点之一处接收的信号偏置。

8. 发明授权

US08587292B2 Power measurement circuit 有权
公开(公告)号：US08587292B2
公开(公告)日：2013-11-19
申请号：US12842256
申请日：2010-07-23
申请人： Surinder Pal Singh , Kaushik Saha
发明人： Surinder Pal Singh , Kaushik Saha
IPC分类号： G01R1/20
CPC分类号： H04L67/025 , G01R19/22 , G01R21/133 , H04L41/32
摘要： A system for power measurement in an electronic device includes a sensing unit, an analog-to-digital converter (ADC) and a controller. The sensing unit senses voltage across a power source and modulates a carrier signal based on the sensed voltage. The ADC converts a combination of the modulated carrier signal and audio signals received by the electronic device to generate a digitized combined signal and provides the digitized combined signal to the controller. The controller separates digitized modulated carrier signal and digitized audio signals. The digitized modulated carrier signal is demodulated to generate an output signal that provides a measure of the power consumed by the electronic device.

9. 发明授权

US07870177B2 Method and system for multi-processor FFT/IFFT with minimum inter-processor data communication 有权
标题翻译：用于多处理器FFT / IFFT的方法和系统，具有最少的处理器间数据通信
公开(公告)号：US07870177B2
公开(公告)日：2011-01-11
申请号：US10781336
申请日：2004-02-17
申请人： Kaushik Saha , Srijib Narayan
发明人： Kaushik Saha , Srijib Narayan
IPC分类号： G06F15/00
CPC分类号： G06F17/142
摘要： The embodiments of the present invention provide a scalable method for implementing FFT/IFFT computations in multiprocessor architectures that provides improved throughput by eliminating the need for inter-processor communication after the computation of the first “log2P” stages for an implementation using “P” processing elements, comprising computing each butterfly of the first “log2P” stages on either a single processor or each of the “P” processors simultaneously and distributing the computation of the butterflies in all the subsequent stages among the “P” processors such that each chain of cascaded butterflies consisting of those butterflies that have inputs and outputs connected together, are processed by the same processor. The embodiments of the invention also provide a system for obtaining scalable implementation of FFT/IFFT computations in multiprocessor architectures that provides improved throughput by eliminating the need for inter-processor communication after the computation of the first “log2P” stages for an implementation using “P” processing elements.
摘要翻译：本发明的实施例提供了一种用于在多处理器架构中实现FFT / IFFT计算的可扩展方法，其通过在使用“P”处理的实现的第一“log2P”阶段的计算之后消除对处理器间通信的需要来提供改进的吞吐量元素，包括同时在单个处理器或每个“P”处理器上计算第一“log2P”阶段的每个蝴蝶并在“P”个处理器中的所有后续阶段中分配蝴蝶的计算，使得每个链由具有连接在一起的输入和输出的蝴蝶组成的级联蝴蝶由相同的处理器处理。本发明的实施例还提供了一种用于在多处理器架构中获得FFT / IFFT计算的可伸缩实现的系统，其通过在使用“P”的实现的计算第一“log2P”阶段之后消除对处理器间通信的需要而提供改进的吞吐量 “处理要素

10. 发明申请

US20090265739A1 METHOD AND SYSTEM FOR CHANNEL SELECTION IN A DIGITAL BROADCAST RECEPTION TERMINAL 审中-公开
标题翻译：数字广播接收终端中频道选择的方法和系统
公开(公告)号：US20090265739A1
公开(公告)日：2009-10-22
申请号：US12105834
申请日：2008-04-18
申请人： Prabhjot Singh ARORA , Kaushik Saha
发明人： Prabhjot Singh ARORA , Kaushik Saha
IPC分类号： H04N5/445 , G06F13/00 , H04N7/173
CPC分类号： H04N7/163 , H04N5/44543 , H04N5/44591 , H04N21/4345 , H04N21/4384 , H04N21/4438 , H04N21/4755 , H04N21/482
摘要： The present invention discloses a system and method for channel selection in a digital broadcast reception terminal. The system tunes to different frequencies and generates visual clips corresponding to a plurality of channels in a frequency band. Visual clips of multiple channels are simultaneously displayed on a display screen which provides the user an easy way to select a desired program.
摘要翻译：本发明公开了一种在数字广播接收终端中进行频道选择的系统和方法。该系统调谐到不同的频率并产生与频带中的多个信道相对应的视频剪辑。多个频道的视频剪辑同时显示在显示屏幕上，为用户提供了一种选择所需节目的简单方法。

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