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1. 发明授权

US08446951B2 Dynamic image receiving apparatus, dynamic image receiving method and program 有权
标题翻译：动态图像接收装置，动态图像接收方法和程序
公开(公告)号：US08446951B2
公开(公告)日：2013-05-21
申请号：US12680491
申请日：2008-09-19
申请人： Katsunori Tanaka , Atsushi Hatabu , Yuzo Senda , Katsutoshi Seki , Tomoyoshi Kobori , Kosuke Nishihara , Soji Mori
发明人： Katsunori Tanaka , Atsushi Hatabu , Yuzo Senda , Katsutoshi Seki , Tomoyoshi Kobori , Kosuke Nishihara , Soji Mori
IPC分类号： H04N7/12
CPC分类号： H04N21/4307 , H04N19/44
摘要： To provide a dynamic image receiving apparatus which receives dynamic image streams coded with inter-frame prediction such as MPEG from a plurality of channels, and collects the dynamic image streams containing intra-frame coded pictures from each channel in a short time. The dynamic image receiving apparatus includes: a time information accumulative processing device which accumulates code receiving time of the intra-frame coded picture of the dynamic image stream, and periodicity time information containing one of or both of presentation time information and decoding time information contained in the dynamic image stream for each dynamic image stream of the plurality of channels; code receiving time predicting devices which predict the code receiving time of the intra-frame coded pictures based on the periodicity time information; and a channel selection control device which controls channel selection of the dynamic image stream to be received based on the predicted code receiving time information.
摘要翻译：提供一种动态图像接收装置，其接收从多个频道接收诸如MPEG之类的帧间预测编码的动态图像流，并且在短时间内收集每个信道中包含帧内编码图像的动态图像流。动态图像接收装置包括：时间信息累积处理装置，其累积动态图像流的帧内编码图像的代码接收时间，以及包含显示时间信息和解码时间信息中的一个或两个的周期性时间信息针对所述多个频道的每个动态图像流的所述动态图像流; 代码接收时间预测装置，其基于周期时间信息来预测帧内编码图像的代码接收时间; 以及频道选择控制装置，其基于预测的代码接收时间信息来控制要接收的动态图像流的频道选择。

2. 发明申请

US20100246673A1 DYNAMIC IMAGE RECEIVING APPARATUS, DYNAMIC IMAGE RECEIVING METHOD AND PROGRAM 有权
标题翻译：动态图像接收装置，动态图像接收方法和程序
公开(公告)号：US20100246673A1
公开(公告)日：2010-09-30
申请号：US12680491
申请日：2008-09-19
申请人： Katsunori Tanaka , Atsushi Hatabu , Yuzo Senda , Katsutoshi SEKI , Tomoyoshi Kobori , Kosuke Nishihara , Soji Mori
发明人： Katsunori Tanaka , Atsushi Hatabu , Yuzo Senda , Katsutoshi SEKI , Tomoyoshi Kobori , Kosuke Nishihara , Soji Mori
IPC分类号： H04N7/12
CPC分类号： H04N21/4307 , H04N19/44
摘要： To provide a dynamic image receiving apparatus which receives dynamic image streams coded with inter-frame prediction such as MPEG from a plurality of channels, and collects the dynamic image streams containing intra-frame coded pictures from each channel in a short time. The dynamic image receiving apparatus includes: a time information accumulative processing device which accumulates code receiving time of the intra-frame coded picture of the dynamic image stream, and periodicity time information containing one of or both of presentation time information and decoding time information contained in the dynamic image stream for each dynamic image stream of the plurality of channels; code receiving time predicting devices which predict the code receiving time of the intra-frame coded pictures based on the periodicity time information; and a channel selection control device which controls channel selection of the dynamic image stream to be received based on the predicted code receiving time information.
摘要翻译：提供一种动态图像接收装置，其接收从多个频道接收诸如MPEG之类的帧间预测编码的动态图像流，并且在短时间内收集每个信道中包含帧内编码图像的动态图像流。动态图像接收装置包括：时间信息累积处理装置，其累积动态图像流的帧内编码图像的代码接收时间，以及包含显示时间信息和解码时间信息中的一个或两个的周期性时间信息针对所述多个频道的每个动态图像流的所述动态图像流; 代码接收时间预测装置，其基于周期时间信息来预测帧内编码图像的代码接收时间; 以及频道选择控制装置，其基于预测的代码接收时间信息来控制要接收的动态图像流的频道选择。

3. 发明授权

US09424230B2 Converting a data placement between memory banks and an array processing section 有权
标题翻译：在存储体和阵列处理部分之间转换数据放置
公开(公告)号：US09424230B2
公开(公告)日：2016-08-23
申请号：US12594757
申请日：2008-02-22
申请人： Tomoyoshi Kobori , Katsutoshi Seki
发明人： Tomoyoshi Kobori , Katsutoshi Seki
IPC分类号： G06F15/173 , G06F15/80 , G06T1/20
CPC分类号： G06F15/8046 , G06F15/17381 , G06T1/20
摘要： In an array processing section, using data strings entered from input ports, a plurality of data processor elements execute predetermined operations while transferring data to each other, and output data strings of results of the operations from a plurality of output ports. A first data string converter converts data strings stored in a plurality of data storages of a data storage group into a placement suitable for the operations in the array processing section, and enters the converted data strings into the input ports of the array processing section. A second data string converter converts the data strings output from output ports of the array processing section into a placement to be stored in the plurality of data storages of the data storage group.
摘要翻译：在阵列处理部分中，使用从输入端口输入的数据串，多个数据处理器元件在彼此传送数据的同时执行预定的操作，并从多个输出端口输出操作结果的数据串。第一数据串转换器将存储在数据存储组的多个数据存储器中的数据串转换成适用于阵列处理部分中的操作的放置，并将转换的数据串输入到阵列处理部分的输入端口。第二数据串转换器将从阵列处理部分的输出端口输出的数据串转换为要存储在数据存储组的多个数据存储器中的放置。

4. 发明申请

US20100131738A1 ARRAY PROCESSOR TYPE DATA PROCESSING APPARATUS 有权
标题翻译：阵列处理器类型数据处理设备
公开(公告)号：US20100131738A1
公开(公告)日：2010-05-27
申请号：US12594757
申请日：2008-02-22
申请人： Tomoyoshi Kobori , Katsutoshi Seki
发明人： Tomoyoshi Kobori , Katsutoshi Seki
IPC分类号： G06F15/80 , G06F9/02
CPC分类号： G06F15/8046 , G06F15/17381 , G06T1/20
摘要： In an array processing section, using data strings entered from input ports, a plurality of data processor elements execute predetermined operations while transferring data to each other, and output data strings of results of the operations from a plurality of output ports. A first data string converter converts data strings stored in a plurality of data storages of a data storage group into a placement suitable for the operations in the array processing section, and enters the converted data strings into the input ports of the array processing section. A second data string converter converts the data strings output from output ports of the array processing section into a placement to be stored in the plurality of data storages of the data storage group.
摘要翻译：在阵列处理部分中，使用从输入端口输入的数据串，多个数据处理器元件在彼此传送数据的同时执行预定的操作，并从多个输出端口输出操作结果的数据串。第一数据串转换器将存储在数据存储组的多个数据存储器中的数据串转换成适用于阵列处理部分中的操作的放置，并将转换的数据串输入到阵列处理部分的输入端口。第二数据串转换器将从阵列处理部分的输出端口输出的数据串转换为要存储在数据存储组的多个数据存储器中的放置。

5. 发明授权

US09250996B2 Multicore type error correction processing system and error correction processing apparatus 有权
标题翻译：多核型纠错处理系统和纠错处理装置
公开(公告)号：US09250996B2
公开(公告)日：2016-02-02
申请号：US13877650
申请日：2011-10-04
申请人： Tomoyoshi Kobori , Steffen Kunze , Emil Matus , Gerhard Fettweis
发明人： Tomoyoshi Kobori , Steffen Kunze , Emil Matus , Gerhard Fettweis
IPC分类号： G06F11/10 , H03M13/11 , H03M13/00 , H03M13/29 , H03M13/27 , G06F5/01
CPC分类号： G06F11/1044 , G06F5/015 , H03M13/1102 , H03M13/1105 , H03M13/114 , H03M13/1145 , H03M13/1162 , H03M13/1171 , H03M13/2775 , H03M13/296 , H03M13/2978 , H03M13/6508 , H03M13/6513 , H03M13/6566 , H03M13/6569 , H03M13/6577
摘要： In a multicore type error correction processing system which can simultaneously cope with a plurality of error correction methods and a plurality of code lengths, an interconnect part 11 has a barrel shifter which extends across a plurality of error correction processing parts 12a-12c. An error correction process can be selectively performed by collectively using a group of the plurality of the error correction processing parts 12a-12c or by individually using each of individual error correction processing parts 12a-12c in response to interconnection configuration information. With this structure, the plurality of the error correction processing parts 12a-12c are collectively used if computation resources are insufficient and an idling error correction processing part is assigned to another error correction process if computation resources are excessive.
摘要翻译：在能够同时处理多个纠错方法和多个码长的多核型纠错处理系统中，互连部分11具有延伸跨越多个纠错处理部分12a-12c的桶形移位器。可以通过集体地使用多个纠错处理部分12a-12c的组或者通过单独地使用每个单独的纠错处理部分12a-12c来响应于互连配置信息来选择性地执行纠错处理。利用这种结构，如果计算资源不足，则多个纠错处理部分12a-12c被共同使用，并且如果计算资源过多，则将空闲纠错处理部分分配给另一纠错处理部分。

6. 发明申请

US20140040700A1 MULTICORE TYPE ERROR CORRECTION PROCESSING SYSTEM AND ERROR CORRECTION PROCESSING APPARATUS 有权
标题翻译：多种类型错误校正处理系统和错误校正处理设备
公开(公告)号：US20140040700A1
公开(公告)日：2014-02-06
申请号：US13877650
申请日：2011-10-04
申请人： Tomoyoshi Kobori , Steffen Kunze , Emil Matus , Gerhard Fettweis
发明人： Tomoyoshi Kobori , Steffen Kunze , Emil Matus , Gerhard Fettweis
IPC分类号： G06F11/10
CPC分类号： G06F11/1044 , G06F5/015 , H03M13/1102 , H03M13/1105 , H03M13/114 , H03M13/1145 , H03M13/1162 , H03M13/1171 , H03M13/2775 , H03M13/296 , H03M13/2978 , H03M13/6508 , H03M13/6513 , H03M13/6566 , H03M13/6569 , H03M13/6577
摘要： In a multicore type error correction processing system which can simultaneously cope with a plurality of error correction methods and a plurality of code lengths, an interconnect part 11 has a barrel shifter which extends across a plurality of error correction processing parts 12a-12c. An error correction process can be selectively performed by collectively using a group of the plurality of the error correction processing parts 12a-12c or by individually using each of individual error correction processing parts 12a-12c in response to interconnection configuration information. With this structure, the plurality of the error correction processing parts 12a-12c are collectively used if computation resources are insufficient and an idling error correction processing part is assigned to another error correction process if computation resources are excessive.
摘要翻译：在能够同时处理多个纠错方法和多个码长的多核型纠错处理系统中，互连部分11具有延伸跨越多个纠错处理部分12a-12c的桶形移位器。可以通过集体地使用多个纠错处理部分12a-12c的组或者通过单独地使用每个单独的纠错处理部分12a-12c来响应于互连配置信息来选择性地执行纠错处理。利用这种结构，如果计算资源不足，则多个纠错处理部分12a-12c被共同使用，并且如果计算资源过多，则将空闲纠错处理部分分配给另一纠错处理部分。

7. 发明授权

US08452943B2 Apparatus and method for address generation for array processor and array processor 有权
标题翻译：阵列处理器和阵列处理器的地址生成装置和方法
公开(公告)号：US08452943B2
公开(公告)日：2013-05-28
申请号：US12746468
申请日：2008-12-05
申请人： Tomoyoshi Kobori
发明人： Tomoyoshi Kobori
IPC分类号： G06F12/00
CPC分类号： G06F15/8046
摘要： In address generation processors, the start and the end of the processing for address generation need to be controlled in addition to controlling the processing for base address generation. A timing control unit manages control for address conversion on a clock cycle basis. The difference between the processing speed in the address generation processors and the processing speed in the address conversion circuit is absorbed by buffers.
摘要翻译：在地址生成处理器中，除了控制基地址生成的处理之外，还需要控制地址生成处理的开始和结束。定时控制单元基于时钟周期管理地址转换的控制。地址生成处理器中的处理速度与地址转换电路中的处理速度之间的差异被缓冲器吸收。

8. 发明申请

US20100306496A1 APPARATUS AND METHOD FOR ADDRESS GENERATION FOR ARRAY PROCESSOR AND ARRAY PROCESSOR 有权
标题翻译：用于阵列处理器和阵列处理器的地址生成装置和方法
公开(公告)号：US20100306496A1
公开(公告)日：2010-12-02
申请号：US12746468
申请日：2008-12-05
申请人： Tomoyoshi Kobori
发明人： Tomoyoshi Kobori
IPC分类号： G06F12/00
CPC分类号： G06F15/8046
摘要： In address generation processors, the start and the end of the processing for address generation need to be controlled in addition to controlling the processing for base address generation. A timing control unit manages control for address conversion on a clock cycle basis. The difference between the processing speed in the address generation processors and the processing speed in the address conversion circuit is absorbed by buffers.
摘要翻译：在地址生成处理器中，除了控制基地址生成的处理之外，还需要控制地址生成处理的开始和结束。定时控制单元基于时钟周期管理地址转换的控制。地址生成处理器中的处理速度与地址转换电路中的处理速度之间的差异被缓冲器吸收。

9. 发明授权

US08694975B2 Programming system in multi-core environment, and method and program of the same 有权
标题翻译：编程系统在多核环境下，以及方法与程序相同
公开(公告)号：US08694975B2
公开(公告)日：2014-04-08
申请号：US13062761
申请日：2009-07-23
申请人： Tomoyoshi Kobori
发明人： Tomoyoshi Kobori
IPC分类号： G06F9/45
CPC分类号： G06F8/45 , G06F8/54
摘要： A first compiler generates one or more object codes from a program code for a first processor included in an arithmetic processing system to which a plurality of processors are mutually connected. A first linker links the generated one or more object codes to generate an execution file for the first processor. A parameter information generation unit generates, based on the information acquired from the first linker, parameter information used in a second processor included in the arithmetic processing system. A second compiler refers to a program code and the parameter information for the second processor to generate one or more object codes. A second linker links the generated one or more object codes to generate an execution file for the second processor.
摘要翻译：第一编译器从包括在多个处理器相互连接的算术处理系统中的第一处理器的程序代码生成一个或多个目标代码。第一链接器链接所生成的一个或多个目标代码以生成用于第一处理器的执行文件。参数信息生成单元基于从第一链接器获取的信息，生成包含在算术处理系统中的第二处理器中使用的参数信息。第二编译器参考程序代码和第二处理器的参数信息来生成一个或多个目标代码。第二链接器链接所生成的一个或多个目标代码以生成用于第二处理器的执行文件。

10. 发明申请

US20110167417A1 PROGRAMMING SYSTEM IN MULTI-CORE, AND METHOD AND PROGRAM OF THE SAME 有权
标题翻译：多核编程系统及其方法与程序
公开(公告)号：US20110167417A1
公开(公告)日：2011-07-07
申请号：US13062761
申请日：2009-07-23
申请人： Tomoyoshi Kobori
发明人： Tomoyoshi Kobori
IPC分类号： G06F9/45
CPC分类号： G06F8/45 , G06F8/54
摘要： A first compiler generates one or more object codes from a program code for a first processor included in an arithmetic processing system to which a plurality of processors are mutually connected. A first linker links the generated one or more object codes to generate an execution file for the first processor. A parameter information generation unit generates, based on the information acquired from the first linker, parameter information used in a second processor included in the arithmetic processing system. A second compiler refers to a program code and the parameter information for the second processor to generate one or more object codes. A second linker links the generated one or more object codes to generate an execution file for the second processor.
摘要翻译：第一编译器从包括在多个处理器相互连接的算术处理系统中的第一处理器的程序代码生成一个或多个目标代码。第一链接器链接所生成的一个或多个目标代码以生成用于第一处理器的执行文件。参数信息生成单元基于从第一链接器获取的信息，生成包含在算术处理系统中的第二处理器中使用的参数信息。第二编译器参考程序代码和第二处理器的参数信息来生成一个或多个目标代码。第二链接器链接所生成的一个或多个目标代码以生成用于第二处理器的执行文件。

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