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1. 发明授权

US06383906B1 Method of forming junction-leakage free metal salicide in a semiconductor wafer with ultra-low silicon consumption 有权
标题翻译：在具有超低硅消耗的半导体晶片中形成结漏电的金属硅化物的方法
公开(公告)号：US06383906B1
公开(公告)日：2002-05-07
申请号：US09641436
申请日：2000-08-18
申请人： Karsten Wieczorek , Nicholas Kepler , Paul R. Besser , Larry Y. Wang
发明人： Karsten Wieczorek , Nicholas Kepler , Paul R. Besser , Larry Y. Wang
IPC分类号： H01L214763
CPC分类号： H01L29/6653 , H01L21/28518 , H01L29/665 , H01L29/6656 , H01L29/6659
摘要： A method for forming ultra shallow junctions in a semiconductor wafer uses disposable spacers and a silicon cap layer to achieve ultra-low low silicon consumption during a salicide formation process. A refractory metal layer, such as a cobalt layer, is deposited over the gate and source/drain junctions of a semiconductor device. Silicon nitride disposable spacers are formed over the metal layer in the region of the sidewall spacers previously formed on the sidewalls of the gate. A silicon cap layer is deposited over the metal layer and the disposable spacers. Rapid thermal annealing is performed to form the high-ohmic phase of the salicide, with the disposable spacers preventing interaction and between the cobalt and the silicon in the area between the gate and the source/drain junctions along the sidewall spacers. The silicon cap layer provides a source of silicon for consumption during the first phase of salicide formation, reducing the amount of silicon of the source/drain junctions that is consumed.
摘要翻译：在半导体晶片中形成超浅结的方法使用一次性间隔物和硅帽层，以在自对准硅化物形成过程中实现超低的低硅消耗。难熔金属层，例如钴层，沉积在半导体器件的栅极和源极/漏极结上。氮化硅一次性间隔物形成在预先形成在栅极的侧壁上的侧壁间隔区域中的金属层的上方。在金属层和一次性间隔物上沉积硅覆盖层。进行快速热退火以形成硅化物的高欧姆相，其中一次性间隔物防止了沿着侧壁间隔物的栅极和源极/漏极结之间的区域中的钴和硅之间的相互作用。硅封层在硅化物形成的第一阶段期间提供硅消耗源，从而减少消耗的源极/漏极结的硅量。

2. 发明授权

US06323516B1 Flash memory device and fabrication method having a high coupling ratio 有权
标题翻译：具有高耦合比的闪存器件和制造方法
公开(公告)号：US06323516B1
公开(公告)日：2001-11-27
申请号：US09390052
申请日：1999-09-03
申请人： Larry Y. Wang , Steven K. Park
发明人： Larry Y. Wang , Steven K. Park
IPC分类号： H01L29788
CPC分类号： H01L29/42324
摘要： Embodiments of the invention comprise a new device and technique to realize an improved coupling ratio integrated circuit device. This improvement is achieved by increasing an overlap portion between the first and second polysilicon layers, so as to increase the effective coupling ratio between the layers. In the embodiments of the present invention, a relatively tall or large portion of oxide is formed over at least a portion of each of a plurality of shallow trench isolation regions. This oxide is then utilized to provide a larger first polysilicon layer surface area, but without substantially increasing the tunnel oxide layer surface area. Then, a dielectric interlayer is formed upon the surface of the first polysilicon layer, and next, a second polysilicon layer is formed upon the dielectric interlayer. This increased overlap portion thus allows for an increased coupling ratio. Further, the coupling ratio may be tailored by adjusting either or both of the first and second polysilicon layer surface areas without requiring a substantial change in the tunnel oxide layer surface area.
摘要翻译：本发明的实施例包括实现改进的耦合比集成电路器件的新器件和技术。这种改进通过增加第一和第二多晶硅层之间的重叠部分来实现，以便增加层之间的有效耦合比。在本发明的实施例中，在多个浅沟槽隔离区域的每一个的至少一部分上形成相当高或较大部分的氧化物。然后利用该氧化物提供较大的第一多晶硅层表面积，但基本不增加隧道氧化物层的表面积。然后，在第一多晶硅层的表面上形成电介质中间层，接着在电介质中间层上形成第二多晶硅层。这种增加的重叠部分因此允许增加耦合比。此外，可以通过调整第一和第二多晶硅层表面区域中的一个或两个而不需要隧道氧化物层表面积的实质变化来调整耦合比。

3. 发明授权

US5485097A Method of electrically measuring a thin oxide thickness by tunnel voltage 失效
标题翻译：通过隧道电压电测量薄氧化物厚度的方法
公开(公告)号：US5485097A
公开(公告)日：1996-01-16
申请号：US287332
申请日：1994-08-08
申请人： Larry Y. Wang
发明人： Larry Y. Wang
IPC分类号： G01B7/06 , G01R31/28 , H01L21/66 , G01R27/00
CPC分类号： G01R31/2831 , B82Y15/00 , G01B7/06 , H01L22/12
摘要： A method of electrically measuring thin oxide thickness by tunnel voltage in a device under test includes the steps of applying a predetermined value of current density through the device under test, measuring voltage developed across the device under test, and calculating the oxide electrical thickness through a predetermined calibration curve. This method is suitable for incorporation into an automatic tester for fast and high volume data collection. This technique also has higher resolution and accuracy than measurements obtained optically.
摘要翻译：在被测器件中通过隧道电压电测量薄氧化物厚度的方法包括以下步骤：通过被测器件施加预定值的电流密度，测量在被测器件上产生的电压，以及通过以下步骤计算氧化物电学厚度预定校准曲线。该方法适用于自动测试仪的快速和高容量数据采集。该技术还具有比通过光学获得的测量更高的分辨率和精度。

4. 发明授权

US08748232B2 Semiconductor device having a through-substrate via 有权
标题翻译：具有贯通基板通孔的半导体装置
公开(公告)号：US08748232B2
公开(公告)日：2014-06-10
申请号：US13342420
申请日：2012-01-03
申请人： Arkadii V. Samoilov , Tyler Parent , Larry Y. Wang
发明人： Arkadii V. Samoilov , Tyler Parent , Larry Y. Wang
IPC分类号： H01L21/00
CPC分类号： H01L24/81 , H01L21/568 , H01L21/6835 , H01L21/76898 , H01L23/3128 , H01L23/3135 , H01L23/481 , H01L23/49811 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2221/6834 , H01L2221/6835 , H01L2221/68381 , H01L2224/02313 , H01L2224/02331 , H01L2224/02381 , H01L2224/0239 , H01L2224/024 , H01L2224/03828 , H01L2224/0401 , H01L2224/05025 , H01L2224/0508 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/11002 , H01L2224/11334 , H01L2224/11849 , H01L2224/13022 , H01L2224/13024 , H01L2224/13025 , H01L2224/13111 , H01L2224/13147 , H01L2224/14181 , H01L2224/16145 , H01L2224/16147 , H01L2224/16225 , H01L2224/16227 , H01L2224/81 , H01L2224/81191 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2924/181 , H01L2924/01047 , H01L2924/01029 , H01L2924/01082 , H01L2924/00014 , H01L2924/01013 , H01L2224/11 , H01L2224/02 , H01L2224/03 , H01L2924/00
摘要： Semiconductor devices are described that include a via that extends only partially through the substrate. Through-substrate vias (TSV) furnish electrical interconnectivity to electronic components formed in the substrates. In implementations, the semiconductor devices are fabricated by first bonding a semiconductor wafer to a carrier wafer with an adhesive material. The semiconductor wafer includes an etch stop disposed within the wafer (e.g., between a first surface a second surface of the wafer). One or more vias are formed through the wafer. The vias extend from the second surface to the etch stop.
摘要翻译：描述了包括仅部分延伸穿过衬底的通孔的半导体器件。贯通衬底通孔（TSV）提供与衬底中形成的电子部件的电互连性。在实现中，半导体器件通过首先使用粘合剂材料将半导体晶片接合到载体晶片来制造。半导体晶片包括设置在晶片内的蚀刻停止（例如，在第一表面和晶片的第二表面之间）。通过晶片形成一个或多个通孔。通孔从第二表面延伸到蚀刻停止。

5. 发明申请

US20130168850A1 SEMICONDUCTOR DEVICE HAVING A THROUGH-SUBSTRATE VIA 有权
标题翻译：具有通孔基板的半导体器件
公开(公告)号：US20130168850A1
公开(公告)日：2013-07-04
申请号：US13342420
申请日：2012-01-03
申请人： Arkadii V. Samoilov , Tyler Parent , Larry Y. Wang
发明人： Arkadii V. Samoilov , Tyler Parent , Larry Y. Wang
IPC分类号： H01L23/48 , H01L21/56
CPC分类号： H01L24/81 , H01L21/568 , H01L21/6835 , H01L21/76898 , H01L23/3128 , H01L23/3135 , H01L23/481 , H01L23/49811 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2221/6834 , H01L2221/6835 , H01L2221/68381 , H01L2224/02313 , H01L2224/02331 , H01L2224/02381 , H01L2224/0239 , H01L2224/024 , H01L2224/03828 , H01L2224/0401 , H01L2224/05025 , H01L2224/0508 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/11002 , H01L2224/11334 , H01L2224/11849 , H01L2224/13022 , H01L2224/13024 , H01L2224/13025 , H01L2224/13111 , H01L2224/13147 , H01L2224/14181 , H01L2224/16145 , H01L2224/16147 , H01L2224/16225 , H01L2224/16227 , H01L2224/81 , H01L2224/81191 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2924/181 , H01L2924/01047 , H01L2924/01029 , H01L2924/01082 , H01L2924/00014 , H01L2924/01013 , H01L2224/11 , H01L2224/02 , H01L2224/03 , H01L2924/00
摘要： Semiconductor devices are described that include a via that extends only partially through the substrate. Through-substrate vias (TSV) furnish electrical interconnectivity to electronic components formed in the substrates. In implementations, the semiconductor devices are fabricated by first bonding a semiconductor wafer to a carrier wafer with an adhesive material. The semiconductor wafer includes an etch stop disposed within the wafer (e.g., between a first surface a second surface of the wafer). One or more vias are formed through the wafer. The vias extend from the second surface to the etch stop.
摘要翻译：描述了包括仅部分延伸穿过衬底的通孔的半导体器件。贯通衬底通孔（TSV）提供与衬底中形成的电子部件的电互连性。在实现中，半导体器件通过首先使用粘合剂材料将半导体晶片接合到载体晶片来制造。半导体晶片包括设置在晶片内的蚀刻停止（例如，在第一表面和晶片的第二表面之间）。通过晶片形成一个或多个通孔。通孔从第二表面延伸到蚀刻停止。

6. 发明授权

US5904543A Method for formation of offset trench isolation by the use of disposable spacer and trench oxidation 失效
标题翻译：通过使用一次性间隔物和沟槽氧化形成偏移沟槽隔离的方法
公开(公告)号：US5904543A
公开(公告)日：1999-05-18
申请号：US623632
申请日：1996-03-28
申请人： Larry Y. Wang
发明人： Larry Y. Wang
IPC分类号： H01L21/762 , C03C15/00
CPC分类号： H01L21/76235
摘要： A method of rounding corners of isolating trenches formed in a substrate with a planar surface includes a first step of forming a masking material on the planar surface. Edges of the masking material are offset from the corners of the isolating trenches. The second method step includes growing an oxide on an exposed portion of the substrate under high temperature. The oxidation under high temperature causes the corners of the isolating trenches to become rounded.
摘要翻译：将形成在具有平坦表面的基板中的隔离沟槽的角部四舍五入的方法包括在平坦表面上形成掩模材料的第一步骤。掩模材料的边缘偏离隔离沟槽的角。第二方法步骤包括在高温下在衬底的暴露部分上生长氧化物。高温下的氧化会导致隔离沟槽的角部变圆。

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