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1. 发明授权

US06754553B2 Implant monitoring using multiple implanting and annealing steps 失效
标题翻译：使用多个植入和退火步骤的植入物监测
公开(公告)号：US06754553B2
公开(公告)日：2004-06-22
申请号：US09820033
申请日：2001-03-28
申请人： Karsten Wieczorek , Manfred Horstmann , Christian Krueger
发明人： Karsten Wieczorek , Manfred Horstmann , Christian Krueger
IPC分类号： G06F1900
CPC分类号： H01L22/10 , H01J2237/30433 , H01J2237/31701 , H01L21/26506 , H01L21/2658
摘要： Test wafer consumption is a significant contributor to overall cost of manufacturing in semiconductor industry due to scrapping the test wafers after one monitoring of implantation parameters. This invention provides a method to reuse the same test wafer for monitoring the implantation parameters more than once. This method comprises the possibility of implanting the same implant species together with identical implanting and annealing conditions as well as of implanting a broad variety of implant species together with varying implanting and annealing conditions. Therefore, this invention helps to significantly reduce the number of test wafers consumed in the implant-area.
摘要翻译：测试晶片消耗是半导体工业制造总体成本的重要因素，因为在一次监测植入参数之后报废测试晶片。本发明提供一种重复使用相同测试晶片多于一次来监测注入参数的方法。该方法包括以相同的植入和退火条件以及植入各种植入物种以及不同的植入和退火条件一起植入相同植入物种的可能性。因此，本发明有助于显着减少在植入区域中消耗的测试晶片的数量。

2. 发明授权

US06812074B2 SOI field effect transistor element having a recombination region and method of forming same 有权
公开(公告)号：US06812074B2
公开(公告)日：2004-11-02
申请号：US10391255
申请日：2003-03-18
申请人： Karsten Wieczorek , Manfred Horstmann , Christian Krueger
发明人： Karsten Wieczorek , Manfred Horstmann , Christian Krueger
IPC分类号： H01L21339
CPC分类号： H01L29/78696 , H01L29/66772 , H01L29/78612 , H01L29/78684 , Y10S438/933 , Y10S438/938
摘要： An SOI transistor element and a method of fabricating the same is disclosed, wherein a high concentration of stationary point defects is created by including a region within the active transistor area that has a slight lattice mismatch. In one particular embodiment, a silicon germanium layer is provided in the active area having a high concentration of point defects due to relaxing the strain of the silicon germanium layer upon heat treating the transistor element. Due to the point defects, the recombination rate is significantly increased, thereby reducing the number of charged carriers stored in the active area.

3. 发明申请

US20050037548A1 SOI field effect transistor element having a recombination region and method of forming same 审中-公开
标题翻译：具有复合区域的SOI场效应晶体管元件及其形成方法
公开(公告)号：US20050037548A1
公开(公告)日：2005-02-17
申请号：US10949089
申请日：2004-09-24
申请人： Karsten Wieczorek , Manfred Horstmann , Christian Krueger
发明人： Karsten Wieczorek , Manfred Horstmann , Christian Krueger
IPC分类号： H01L21/336 , H01L29/786 , H01L21/00
CPC分类号： H01L29/78696 , H01L29/66772 , H01L29/78612 , H01L29/78684
摘要： An SOI transistor element and a method of fabricating the same is disclosed, wherein a high concentration of stationary point defects is created by including a region within the active transistor area that has a slight lattice mismatch. In one particular embodiment, a silicon germanium layer is provided in the active area having a high concentration of point defects due to relaxing the strain of the silicon germanium layer upon heat treating the transistor element. Due to the point defects, the recombination rate is significantly increased, thereby reducing the number of charged carriers stored in the active area.
摘要翻译：公开了SOI晶体管元件及其制造方法，其中通过在有源晶体管区域内包含具有轻微晶格失配的区域来产生高浓度的固定点缺陷。在一个特定实施例中，由于在对晶体管元件进行热处理时放松硅锗层的应变，在有源区域中提供了具有高浓度点缺陷的硅锗层。由于点缺陷，复合率显着增加，从而减少存储在有源区域中的带电载流子数量。

4. 发明授权

US07297994B2 Semiconductor device having a retrograde dopant profile in a channel region 有权
标题翻译：半导体器件在沟道区域具有逆向掺杂物分布
公开(公告)号：US07297994B2
公开(公告)日：2007-11-20
申请号：US11072142
申请日：2005-03-04
申请人： Karsten Wieczorek , Manfred Horstmann , Rolf Stephan
发明人： Karsten Wieczorek , Manfred Horstmann , Rolf Stephan
IPC分类号： H10L29/00 , H01L29/80
CPC分类号： H01L21/823807 , H01L29/1033 , H01L29/105 , H01L29/1054 , H01L29/6659
摘要： An epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure. The channel layer may be undoped or slightly doped, as required, so that the finally obtained dopant concentration in the channel layer is significantly reduced compared to a conventional device to thereby provide a retrograde dopant profile in a channel region of a field effect transistor. Additionally, a barrier diffusion layer may be provided between the well structure and the channel layer to reduce up-diffusion during any heat treatments carried out after the formation of the channel layer. The final dopant profile in the channel region may be adjusted by the thickness of the channel layer, the thickness and the composition of the diffusion barrier layer and any additional implantation steps to introduce dopant atoms in the channel layer.
摘要翻译：在离子注入步骤之后在阱结构上提供外延生长的沟道层，并且进行热处理步骤以在阱结构中建立所需的掺杂剂分布。根据需要，沟道层可以是未掺杂的或稍微掺杂的，使得与常规器件相比，沟道层中最终获得的掺杂剂浓度显着降低，从而在场效应晶体管的沟道区域中提供逆向掺杂物分布。此外，可以在阱结构和沟道层之间提供阻挡扩散层，以在形成沟道层之后进行的任何热处理期间减小向上扩散。可以通过沟道层的厚度，扩散阻挡层的厚度和组成以及在沟道层中引入掺杂剂原子的任何额外的注入步骤来调整沟道区中的最终掺杂物分布。

5. 发明授权

US07217657B2 Semiconductor device having different metal silicide portions and method for fabricating the semiconductor device 有权
标题翻译：具有不同金属硅化物部分的半导体器件和用于制造半导体器件的方法
公开(公告)号：US07217657B2
公开(公告)日：2007-05-15
申请号：US10260926
申请日：2002-09-30
申请人： Karsten Wieczorek , Manfred Horstmann , Rolf Stephan
发明人： Karsten Wieczorek , Manfred Horstmann , Rolf Stephan
IPC分类号： H01L21/44
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/823418 , H01L21/823443 , H01L29/4933
摘要： A method is disclosed in which differing metal layers are sequentially deposited on silicon-containing regions so that the type and thickness of the metal layers may be adapted to specific characteristics of the underlying silicon-containing regions. Subsequently, a heat treatment is performed to convert the metals into metal silicides so as to improve the electrical conductivity of the silicon-containing regions. In this way, silicide portions may be formed that are individually adapted to specific silicon-containing regions so that device performance of individual semiconductor elements or the overall performance of a plurality of semiconductor elements may be significantly improved. Moreover, a semiconductor device is disclosed comprising at least two silicon-containing regions having formed therein differing silicide portions, wherein at least one silicide portion comprises a noble metal.
摘要翻译：公开了一种方法，其中不同的金属层依次沉积在含硅区域上，使得金属层的类型和厚度可以适应于下面的含硅区域的特定特性。随后，进行热处理以将金属转化为金属硅化物，从而提高含硅区域的导电性。以这种方式，可以形成独立地适应特定的含硅区域的硅化物部分，从而可以显着改善各个半导体元件的器件性能或多个半导体元件的整体性能。此外，公开了一种半导体器件，其包括至少两个其中形成有不同硅化物部分的含硅区域，其中至少一个硅化物部分包括贵金属。

6. 发明授权

US07060549B1 SRAM devices utilizing tensile-stressed strain films and methods for fabricating the same 有权
标题翻译：使用拉伸应力应变膜的SRAM器件及其制造方法
公开(公告)号：US07060549B1
公开(公告)日：2006-06-13
申请号：US11174400
申请日：2005-07-01
申请人： Mark Craig , Karsten Wieczorek , Manfred Horstmann
发明人： Mark Craig , Karsten Wieczorek , Manfred Horstmann
IPC分类号： H01L21/8238
CPC分类号： H01L29/7843 , H01L27/11 , H01L27/1104 , H01L29/78
摘要： SRAM devices utilizing tensile-stressed strain films and methods for fabricating such SRAM devices are provided. An SRAM device, in one embodiment, comprises an NFET and a PFET that are electrically coupled and physically isolated. The PFET has a gate region, a source region, and a drain region. A tensile-strained stress film is disposed on the gate region and at least a portion of the source region and the drain region of the PFET. A method for fabricating a cell of an SRAM device comprises fabricating an NFET and a PFET overlying a substrate. The PFET and the NFET are electically coupled and are physically isolated. A tensile-strained stress film is deposited on the gate region and at least a portion of the source region and the drain region of the PFET.
摘要翻译：提供了使用拉伸应力应变膜的SRAM器件和制造这种SRAM器件的方法。在一个实施例中，SRAM器件包括电耦合和物理隔离的NFET和PFET。 PFET具有栅极区域，源极区域和漏极区域。拉伸应变应力膜设置在栅极区域和PFET的源极区域和漏极区域的至少一部分上。用于制造SRAM器件的单元的方法包括制造覆盖衬底的NFET和PFET。 PFET和NFET电耦合并且物理隔离。在栅极区域和PFET的源极区域和漏极区域的至少一部分上沉积拉伸应变膜。

7. 发明申请

US20060046400A1 Method of forming a semiconductor structure comprising transistor elements with differently stressed channel regions 有权
标题翻译：形成半导体结构的方法包括具有不同应力沟道区的晶体管元件
公开(公告)号：US20060046400A1
公开(公告)日：2006-03-02
申请号：US11114262
申请日：2005-04-26
申请人： Gert Burbach , Rolf Stephan , Karsten Wieczorek , Manfred Horstmann
发明人： Gert Burbach , Rolf Stephan , Karsten Wieczorek , Manfred Horstmann
IPC分类号： H01L21/336
CPC分类号： H01L29/7842 , H01L21/823412 , H01L21/823437 , H01L21/823807 , H01L21/823828 , H01L29/7843
摘要： A semiconductor structure comprising a first transistor element and a second transistor element is provided. Stress in channel regions of the first and the second transistor element is controlled by forming stressed layers having a predetermined stress over the transistors. The stressed layers may be used as etch stop layers in the formation of contact vias through an interlayer dielectric formed over the transistors.
摘要翻译：提供包括第一晶体管元件和第二晶体管元件的半导体结构。通过在晶体管上形成具有预定应力的应力层来控制第一和第二晶体管元件的沟道区域中的应力。应力层可以用作通过在晶体管上形成的层间电介质形成接触孔的蚀刻停止层。

8. 发明授权

US06673665B2 Semiconductor device having increased metal silicide portions and method of forming the semiconductor 有权
标题翻译：具有增加的金属硅化物部分的半导体器件和形成半导体的方法
公开(公告)号：US06673665B2
公开(公告)日：2004-01-06
申请号：US10210637
申请日：2002-07-31
申请人： Karsten Wieczorek , Manfred Horstmann , Rolf Stephan
发明人： Karsten Wieczorek , Manfred Horstmann , Rolf Stephan
IPC分类号： H01L218234
CPC分类号： H01L29/66507 , H01L21/28052 , H01L21/28518 , H01L21/823814 , H01L21/823835 , H01L21/823864 , H01L29/665
摘要： The surface area of silicon lines which receives a silicide portion is increased to decrease the line resistance in narrow polysilicon lines, such as gate electrodes. Sidewall spacers are formed such that an upper portion of the line sidewall is exposed so as to react with a refractory metal to form a low resistance silicide. The upper portion may be exposed by overetching the dielectric layer deposited to form the sidewall spacers.
摘要翻译：接收硅化物部分的硅线的表面积增加，以减小诸如栅电极的窄多晶硅线中的线电阻。侧壁间隔件形成为使得侧壁的上部被暴露以与难熔金属反应以形成低电阻硅化物。可以通过过蚀刻沉积以形成侧壁间隔物的介电层来暴露上部。

9. 发明授权

US06281086B1 Semiconductor device having a low resistance gate conductor and method of fabrication the same 有权
标题翻译：具有低电阻栅极导体的半导体器件及其制造方法
公开(公告)号：US06281086B1
公开(公告)日：2001-08-28
申请号：US09422548
申请日：1999-10-21
申请人： Karsten Wieczorek , Manfred Horstmann , Tilo Mantei
发明人： Karsten Wieczorek , Manfred Horstmann , Tilo Mantei
IPC分类号： H01L21336
CPC分类号： H01L29/66507 , H01L21/28052 , H01L21/28105 , H01L29/4966
摘要： A semiconductor device and a method of fabricating the same is provided, wherein the semiconductor device exhibits a lower gate delay time when compared to that of a conventional semiconductor device. The reduction of gate delay time is achieved by providing a conductive layer enclosing the gate electrode so as to significantly increase the surface portion of the gate electrode having a low electric resistance. For example, providing a substantially inverted U-shaped silicide layer enclosing the gate electrode leads to a decrease in the electrical resistance of about 67% with a given aspect ratio of about 1. Moreover, reducing the gate length, i.e., increasing the aspect ratio of the gate electrode results in a nearly complete independence of the gate resistance from the gate length.
摘要翻译：提供一种半导体器件及其制造方法，其中与常规半导体器件相比，半导体器件表现出较低的栅极延迟时间。栅极延迟时间的减小通过提供包围栅电极的导电层来显着增加具有低电阻的栅电极的表面部分来实现。例如，提供围绕栅电极的大致倒U形硅化物层导致电阻降低约67％，给定的纵横比约为1.此外，减小栅极长度，即增加纵横比的栅电极导致栅极电阻几乎完全独立于栅极长度。

10. 发明授权

US07955937B2 Method for manufacturing semiconductor device comprising SOI transistors and bulk transistors 有权
标题翻译：包括SOI晶体管和体晶体管的半导体器件的制造方法
公开(公告)号：US07955937B2
公开(公告)日：2011-06-07
申请号：US11560896
申请日：2006-11-17
申请人： Karsten Wieczorek , Manfred Horstmann , Thomas Feudel , Thomas Heller
发明人： Karsten Wieczorek , Manfred Horstmann , Thomas Feudel , Thomas Heller
IPC分类号： H01L21/331
CPC分类号： H01L21/823481 , H01L21/76243 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L27/1207
摘要： By forming bulk-like transistors in sensitive RAM areas of otherwise SOI-based CMOS circuits, a significant savings in valuable chip area may be achieved since the RAM areas may be formed on the basis of a bulk transistor configuration, thereby eliminating hysteresis effects that may typically be taken into consideration by providing transistors of increased transistor width or by providing body ties. Hence, the benefit of high switching speed may be maintained in speed-critical circuitry, such as CPU cores, while at the same time the RAM circuit may be formed in a highly space-efficient manner.
摘要翻译：通过在其它基于SOI的CMOS电路的敏感RAM区域中形成块状晶体管，可以实现有价值的芯片面积的显着节省，因为可以基于体晶体管配置形成RAM区域，从而消除可能通常通过提供增加的晶体管宽度的晶体管或通过提供身体纽带来考虑。因此，高速切换速度的好处可以保持在诸如CPU内核之类的速度关键电路中，同时可以以高空间效率的方式形成RAM电路。

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