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1. 发明授权

US08923031B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08923031B2
公开(公告)日：2014-12-30
申请号：US13778849
申请日：2013-02-27
申请人： Kabushiki Kaisha Toshiba
发明人： Kei Sakamoto , Masaki Kondo , Nobuaki Yasutake , Takayuki Okamura
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0002 , G11C13/004 , G11C13/0069 , G11C2213/72
摘要： A semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of first lines, a plurality of second lines, and memory cells disposed at each of intersections of the first lines and the second lines; and a control circuit configured to apply a first voltage to a selected first line, apply a second voltage having a voltage value which is smaller than that of the first voltage to a selected second line, and apply a third voltage and a fourth voltage to a non-selected first line and a non-selected second line, respectively. The control circuit is configured to apply a fifth voltage to one of the non-selected first lines that is adjacent to the selected first line, and apply a sixth voltage to one of the non-selected second lines that is adjacent to the selected second line.
摘要翻译：根据实施例的半导体存储器件包括：存储单元阵列，包括多个第一线，多条第二线和设置在第一线和第二线的每个交点处的存储单元; 以及控制电路，被配置为向所选择的第一线施加第一电压，将具有小于第一电压的电压值的第二电压施加到所选择的第二线，并将第三电压和第四电压施加到未选择的第一行和未选择的第二行。控制电路被配置为向与所选择的第一行相邻的未选择的第一行之一施加第五电压，并且将第六电压施加到与所选择的第二行相邻的未选择的第二行之一。

2. 发明授权

US09111858B2 Non-volatile semiconductor memory device and method for manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US09111858B2
公开(公告)日：2015-08-18
申请号：US13838722
申请日：2013-03-15
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Jun Nishimura , Nobuaki Yasutake , Kei Sakamoto , Takayuki Okamura
IPC分类号： H01L21/336 , H01L27/24 , H01L45/00
CPC分类号： H01L27/2481 , H01L27/2409 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1641 , H01L45/1675
摘要： A non-volatile semiconductor memory device includes a cell array layer including a first wire, one or more memory cells stacked on the first wire, and a second wire formed on the memory cell so as to cross the first wire, wherein the memory cell includes a current rectifying element and a variable resistance element, and an atomic composition ratio of nitrogen is higher than that of oxygen in a part of a sidewall of the current rectifying element.
摘要翻译：一种非易失性半导体存储器件包括：单元阵列层，包括第一布线，堆叠在第一布线上的一个或多个存储单元，以及形成在存储单元上以跨越第一布线的第二布线，其中存储单元包括电流整流元件和可变电阻元件，并且氮的原子组成比高于当前整流元件的侧壁的一部分中的氧的原子组成比。

3. 发明申请

US20140003127A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20140003127A1
公开(公告)日：2014-01-02
申请号：US13778371
申请日：2013-02-27
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kei Sakamoto , Takayuki Okamura , Nobuaki Yasutake , Jun Nishimura
IPC分类号： G11C13/00
CPC分类号： G11C13/0002 , G11C13/0023 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/10 , H01L45/12 , H01L45/1233
摘要： A semiconductor memory device according to an embodiment includes a memory cell array including memory cells, the memory cells each configured having a current rectifier element and a variable resistance element connected in series therein. Each of the memory cells has formed on aside surface thereof: a first insulating film provided on aside surface of the current rectifier element and the variable resistance element and having a composition ratio of anon-silicon element to silicon which is a first value; a silicon oxide film provided on a side surface of the first insulating film; and a second insulating film provided on aside surface of the silicon oxide film and having a composition ratio of a non-silicon element to silicon which is a second value. The first value is smaller than the second value.
摘要翻译：根据实施例的半导体存储器件包括存储单元阵列，该存储单元阵列包括存储单元，每个存储单元均配置有电流整流元件和串联连接的可变电阻元件。每个存储单元形成在其旁边表面上：设置在电流整流元件和可变电阻元件的另一表面上的第一绝缘膜，并且具有作为第一值的硅 - 硅元件与硅的组成比; 设置在所述第一绝缘膜的侧面上的氧化硅膜; 以及设置在氧化硅膜的表面上并具有作为第二值的非硅元素与硅的组成比的第二绝缘膜。第一个值小于第二个值。

4. 发明申请

US20130277640A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：US20130277640A1
公开(公告)日：2013-10-24
申请号：US13838722
申请日：2013-03-15
申请人： Kabushiki Kaisha Toshiba
发明人： Jun NISHIMURA , Nobuaki Yasutake , Kei Sakamoto , Takayuki Okamura
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L27/2481 , H01L27/2409 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1641 , H01L45/1675
摘要： A non-volatile semiconductor memory device includes a cell array layer including a first wire, one or more memory cells stacked on the first wire, and a second wire formed on the memory cell so as to cross the first wire, wherein the memory cell includes a current rectifying element and a variable resistance element, and an atomic composition ratio of nitrogen is higher than that of oxygen in a part of a sidewall of the current rectifying element.
摘要翻译：一种非易失性半导体存储器件包括：单元阵列层，包括第一布线，堆叠在第一布线上的一个或多个存储单元，以及形成在存储单元上的第二布线，以便跨越第一布线，其中存储单元包括电流整流元件和可变电阻元件，并且氮的原子组成比高于当前整流元件的侧壁的一部分中的氧的原子组成比。

5. 发明授权

US09142288B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09142288B2
公开(公告)日：2015-09-22
申请号：US14563605
申请日：2014-12-08
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kei Sakamoto , Masaki Kondo , Nobuaki Yasutake , Takayuki Okamura
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0002 , G11C13/004 , G11C13/0069 , G11C2213/72
摘要： A semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of first lines, a plurality of second lines, and memory cells disposed at each of intersections of the first lines and the second lines; and a control circuit configured to apply a first voltage to a selected first line, apply a second voltage having a voltage value which is smaller than that of the first voltage to a selected second line, and apply a third voltage and a fourth voltage to a non-selected first line and a non-selected second line, respectively. The control circuit is configured to apply a fifth voltage to one of the non-selected first lines that is adjacent to the selected first line, and apply a sixth voltage to one of the non-selected second lines that is adjacent to the selected second line.
摘要翻译：根据实施例的半导体存储器件包括：存储单元阵列，包括多个第一线，多条第二线和设置在第一线和第二线的每个交点处的存储单元; 以及控制电路，被配置为向所选择的第一线施加第一电压，将具有小于第一电压的电压值的第二电压施加到所选择的第二线，并将第三电压和第四电压施加到未选择的第一行和未选择的第二行。控制电路被配置为向与所选择的第一行相邻的未选择的第一行之一施加第五电压，并且将第六电压施加到与所选择的第二行相邻的未选择的第二行之一。

6. 发明授权

US09583629B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09583629B2
公开(公告)日：2017-02-28
申请号：US14952156
申请日：2015-11-25
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Jun Nishimura , Nobuaki Yasutake , Takayuki Okamura
IPC分类号： H01L29/786 , H01L27/24 , H01L29/423 , H01L29/78 , H01L45/00
CPC分类号： H01L29/78609 , H01L27/2454 , H01L27/249 , H01L29/42368 , H01L29/42376 , H01L29/7827 , H01L29/78624 , H01L29/78642 , H01L45/1226 , H01L45/145 , H01L45/146 , H01L45/148 , H01L45/149 , H01L45/16
摘要： According to one embodiment, a first transistor includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a first gate insulating film, and a first gate electrode. The first semiconductor region is provided in a first semiconductor layer extending in a second direction substantially perpendicular to the surface of the semiconductor substrate from the first line. The second semiconductor region is provided above the first semiconductor region in the first semiconductor layer. The third semiconductor region is provided above the second semiconductor region in the first semiconductor layer. The first gate insulating film covers a first side face of the first semiconductor layer. The first gate electrode covers the first side face of the first semiconductor layer through the first gate insulating film. The first transistor has an asymmetrical structure with respect to a center face of the second semiconductor region in the second direction.
摘要翻译：根据一个实施例，第一晶体管包括第一半导体区域，第二半导体区域，第三半导体区域，第一栅极绝缘膜和第一栅极电极。第一半导体区域设置在第一半导体层中，该第一半导体层在与第一线基本上垂直于半导体衬底的表面的第二方向上延伸。第二半导体区域设置在第一半导体层中的第一半导体区域的上方。第三半导体区域设置在第一半导体层中的第二半导体区域的上方。第一栅极绝缘膜覆盖第一半导体层的第一侧面。第一栅极电极通过第一栅极绝缘膜覆盖第一半导体层的第一侧面。第一晶体管相对于第二半导体区域的第二方向的中心面具有不对称结构。

7. 发明授权

US09368196B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09368196B2
公开(公告)日：2016-06-14
申请号：US14578847
申请日：2014-12-22
申请人： Kabushiki Kaisha Toshiba
发明人： Kei Sakamoto , Takayuki Okamura , Nobuaki Yasutake , Jun Nishimura
IPC分类号： G11C13/00 , H01L45/00 , H01L27/24
CPC分类号： G11C13/0002 , G11C13/0023 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/10 , H01L45/12 , H01L45/1233
摘要： A semiconductor memory device according to an embodiment includes a memory cell array including memory cells, the memory cells each configured having a current rectifier element and a variable resistance element connected in series therein. Each of the memory cells has formed on a side surface thereof: a first insulating film provided on a side surface of the current rectifier element and the variable resistance element and having a composition ratio of a non-silicon element to silicon which is a first value; a silicon oxide film provided on a side surface of the first insulating film; and a second insulating film provided on a side surface of the silicon oxide film and having a composition ratio of a non-silicon element to silicon which is a second value. The first value is smaller than the second value.
摘要翻译：根据实施例的半导体存储器件包括存储单元阵列，该存储单元阵列包括存储单元，每个存储单元均配置有电流整流元件和串联连接的可变电阻元件。每个存储单元形成在其侧表面上：设置在电流整流元件和可变电阻元件的侧表面上的第一绝缘膜，并且具有作为第一值的非硅元件与硅的组成比 ; 设置在所述第一绝缘膜的侧面上的氧化硅膜; 以及设置在所述氧化硅膜的侧面上并且具有作为第二值的非硅元素与硅的组成比的第二绝缘膜。第一个值小于第二个值。

8. 发明授权

US09184217B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US09184217B2
公开(公告)日：2015-11-10
申请号：US14022443
申请日：2013-09-10
申请人： Kabushiki Kaisha Toshiba
发明人： Nobuaki Yasutake , Takayuki Okamura
IPC分类号： H01L47/00 , H01L27/24
CPC分类号： H01L27/2454 , H01L27/2481 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/16
摘要： According to one embodiment, a memory device includes: a first interconnect extending in a first direction; a plurality of second interconnects extending in a second direction intersecting with the first direction, and having lower ends positioned on the first interconnect; a plurality of third interconnects extending in a third direction intersecting with the second direction; a memory layer provided between the second interconnects and the third interconnects; and selectors respectively provided between the first interconnect and the lower ends of the plurality of second interconnects.
摘要翻译：根据一个实施例，存储器件包括：沿第一方向延伸的第一互连; 多个第二互连件，其在与所述第一方向相交的第二方向上延伸，并且具有位于所述第一互连件上的下端; 多个第三互连件，沿与第二方向相交的第三方向延伸; 设置在第二互连和第三互连之间的存储层; 以及分别设置在多个第二互连件的第一互连和下端之间的选择器。

9. 发明申请

US20150255510A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20150255510A1
公开(公告)日：2015-09-10
申请号：US14461720
申请日：2014-08-18
申请人： Kabushiki Kaisha Toshiba
发明人： Jun Nishimura , Nobuaki Yasutake , Takayuki Okamura
IPC分类号： H01L27/24 , H01L29/78
CPC分类号： H01L29/78609 , H01L27/2454 , H01L27/249 , H01L29/42368 , H01L29/42376 , H01L29/7827 , H01L29/78624 , H01L29/78642 , H01L45/1226 , H01L45/145 , H01L45/146 , H01L45/148 , H01L45/149 , H01L45/16
摘要： According to one embodiment, a first transistor includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a first gate insulating film, and a first gate electrode. The first semiconductor region is provided in a first semiconductor layer extending in a second direction substantially perpendicular to the surface of the semiconductor substrate from the first line. The second semiconductor region is provided above the first semiconductor region in the first semiconductor layer. The third semiconductor region is provided above the second semiconductor region in the first semiconductor layer. The first gate insulating film covers a first side face of the first semiconductor layer. The first gate electrode covers the first side face of the first semiconductor layer through the first gate insulating film. The first transistor has an asymmetrical structure with respect to a center face of the second semiconductor region in the second direction.
摘要翻译：根据一个实施例，第一晶体管包括第一半导体区域，第二半导体区域，第三半导体区域，第一栅极绝缘膜和第一栅极电极。第一半导体区域设置在第一半导体层中，该第一半导体层在与第一线基本上垂直于半导体衬底的表面的第二方向上延伸。第二半导体区域设置在第一半导体层中的第一半导体区域的上方。第三半导体区域设置在第一半导体层中的第二半导体区域的上方。第一栅极绝缘膜覆盖第一半导体层的第一侧面。第一栅极电极通过第一栅极绝缘膜覆盖第一半导体层的第一侧面。第一晶体管相对于第二半导体区域的第二方向的中心面具有不对称结构。

10. 发明授权

US08937830B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08937830B2
公开(公告)日：2015-01-20
申请号：US13778371
申请日：2013-02-27
申请人： Kabushiki Kaisha Toshiba
发明人： Kei Sakamoto , Takayuki Okamura , Nobuaki Yasutake , Jun Nishimura
IPC分类号： G11C13/00 , H01L45/00 , H01L27/24
CPC分类号： G11C13/0002 , G11C13/0023 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/10 , H01L45/12 , H01L45/1233
摘要： A semiconductor memory device according to an embodiment includes a memory cell array including memory cells, the memory cells each configured having a current rectifier element and a variable resistance element connected in series therein. Each of the memory cells has formed on aside surface thereof: a first insulating film provided on aside surface of the current rectifier element and the variable resistance element and having a composition ratio of a non-silicon element to silicon which is a first value; a silicon oxide film provided on a side surface of the first insulating film; and a second insulating film provided on aside surface of the silicon oxide film and having a composition ratio of a non-silicon element to silicon which is a second value. The first value is smaller than the second value.
摘要翻译：根据实施例的半导体存储器件包括存储单元阵列，该存储单元阵列包括存储单元，每个存储单元均配置有电流整流元件和串联连接的可变电阻元件。每个存储单元形成在其旁边表面上：设置在电流整流元件和可变电阻元件的另一表面上并具有作为第一值的非硅元件与硅的组成比的第一绝缘膜; 设置在所述第一绝缘膜的侧面上的氧化硅膜; 以及设置在氧化硅膜的表面上并具有作为第二值的非硅元素与硅的组成比的第二绝缘膜。第一个值小于第二个值。

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