专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09583437B2 Manufacturing method of a semiconductor device and method for creating a layout thereof 有权
标题翻译：半导体器件的制造方法及其布局的制造方法
公开(公告)号：US09583437B2
公开(公告)日：2017-02-28
申请号：US14829250
申请日：2015-08-18
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kosuke Yanagidaira , Chikaaki Kodama
IPC分类号： H01L23/528 , H01L21/768 , H01L21/311 , H01L23/522 , H01L27/02 , H01L27/115 , H01L23/48
CPC分类号： H01L23/528 , H01L21/31144 , H01L21/76802 , H01L21/76816 , H01L21/76877 , H01L23/48 , H01L23/522 , H01L27/0207 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L2924/0002 , H01L2924/00
摘要： A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.
摘要翻译：本发明的一个实施例的半导体器件的制造方法包括：在衬底上形成待加工的绝缘层; 在所述衬底上的第一区域中形成第一牺牲层，所述第一牺牲层被图案化以在所述第一区域中形成连接到元件的功能线; 在所述衬底上的第二区域中形成第二牺牲层，所述第二牺牲层被图案化以在所述第二区域中形成虚拟布线; 在所述第一牺牲层的侧壁处形成第三牺牲层，并在所述第二牺牲层的侧壁处形成第四牺牲层，所述第三牺牲层和所述第四牺牲层被分离; 通过使用第三牺牲层和第四牺牲层作为掩模蚀刻待处理的绝缘层来形成凹部; 并在凹部中填充导电材料。

2. 发明授权

US08816723B1 Buffer circuit 有权
标题翻译：缓冲电路
公开(公告)号：US08816723B1
公开(公告)日：2014-08-26
申请号：US13959984
申请日：2013-08-06
申请人： Kabushiki Kaisha Toshiba
发明人： Kosuke Yanagidaira
IPC分类号： H03K5/22
CPC分类号： G05F3/16 , G11C7/1084 , H03K19/0027
摘要： A buffer circuit includes a first current mirror circuit, a second current mirror circuit, a first transistor, and a second transistor. The first current mirror circuit passes a first mirror current through a second node, corresponding to a first current passed through a first node, and is activated based on a first activating signal. The second current mirror circuit is connected to the first node and the second node, passes a second mirror current through the second node, corresponding to a second current passed through the first node, and is activated based on a second activating signal. The first transistor has a gate to which a reference voltage is applied and has a drain connected to the first node. The second transistor has a gate to which an input voltage is applied and has a drain connected to the second node.
摘要翻译：缓冲电路包括第一电流镜电路，第二电流镜电路，第一晶体管和第二晶体管。第一电流镜电路将第一镜像电流通过第二节点，对应于通过第一节点的第一电流，并且基于第一激活信号被激活。第二电流镜电路连接到第一节点和第二节点，通过第二镜像电流通过第二节点，对应于通过第一节点的第二电流，并且基于第二激活信号被激活。第一晶体管具有施加参考电压的栅极，并且漏极连接到第一节点。第二晶体管具有施加输入电压的栅极，并且漏极连接到第二节点。

3. 发明授权

US08742822B2 Level shift circuit 有权
标题翻译：电平移位电路
公开(公告)号：US08742822B2
公开(公告)日：2014-06-03
申请号：US13752501
申请日：2013-01-29
申请人： Kabushiki Kaisha Toshiba
发明人： Kosuke Yanagidaira , Shouichi Ozaki , Kenro Kubota
IPC分类号： H03L5/00
CPC分类号： H03K17/063 , H03K19/018521 , H03L5/00
摘要： According to one embodiment, a first CMOS inverter receives an input signal corresponding to a first power supply voltage, and is driven by a second power supply voltage which is smaller than the first power supply voltage; a second CMOS inverter is connected to a rear stage of the first CMOS inverter, and is driven by the second power supply voltage; a first driving adjustment circuit adjusts a current driving force of a low level output of the first CMOS inverter; and a second driving adjustment circuit adjusts a current driving force of a low level output of the second CMOS inverter.
摘要翻译：根据一个实施例，第一CMOS反相器接收对应于第一电源电压的输入信号，并且由比第一电源电压小的第二电源电压驱动; 第二CMOS反相器连接到第一CMOS反相器的后级，并由第二电源电压驱动; 第一驱动调整电路调节第一CMOS反相器的低电平输出的电流驱动力; 并且第二驱动调节电路调节第二CMOS反相器的低电平输出的电流驱动力。

4. 发明申请

US20140049308A1 LEVEL SHIFT CIRCUIT 有权
标题翻译：水平移位电路
公开(公告)号：US20140049308A1
公开(公告)日：2014-02-20
申请号：US13752501
申请日：2013-01-29
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kosuke Yanagidaira , Shouichi Ozaki , Kenro Kubota
IPC分类号： H03K17/06 , H03L5/00
CPC分类号： H03K17/063 , H03K19/018521 , H03L5/00
摘要： According to one embodiment, a first CMOS inverter receives an input signal corresponding to a first power supply voltage, and is driven by a second power supply voltage which is smaller than the first power supply voltage; a second CMOS inverter is connected to a rear stage of the first CMOS inverter, and is driven by the second power supply voltage; a first driving adjustment circuit adjusts a current driving force of a low level output of the first CMOS inverter; and a second driving adjustment circuit adjusts a current driving force of a low level output of the second CMOS inverter.
摘要翻译：根据一个实施例，第一CMOS反相器接收对应于第一电源电压的输入信号，并且由比第一电源电压小的第二电源电压驱动; 第二CMOS反相器连接到第一CMOS反相器的后级，并由第二电源电压驱动; 第一驱动调整电路调节第一CMOS反相器的低电平输出的电流驱动力; 并且第二驱动调节电路调节第二CMOS反相器的低电平输出的电流驱动力。

5. 发明授权

US09653125B2 Storage device, memory device and semiconductor device for improving data transfer speeds 有权
公开(公告)号：US09653125B2
公开(公告)日：2017-05-16
申请号：US15009377
申请日：2016-01-28
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Shouichi Ozaki , Kosuke Yanagidaira
IPC分类号： G11C7/10 , G11C5/06 , G11C5/14 , G06F1/26
CPC分类号： G11C5/06 , G06F1/26 , G11C5/147 , G11C7/1057 , G11C7/1084 , G11C2029/0411
摘要： According to one embodiment, a storage device includes a memory device including a memory cell configured to hold data, an output buffer configured to output the data, and a circuit configured to generate a reference voltage; and a controller device including an input buffer. The data from the output buffer is input into one input terminal of the input buffer and the reference voltage from the circuit is input into the other input terminal of the input buffer.

6. 发明授权

US09570182B1 Semiconductor memory device and memory system 有权
标题翻译：半导体存储器件和存储器系统
公开(公告)号：US09570182B1
公开(公告)日：2017-02-14
申请号：US15000687
申请日：2016-01-19
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kosuke Yanagidaira , Shouichi Ozaki
IPC分类号： G11C16/04 , G11C16/14 , G11C16/26
CPC分类号： G11C16/32 , G11C7/1057 , G11C7/1084 , G11C7/109 , G11C16/10 , G11C16/20 , G11C16/26 , G11C29/022 , G11C29/028 , G11C29/50008 , G11C29/50012 , G11C2029/0409 , G11C2207/105
摘要： According to one embodiment, a semiconductor memory device comprises an input circuit configured to input data, a memory cell array which includes memory cells enabling data to be held and to which the input data is written, a control circuit configured to control operation of a memory relating to the data, and a training circuit configured to execute training of the input circuit in parallel with the operation of the memory.
摘要翻译：根据一个实施例，半导体存储器件包括被配置为输入数据的输入电路，存储单元阵列，其包括使能够保持数据并且输入数据被写入的存储单元，配置成控制存储器的操作的控制电路以及训练电路，被配置为与存储器的操作并行地执行输入电路的训练。

7. 发明授权

US09564185B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09564185B1
公开(公告)日：2017-02-07
申请号：US15000433
申请日：2016-01-19
申请人： Kabushiki Kaisha Toshiba
发明人： Kosuke Yanagidaira
IPC分类号： G11C7/00 , G11C7/10 , G11C7/22 , G11C8/06 , G11C7/12 , G11C8/18
CPC分类号： G11C7/12 , G11C7/1081 , G11C8/06 , G11C8/18
摘要： According to one embodiment, a semiconductor memory device includes a memory including a memory cell array, and an input/output pin configured to transfer data, a command, and an address from an external to the memory. The memory includes a termination circuit provided between the input/output pin and the memory cell array, and configured to supply a first voltage having a first amplitude in a first transfer mode and supply a second voltage having a second amplitude in a second transfer mode, a first intermediate value of the first amplitude being different from a second intermediate value of the second amplitude.
摘要翻译：根据一个实施例，半导体存储器件包括存储器单元阵列，以及被配置为将数据，命令和地址从外部传送到存储器的输入/输出引脚。存储器包括设置在输入/输出引脚和存储单元阵列之间的终端电路，并且被配置为在第一传输模式中提供具有第一幅度的第一电压并且在第二传输模式中提供具有第二幅度的第二电压，第一幅度的第一中间值不同于第二幅度的第二中间值。

8. 发明授权

US09520164B1 ZQ calibration circuit and semiconductor device including the same 有权
标题翻译： ZQ校准电路和包括其的半导体器件
公开(公告)号：US09520164B1
公开(公告)日：2016-12-13
申请号：US14947955
申请日：2015-11-20
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kensuke Yamamoto , Kosuke Yanagidaira , Shouichi Ozaki
IPC分类号： H03K17/16 , G11C7/00 , G11C7/10 , H03K3/353
CPC分类号： G11C7/1057 , G11C2207/2254 , H03K19/17764
摘要： According to one embodiment, a ZQ calibration circuit comprises a replica buffer controller configured to apply electric stress to a replica buffer circuit with a circuit configuration substantially identical to a circuit configuration of an output buffer circuit according to a usage status of the output buffer circuit during a period when no calibration operation is performed.
摘要翻译：根据一个实施例，ZQ校准电路包括复制缓冲器控制器，其被配置为根据输出缓冲器电路的使用状态根据输出缓冲器电路的使用状态将电应力施加到具有与输出缓冲器电路的电路配置基本相同的电路配置的复制缓冲器电路不执行校准操作的时间段。

9. 发明授权

US09209070B2 Manufacturing method of a semiconductor device and method for creating a layout thereof 有权
标题翻译：半导体器件的制造方法及其布局的制造方法
公开(公告)号：US09209070B2
公开(公告)日：2015-12-08
申请号：US14492940
申请日：2014-09-22
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kosuke Yanagidaira , Chikaaki Kodama
IPC分类号： H01L21/44 , H01L21/768 , H01L21/311 , H01L23/522 , H01L27/02 , H01L27/115 , H01L23/48
CPC分类号： H01L23/528 , H01L21/31144 , H01L21/76802 , H01L21/76816 , H01L21/76877 , H01L23/48 , H01L23/522 , H01L27/0207 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L2924/0002 , H01L2924/00
摘要： A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.
摘要翻译：本发明的一个实施例的半导体器件的制造方法包括：在衬底上形成待加工的绝缘层; 在所述衬底上的第一区域中形成第一牺牲层，所述第一牺牲层被图案化以在所述第一区域中形成连接到元件的功能线; 在所述衬底上的第二区域中形成第二牺牲层，所述第二牺牲层被图案化以在所述第二区域中形成虚拟布线; 在所述第一牺牲层的侧壁处形成第三牺牲层，并在所述第二牺牲层的侧壁处形成第四牺牲层，所述第三牺牲层和所述第四牺牲层被分离; 通过使用第三牺牲层和第四牺牲层作为掩模蚀刻待处理的绝缘层来形成凹部; 并在凹部中填充导电材料。

10. 发明申请

US20170076756A1 STORAGE DEVICE, MEMORY DEVICE AND SEMICONDUCTOR DEVICE 有权
标题翻译：存储器件，存储器件和半导体器件
公开(公告)号：US20170076756A1
公开(公告)日：2017-03-16
申请号：US15009377
申请日：2016-01-28
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Shouichi OZAKI , Kosuke Yanagidaira
IPC分类号： G11C5/06 , G11C5/14 , G06F1/26 , G11C7/10
CPC分类号： G11C5/06 , G06F1/26 , G11C5/147 , G11C7/1057 , G11C7/1084 , G11C2029/0411
摘要： According to one embodiment, a storage device includes a memory device including a memory cell configured to hold data, an output buffer configured to output the data, and a circuit configured to generate a reference voltage; and a controller device including an input buffer. The data from the output buffer is input into one input terminal of the input buffer and the reference voltage from the circuit is input into the other input terminal of the input buffer.
摘要翻译：根据一个实施例，一种存储装置包括：存储器件，其包括被配置为保持数据的存储器单元，被配置为输出数据的输出缓冲器和被配置为产生参考电压的电路; 以及包括输入缓冲器的控制器装置。来自输出缓冲器的数据被输入到输入缓冲器的一个输入端，并且来自电路的参考电压被输入到输入缓冲器的另一个输入端。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式