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1. 发明授权

US08122265B2 Power management using adaptive thermal throttling 有权
标题翻译：电源管理采用自适应热调节
公开(公告)号：US08122265B2
公开(公告)日：2012-02-21
申请号：US11648253
申请日：2006-12-29
申请人： Sivakumar Radhakrishnan , Suneeta Sah , William H. Nale , Rami Naqib , Howard S. David , Rajat Agarwal
发明人： Sivakumar Radhakrishnan , Suneeta Sah , William H. Nale , Rami Naqib , Howard S. David , Rajat Agarwal
IPC分类号： G06F1/00
CPC分类号： G06F1/206 , G06F1/3203
摘要： In some embodiments, a chip includes a scheduler, transmitters, receivers, and control circuitry. The schedule schedules signals to be transmitted outside the chip and the transmitters transmit the scheduled signals outside the chip. The receivers receive signals including signals with temperature information related to a temperature outside the chip. The control circuitry selectively limit a number of commands that can be scheduled within a series of smaller windows while checking the temperature information near the conclusion of a larger window comprising many smaller windows. Other embodiments are described.
摘要翻译：在一些实施例中，芯片包括调度器，发射机，接收机和控制电路。时间表调度要在芯片外部发送的信号，并且发送器在芯片外发送调度信号。接收器接收包括具有与芯片外的温度有关的温度信息的信号的信号。控制电路选择性地限制可以在一系列较小窗口内调度的多个命令，同时检查靠近包括许多较小窗口的较大窗口的结论的温度信息。描述其他实施例。

2. 发明申请

US20080163226A1 Power management using adaptive thermal throttling 有权
标题翻译：电源管理采用自适应热调节
公开(公告)号：US20080163226A1
公开(公告)日：2008-07-03
申请号：US11648253
申请日：2006-12-29
申请人： Sivakumar Radhakrisnan , Suneeta Sah , William H. Nale , Rami Naqib , Howard S. David , Rajat Agarwal
发明人： Sivakumar Radhakrisnan , Suneeta Sah , William H. Nale , Rami Naqib , Howard S. David , Rajat Agarwal
IPC分类号： G06F9/46
CPC分类号： G06F1/206 , G06F1/3203
摘要： In some embodiments, a chip includes a scheduler, transmitters, receivers, and control circuitry. The schedule schedules signals to be transmitted outside the chip and the transmitters transmit the scheduled signals outside the chip. The receivers receive signals including signals with temperature information related to a temperature outside the chip. The control circuitry selectively limit a number of commands that can be scheduled within a series of smaller windows while checking the temperature information near the conclusion of a larger window comprising many smaller windows. Other embodiments are described.
摘要翻译：在一些实施例中，芯片包括调度器，发射机，接收机和控制电路。时间表调度要在芯片外部发送的信号，并且发送器在芯片外发送调度信号。接收器接收包括具有与芯片外的温度有关的温度信息的信号的信号。控制电路选择性地限制可以在一系列较小窗口内调度的多个命令，同时检查靠近包括许多较小窗口的较大窗口的结论的温度信息。描述其他实施例。

3. 发明授权

US08272781B2 Dynamic power control of a memory device thermal sensor 有权
标题翻译：存储器件热传感器的动态功率控制
公开(公告)号：US08272781B2
公开(公告)日：2012-09-25
申请号：US11497946
申请日：2006-08-01
申请人： William H. Nale
发明人： William H. Nale
IPC分类号： G01K7/00 , G01K13/00
CPC分类号： G01K7/425 , G06F1/206 , G06F1/3203 , G06F1/3275 , G06F11/3034 , G06F11/3037 , G06F11/3093 , Y02D10/13 , Y02D10/14 , Y02D10/16
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for the dynamic power control of a memory device thermal sensor. In some embodiments a memory device includes an on-die thermal sensor and enable logic to dynamically enable or disable the on-die thermal sensor. In some embodiments, the on-die thermal sensor senses thermal data responsive to a thermal data sense indication. The thermal data sense indication may be received subsequent to the expiration of a delay period.
摘要翻译：本发明的实施例通常涉及用于存储器件热传感器的动态功率控制的系统，方法和装置。在一些实施例中，存储器设备包括管芯内热敏传感器，并且启用逻辑以动态地启用或禁用管芯上的热传感器。在一些实施例中，管芯上热敏传感器响应于热数据检测指示感测热数据。可以在延迟周期期满之后接收热量数据检测指示。

4. 发明授权

US5276833A Data cache management system with test mode using index registers and CAS disable and posted write disable 失效
标题翻译：数据缓存管理系统具有测试模式使用索引寄存器和CAS禁用和发布写禁用
公开(公告)号：US5276833A
公开(公告)日：1994-01-04
申请号：US544821
申请日：1990-07-02
申请人： Stuart T. Auvinen , William H. Nale
发明人： Stuart T. Auvinen , William H. Nale
IPC分类号： G06F11/22 , G06F12/08 , G11C29/52
CPC分类号： G11C29/52 , G06F11/22 , G06F12/0802
摘要： A memory controller which can be used with an external tag RAM is disclosed. Existing index registers in the controller serve double duty as buffers for storing tag RAM data during a test mode. Input/output lines for the external tag RAM are coupled to the index registers in addition to being coupled to a comparator for comparison with an external address during normal operation. A buffer is provided so that data from the external address from the CPU can be written through these same tag RAM input/output lines in order to update the tag RAM after a miss. In order to prevent DRAMS from putting data on the memory bus during a cache RAM test, a CAS inhibit signal is provided to the DRAM state machine. Posted writes are also disabled to avoid interference with the address provided to the tag RAM.
摘要翻译：公开了可以与外部标签RAM一起使用的存储器控制器。控制器中的现有索引寄存器在测试模式期间用作存储标签RAM数据的缓冲器。外部标签RAM的输入/输出线除了在正常操作之前与外部地址相比较之外还与比较器耦合到索引寄存器。提供了一个缓冲区，使得来自CPU的外部地址的数据可以通过这些相同的标签RAM输入/输出线写入，以便在错过后更新标签RAM。为了防止DRAMS在高速缓存RAM测试期间将数据置于存储器总线上，CAS禁止信号被提供给DRAM状态机。发布的写入也被禁用，以避免干扰提供给标签RAM的地址。

5. 发明授权

US5793385A Address translator for a shared memory computing system 失效
标题翻译：共享内存计算系统的地址转换器
公开(公告)号：US5793385A
公开(公告)日：1998-08-11
申请号：US662057
申请日：1996-06-12
申请人： William H. Nale
发明人： William H. Nale
IPC分类号： G06F12/02 , G06F12/06
CPC分类号： G06F12/0292
摘要： An address translator for use in a system having a central processing unit, a graphics controller for generating graphics addresses which index a graphics memory address map and for feeding data to a visual display, and a system memory converts a graphics address to a system address within the system memory. The invention initially partitions the system memory into a dedicated system memory for use by the graphics controller and a non-dedicated system memory for use by the central processing unit. The dedicated system memory corresponds to a base assigned memory within the graphics memory address map, and the non-dedicated system memory corresponds to a portion of the graphics memory address map excluding the base assigned memory. If the graphics address is within the base assigned memory, the graphics address is translated to a corresponding system address within the dedicated system memory. If the graphics address is within the portion of the graphics memory address map excluding the base assigned memory, the address translator converts the graphics address to a system address within the non-dedicated system memory, which designates a starting address of an available system memory block. Upon completion of the translation of the graphics address to the non-dedicated system memory, the boundary selector then selects a specific address within this allocated memory block corresponding to the graphics address.
摘要翻译：一种用于具有中央处理单元的系统中的地址转换器，用于产生图形地址的图形控制器的图形控制器，用于将图形存储器地址映射索引并将数据馈送到可视显示器，并且系统存储器将图形地址转换为系统地址系统内存。本发明最初将系统存储器划分为专用系统存储器，供图形控制器和非专用系统存储器供中央处理单元使用。专用系统存储器对应于图形存储器地址图中的基本分配的存储器，并且非专用系统存储器对应于除基本分配的存储器之外的图形存储器地址映射的一部分。如果图形地址在基本分配的存储器内，则图形地址被转换为专用系统存储器内的相应系统地址。如果图形地址在除了基本分配的存储器之外的图形存储器地址映射的部分内，则地址转换器将图形地址转换为非专用系统存储器中的系统地址，其指定可用系统存储器块的起始地址。当完成将图形地址转换到非专用系统存储器时，边界选择器然后选择与该图形地址相对应的该分配的存储块内的特定地址。

6. 发明申请

US20080043556A1 Dynamic power control of a memory device thermal sensor 有权
标题翻译：存储器件热传感器的动态功率控制
公开(公告)号：US20080043556A1
公开(公告)日：2008-02-21
申请号：US11497946
申请日：2006-08-01
申请人： William H. Nale
发明人： William H. Nale
IPC分类号： G11C11/34 , G11C7/04
CPC分类号： G01K7/425 , G06F1/206 , G06F1/3203 , G06F1/3275 , G06F11/3034 , G06F11/3037 , G06F11/3093 , Y02D10/13 , Y02D10/14 , Y02D10/16
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for the dynamic power control of a memory device thermal sensor. In some embodiments a memory device includes an on-die thermal sensor and enable logic to dynamically enable or disable the on-die thermal sensor. In some embodiments, the on-die thermal sensor senses thermal data responsive to a thermal data sense indication. The thermal data sense indication may be received subsequent to the expiration of a delay period.
摘要翻译：本发明的实施例通常涉及用于存储器件热传感器的动态功率控制的系统，方法和装置。在一些实施例中，存储器设备包括管芯内热敏传感器，并且启用逻辑以动态地启用或禁用管芯上的热传感器。在一些实施例中，管芯上热敏传感器响应于热数据检测指示感测热数据。可以在延迟周期期满之后接收热量数据检测指示。

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