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1. 发明申请

US20170271347A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 有权
公开(公告)号：US20170271347A1
公开(公告)日：2017-09-21
申请号：US15264086
申请日：2016-09-13
申请人： Kabushiki Kaisha Toshiba
发明人： Yoshiaki FUKUZUMI
IPC分类号： H01L27/115
CPC分类号： H01L27/11565 , H01L27/11582 , H01L28/00
摘要： According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, and a columnar portion. The stacked body includes a first insulating layer provided on the substrate, a first electrode layer provided on the first insulating layer and including polycrystalline silicon, a second insulating layer provided on the first electrode layer, and a second electrode layer provided on the second insulating layer. The columnar portion includes a semiconductor layer extending in a stacking direction of the stacked body and a memory layer provided between the semiconductor layer and the stacked body. The first and second electrode layers respectively have a first thickness and a second thickness in the stacking direction, and the first thickness of the first electrode layer is thicker than the second thickness of the second electrode layer.

2. 发明申请

US20160126251A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20160126251A1
公开(公告)日：2016-05-05
申请号：US14601384
申请日：2015-01-21
申请人： Kabushiki Kaisha Toshiba
发明人： Masanari FUJITA , Yoshiaki FUKUZUMI
IPC分类号： H01L27/115 , H01L29/49
CPC分类号： H01L27/11582 , H01L27/11573 , H01L27/11575 , H01L29/495
摘要： According to one embodiment, a semiconductor memory device includes a substrate that includes a first region and a second region; a stacked body that is disposed on the first region of the substrate and includes a plurality of first metal layers and a plurality of voids each of which is disposed between the plurality of first metal layers; a columnar portion that penetrates the stacked body, extends in a direction of stacking in the stacking body; a transistor that is disposed on the second region; and the interconnect portion that is disposed on the transistor and includes the plurality of first metal layers and a plurality of second metal layers each of which is disposed between the plurality of first metal layers. The transistor is electrically connected to the channel body or the first metal layer of the stacked body through a interconnect portion.
摘要翻译：根据一个实施例，半导体存储器件包括：衬底，其包括第一区域和第二区域; 所述层叠体设置在所述基板的所述第一区域上，并且包括多个第一金属层和多个空隙，每个所述多个第一金属层设置在所述多个第一金属层之间; 穿过层叠体的柱状部在堆叠体的堆叠方向上延伸; 设置在所述第二区域上的晶体管; 以及布置在晶体管上并包括多个第一金属层的互连部分和多个第二金属层，每个第二金属层设置在多个第一金属层之间。晶体管通过互连部分电连接到层叠体的沟道体或第一金属层。

3. 发明申请

US20140085989A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20140085989A1
公开(公告)日：2014-03-27
申请号：US14017725
申请日：2013-09-04
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yoshiaki FUKUZUMI
IPC分类号： G11C16/08
CPC分类号： G11C16/08 , G11C16/0483 , G11C16/10 , G11C29/028 , G11C2029/5002
摘要： According to one embodiment, a semiconductor memory device includes memory units each of which includes first and second select transistors and memory cells connected in series between the first and second select transistors. A control circuit applies a first potential difference between a source and a drain of either the first or second select transistor in a first memory unit, thereby programming either the first or second select transistor. The control circuit applies a second potential difference between a source and a drain of either the first or second select transistor in a second memory unit connected in common to the same select gate line as that of the first memory unit, thereby inhibiting either the first or second select transistor from being programmed.
摘要翻译：根据一个实施例，半导体存储器件包括各自包括第一和第二选择晶体管和在第一和第二选择晶体管之间串联连接的存储单元的存储单元。控制电路在第一存储器单元中施加第一或第二选择晶体管的源极和漏极之间的第一电位差，从而对第一或第二选择晶体管进行编程。控制电路在与第一存储器单元相同的选择栅极线共同连接的第二存储器单元中的第一或第二选择晶体管的源极和漏极之间施加第二电位差，从而抑制第一或第二选择晶体管的第一或第二选择晶体管的第一或第二电位差，第二选择晶体管被编程。

4. 发明申请

US20130126961A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
公开(公告)号：US20130126961A1
公开(公告)日：2013-05-23
申请号：US13740803
申请日：2013-01-14
申请人： Kabushiki Kaisha Toshiba
发明人： Yoshiaki FUKUZUMI , Ryota Katsumata , Masaru Kidoh , Masaru Kito , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Hideaki Aochi
IPC分类号： H01L27/105
CPC分类号： H01L27/11582 , G11C16/0483 , H01L27/1052 , H01L27/11551 , H01L27/11556 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L29/513
摘要： A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

5. 发明申请

US20170148815A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 有权
公开(公告)号：US20170148815A1
公开(公告)日：2017-05-25
申请号：US15424532
申请日：2017-02-03
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yoshiaki FUKUZUMI , Ryota KATSUMATA , Masaru KITO , Masaru KIDOH , Hiroyasu TANAKA , Yosuke KOMORI , Megumi ISHIDUKI , Junya MATSUNAMI , Tomoko FUJIWARA , Hideaki AOCHI , Ryouhei KlRISAWA , Yoshimasa MIKAJIRI , Shigeta OOTA
IPC分类号： H01L27/11582 , H01L21/223 , H01L29/49 , H01L21/265 , H01L29/10 , H01L29/423
CPC分类号： H01L27/11582 , H01L21/223 , H01L21/265 , H01L27/11578 , H01L29/04 , H01L29/1037 , H01L29/16 , H01L29/42344 , H01L29/4916 , H01L29/66666 , H01L29/66833 , H01L29/7827 , H01L29/792 , H01L29/7926
摘要： A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

6. 发明申请

US20170053935A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20170053935A1
公开(公告)日：2017-02-23
申请号：US15345790
申请日：2016-11-08
申请人： Kabushiki Kaisha Toshiba
发明人： Yoshiaki FUKUZUMI , Shinya ARAI , Masaki TSUJI , Hideaki AOCHI , Hiroyasu TANAKA
IPC分类号： H01L27/115 , H01L29/423
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/11575 , H01L29/42344 , H01L29/66833 , H01L29/7926
摘要： A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.
摘要翻译：一种半导体存储器件，包括：包括半导体材料，第一电极膜，第一绝缘膜，堆叠体和三个或更多个半导体柱的连接构件。层叠体包括交替堆叠的第二电极膜和第二绝缘膜。半导体柱沿着两个或更多个方向排列，沿层叠方向延伸，穿过层叠体和第一绝缘膜，并连接到连接构件。该装置包括设置在半导体柱和层叠体之间以及连接构件和第一电极膜之间的第三绝缘膜。至少在一个第二电极膜和第三绝缘膜之间设置电荷存储层。

7. 发明申请

US20160300846A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20160300846A1
公开(公告)日：2016-10-13
申请号：US15184735
申请日：2016-06-16
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yoshiaki FUKUZUMI
IPC分类号： H01L27/115 , H01L29/45
CPC分类号： H01L29/456 , H01L27/1157 , H01L27/11582
摘要： According to one embodiment, a semiconductor memory device includes a substrate; a stacked body provided on the substrate and including a first stacked portion, a second stacked portion and an intermediate layer, the first stacked portion and the second stacked portion including a plurality of electrode layers and a plurality of insulating layers, the intermediate layer provided between the first stacked portion and the second stacked portion; a column including a semiconductor film and a charge storage film; and an insulating part provided in the stacked body. The column has a first enlarged portion. The insulating part has a second enlarged portion surrounded by the intermediate layer, the second enlarged portion has a larger width than a width of the portion of the insulating part in the first stacked portion and the second stacked portion.
摘要翻译：根据一个实施例，半导体存储器件包括衬底; 设置在所述基板上并且包括第一堆叠部分，第二堆叠部分和中间层的层叠体，所述第一堆叠部分和所述第二堆叠部分包括多个电极层和多个绝缘层，所述中间层设置在第一堆叠部分和第二堆叠部分; 包括半导体膜和电荷存储膜的列; 以及设置在所述层叠体中的绝缘部。该列具有第一放大部分。绝缘部分具有由中间层包围的第二扩大部分，第二扩大部分具有比第一堆叠部分和第二堆叠部分中的绝缘部分的部分的宽度更大的宽度。

8. 发明申请

US20160276363A1 METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：制造半导体存储器件的方法
公开(公告)号：US20160276363A1
公开(公告)日：2016-09-22
申请号：US14844250
申请日：2015-09-03
申请人： Kabushiki Kaisha Toshiba
发明人： Yoshiaki FUKUZUMI , Hideaki Aochi , Mitsuhiro Omura
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L27/11565
摘要： According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a mask layer on the stacked body. The method includes forming a stopper film in a part of the mask layer. The method includes forming a plurality of mask holes in the mask layer. The mask holes include a first mask hole overlapping on the stopper film. The method includes, by etching using the mask layer, forming holes in the stacked body under other mask holes than the first mask hole on the stopper film, but not forming holes in the stacked body under the stopper film. The method includes forming memory films and channel bodies in the holes.
摘要翻译：根据一个实施例，一种用于制造半导体存储器件的方法包括在层叠体上形成掩模层。该方法包括在掩模层的一部分中形成阻挡膜。该方法包括在掩模层中形成多个掩模孔。掩模孔包括在止动膜上重叠的第一掩模孔。该方法包括通过使用掩模层进行蚀刻，在阻挡膜上的第一掩模孔之外的其他掩模孔的下面的层叠体中形成孔，但是在阻挡膜下方不形成堆叠体中的孔。该方法包括在孔中形成记忆膜和通道体。

9. 发明申请

US20160087067A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20160087067A1
公开(公告)日：2016-03-24
申请号：US14842312
申请日：2015-09-01
申请人： Kabushiki Kaisha Toshiba
发明人： Shigeki HATTORI , Tsukasa TADA , Masaya TERAI , Hideyuki NISHIZAWA , Koji ASAKAWA , Yoshiaki FUKUZUMI
IPC分类号： H01L29/51 , H01L29/792
CPC分类号： H01L29/518 , G11C11/5664 , G11C16/0483 , H01L27/285 , H01L29/511 , H01L29/517 , H01L51/0091 , H01L51/0591
摘要： A nonvolatile semiconductor memory device according to an embodiment includes: a semiconductor layer; a control gate electrode; and an organic molecular layer, which is provided between the semiconductor layer and the control gate electrode, and has organic molecules including a molecular structure described by a molecular formula (1).
摘要翻译：根据实施例的非易失性半导体存储器件包括：半导体层; 控制栅电极; 以及设置在半导体层和控制栅电极之间的有机分子层，并且具有包含分子式（1）所示的分子结构的有机分子。

10. 发明申请

US20160079267A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20160079267A1
公开(公告)日：2016-03-17
申请号：US14722543
申请日：2015-05-27
申请人： Kabushiki Kaisha Toshiba
发明人： Yoshiaki FUKUZUMI , Masaki TSUJI
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L27/11556
摘要： According to one embodiment, a first layer; a stacked body provided above the first layer and including a plurality of electrode layers separately stacked each other; a second layer provided between the first layer and the stacked body; an intermediate layer provided between the first layer and the second layer; a semiconductor body provided in the stacked body, the second layer, the intermediate layer and the first layer, the semiconductor body extending in a stacking direction of the stacked body; and a charge storage film provided between the semiconductor body and the plurality of electrode layers. The semiconductor body includes a side surface connected with the intermediate layer in the vicinity of a boundary between the first layer and the second layer. At least one of the first layer and the second layer has conductivity and is connected with the intermediate layer.
摘要翻译：根据一个实施例，第一层; 设置在所述第一层上方并且包括彼此分开堆叠的多个电极层的层叠体; 设置在第一层和层叠体之间的第二层; 设置在所述第一层和所述第二层之间的中间层; 设置在所述层叠体中的半导体本体，所述第二层，所述中间层和所述第一层，所述半导体本体沿所述层叠体的层叠方向延伸; 以及设置在所述半导体主体和所述多个电极层之间的电荷存储膜。半导体本体包括与第一层和第二层之间的边界附近的中间层连接的侧表面。第一层和第二层中的至少一层具有导电性并与中间层连接。

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