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1. 发明申请

US20170278862A1 SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20170278862A1
公开(公告)日：2017-09-28
申请号：US15266416
申请日：2016-09-15
申请人： Kabushiki Kaisha Toshiba
发明人： Jun FUJIKI , Takeshi KAMIGAICHI , Hideaki AOCHI
IPC分类号： H01L27/115 , H01L23/528
CPC分类号： H01L27/11582 , H01L23/528 , H01L27/11524 , H01L27/11556 , H01L27/1157
摘要： A semiconductor memory device according to an embodiment comprises: a plurality of memory strings arranged in a first direction intersecting a surface of a semiconductor substrate, each of the memory strings including a plurality of memory transistors connected in series in a second direction along the surface of the semiconductor substrate; a source side select transistor connected to one end of the memory string; a drain side select transistor connected to the other end of the memory string; a plurality of source lines respectively connected, via the source side select transistor, to each of the plurality of memory strings arranged along the first direction; a bit line commonly connected, via the drain side select transistor, to the plurality of memory strings arranged along the first direction; a word line connected to a gate electrode of the memory transistor; and a layer selector disposed between the source line and the source side select transistor and commonly connected to the plurality of memory strings arranged along the first direction.

2. 发明申请

US20170263636A1 STACKED NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH BURIED SOURCE LINE AND METHOD OF MANUFACTURE 有权
公开(公告)号：US20170263636A1
公开(公告)日：2017-09-14
申请号：US15266850
申请日：2016-09-15
申请人： Kabushiki Kaisha Toshiba
发明人： Takashi ISHIDA , Jun FUJIKI , Shinya ARAI , Fumitaka ARAI , Hideaki AOCHI , Kotaro FUJII
IPC分类号： H01L27/115 , H01L23/522 , H01L23/528
CPC分类号： H01L27/11582 , H01L23/5226 , H01L23/5283 , H01L27/1157 , H01L27/11573 , H01L27/11578
摘要： According to one embodiment, a semiconductor device includes a first interconnection, a first semiconductor region, a stacked body, a columnar portion, first insulators, and arrays. The first interconnection is provided on a substrate via a first insulating film interposed. The first semiconductor region is provided on the first interconnection via a second insulating film. The stacked body is provided on the first semiconductor region. The columnar portion is provided in the stacked body. The first insulators are provided in the stacked body. The first insulators extend in the stacking direction and a first direction crossing the stacking direction. The arrays are provided in the first semiconductor region. The arrays each include second semiconductor regions. The second semiconductor regions are separated from each other. The second semiconductor regions are provided under the first insulators. The second semiconductor regions are electrically connected to the first interconnection.

3. 发明申请

US20170148815A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 有权
公开(公告)号：US20170148815A1
公开(公告)日：2017-05-25
申请号：US15424532
申请日：2017-02-03
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yoshiaki FUKUZUMI , Ryota KATSUMATA , Masaru KITO , Masaru KIDOH , Hiroyasu TANAKA , Yosuke KOMORI , Megumi ISHIDUKI , Junya MATSUNAMI , Tomoko FUJIWARA , Hideaki AOCHI , Ryouhei KlRISAWA , Yoshimasa MIKAJIRI , Shigeta OOTA
IPC分类号： H01L27/11582 , H01L21/223 , H01L29/49 , H01L21/265 , H01L29/10 , H01L29/423
CPC分类号： H01L27/11582 , H01L21/223 , H01L21/265 , H01L27/11578 , H01L29/04 , H01L29/1037 , H01L29/16 , H01L29/42344 , H01L29/4916 , H01L29/66666 , H01L29/66833 , H01L29/7827 , H01L29/792 , H01L29/7926
摘要： A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

4. 发明申请

US20170053935A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20170053935A1
公开(公告)日：2017-02-23
申请号：US15345790
申请日：2016-11-08
申请人： Kabushiki Kaisha Toshiba
发明人： Yoshiaki FUKUZUMI , Shinya ARAI , Masaki TSUJI , Hideaki AOCHI , Hiroyasu TANAKA
IPC分类号： H01L27/115 , H01L29/423
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/11575 , H01L29/42344 , H01L29/66833 , H01L29/7926
摘要： A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.
摘要翻译：一种半导体存储器件，包括：包括半导体材料，第一电极膜，第一绝缘膜，堆叠体和三个或更多个半导体柱的连接构件。层叠体包括交替堆叠的第二电极膜和第二绝缘膜。半导体柱沿着两个或更多个方向排列，沿层叠方向延伸，穿过层叠体和第一绝缘膜，并连接到连接构件。该装置包括设置在半导体柱和层叠体之间以及连接构件和第一电极膜之间的第三绝缘膜。至少在一个第二电极膜和第三绝缘膜之间设置电荷存储层。

5. 发明申请

US20160260736A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20160260736A1
公开(公告)日：2016-09-08
申请号：US14821921
申请日：2015-08-10
申请人： Kabushiki Kaisha Toshiba
发明人： Kotaro FUJII , Hideaki AOCHI
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157
摘要： According to one embodiment, the semiconductor film includes a first semiconductor part, a second semiconductor part, and a third semiconductor part. The first semiconductor part extends in the stacked body in a stacking direction of the stacked body. The second semiconductor part extends in the stacked body in the stacking direction and a first direction crossing the stacking direction. The third semiconductor part extends in the underlayer in a second direction connecting the first semiconductor part and the second semiconductor part. The first semiconductor part, the second semiconductor part and the third semiconductor part are made of a same material and are continuous with each other. The first metal layer is in contact with a side surface of the second semiconductor part.
摘要翻译：根据一个实施例，半导体膜包括第一半导体部件，第二半导体部件和第三半导体部件。第一半导体部件在堆叠体的堆叠方向上延伸。第二半导体部在层叠体的堆叠方向和与堆叠方向交叉的第一方向上延伸。第三半导体部分沿着连接第一半导体部件和第二半导体部件的第二方向在底层中延伸。第一半导体部件，第二半导体部件和第三半导体部件由相同的材料制成并且彼此连续。第一金属层与第二半导体部件的侧面接触。

6. 发明申请

US20150036422A1 MAGNETIC STORAGE ELEMENT, MAGNETIC STORAGE DEVICE, MAGNETIC MEMORY, AND METHOD OF DRIVING MAGNETIC STORAGE ELEMENT 有权
标题翻译：磁性存储元件，磁性存储器件，磁性存储器和驱动磁存储元件的方法
公开(公告)号：US20150036422A1
公开(公告)日：2015-02-05
申请号：US14341059
申请日：2014-07-25
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Hirofumi MORISE , Yoshiaki FUKUZUMI , Shiho NAKAMURA , Tsuyoshi KONDO , Hideaki AOCHI , Takuya SHIMADA
IPC分类号： H01L27/22 , H01L43/02 , G11C11/16
CPC分类号： H01L27/222 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C11/1693 , H01L43/08
摘要： A magnetic storage element according to an embodiment includes: a magnetic nanowire having a cross-sectional area varying in a first direction, the magnetic nanowire having at least two positions where the cross-sectional area is minimal; first and second electrode groups having the magnetic nanowire interposed in between, the magnetic nanowire including at least one of a first region where the first electrodes overlap the second electrodes with the magnetic nanowire interposed in between and a second region where neither the first electrodes nor the second electrodes exist with the magnetic nanowire interposed in between, the magnetic nanowire including at least one of a third region where the first electrodes exist and the second electrodes do not exist with the magnetic nanowire interposed in between and a fourth region where the first electrodes do not exist and the second electrodes exist with the magnetic nanowire interposed in between.
摘要翻译：根据实施例的磁存储元件包括：具有在第一方向上变化的横截面积的磁性纳米线，所述磁性纳米线具有截面积最小的至少两个位置; 具有介于其间的磁性纳米线的第一和第二电极组，所述磁性纳米线包括第一电极与第二电极重叠的第一区域和介于其间的磁性纳米线的第一区域和第二区域中的至少一个，存在介于其间的磁性纳米线的第二电极，磁纳米线包括存在第一电极的第三区域和不存在插入在其间的磁性纳米线的第二电极和第一电极的第四区域中的至少一个不存在第二电极，并且介于其间的磁性纳米线存在。

7. 发明申请

US20140231889A1 SHIFT REGISTER MEMORY AND DRIVING METHOD THEREOF 有权
标题翻译：移位寄存器及其驱动方法
公开(公告)号：US20140231889A1
公开(公告)日：2014-08-21
申请号：US14268701
申请日：2014-05-02
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yoshiaki FUKUZUMI , Hideaki AOCHI
IPC分类号： H01L27/22
CPC分类号： H01L27/228 , G11C11/14 , G11C11/15 , G11C11/155 , G11C11/16 , G11C11/161 , G11C11/1675 , G11C19/02 , G11C19/0808 , G11C19/0833 , H01L27/22 , H01L43/02
摘要： A shift register memory according to the present embodiment includes a magnetic pillar including a plurality of magnetic layers and a plurality of nonmagnetic layers provided between the magnetic layers adjacent to each other. A stress application part applies a stress to the magnetic pillar. A magnetic-field application part applies a static magnetic field to the magnetic pillar. The stress application part applies the stress to the magnetic pillar in order to transfer magnetization states of the magnetic layers in a stacking direction of the magnetic layers.
摘要翻译：根据本实施例的移位寄存器存储器包括具有多个磁性层的磁柱和设置在彼此相邻的磁性层之间的多个非磁性层。应力施加部分对磁柱施加应力。磁场施加部分将静磁场施加到磁柱。应力施加部分将应力施加到磁柱，以便在磁性层的堆叠方向上传递磁性层的磁化状态。

8. 发明申请

US20140104941A1 MAGNETIC MEMORY 有权
标题翻译：磁记忆
公开(公告)号：US20140104941A1
公开(公告)日：2014-04-17
申请号：US14021096
申请日：2013-09-09
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Tsuyoshi KONDO , Hirofumi MORISE , Shiho NAKAMURA , Takuya SHIMADA , Yoshiaki FUKUZUMI , Hideaki AOCHI
IPC分类号： G11C11/02
CPC分类号： G11C11/02 , B82Y10/00 , G11C11/161 , G11C11/1675 , G11C19/0808 , G11C19/0841 , G11C21/00 , G11C2213/52 , Y10S977/762 , Y10S977/838 , Y10S977/943
摘要： A magnetic memory according to an embodiment includes: a magnetic nanowire; first insulating layers provided on a first surface of the magnetic nanowire, each of the first insulating layers having a first and second end faces, a thickness of the first insulating layer over the first end face being thicker than a thickness of the first insulating layer over the second end face; first electrodes on surfaces of the first insulating layers opposite to the first surface; second insulating layers on the second surface of the magnetic nanowire, each of the second insulating layers having a third and fourth end faces, a thickness of the second insulating layer over the third surface being thicker than a thickness of the second insulating layer over the fourth end face; and second electrodes on surfaces of the second insulating layers.
摘要翻译：根据实施例的磁存储器包括：磁性纳米线; 设置在所述磁性纳米线的第一表面上的第一绝缘层，每个所述第一绝缘层具有第一和第二端面，所述第一端面上的所述第一绝缘层的厚度比所述第一绝缘层的厚度厚第二个端面; 所述第一绝缘层与所述第一表面相对的表面上的第一电极; 在所述磁性纳米线的所述第二表面上的第二绝缘层，每个所述第二绝缘层具有第三和第四端面，所述第三绝缘层的厚度在所述第三表面上比第四绝缘层厚度大端面以及在第二绝缘层的表面上的第二电极。

9. 发明申请

US20170271365A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
公开(公告)号：US20170271365A1
公开(公告)日：2017-09-21
申请号：US15271473
申请日：2016-09-21
申请人： Kabushiki Kaisha Toshiba
发明人： Kotaro FUJII , Hideaki AOCHI
IPC分类号： H01L27/115 , H01L23/528
CPC分类号： H01L27/11582 , H01L23/5283 , H01L27/11565 , H01L27/1157
摘要： The memory string comprises: a first semiconductor layer; a stacked body in which a plurality of conductive layers and a plurality of interlayer insulating layers are stacked along a first direction above the first semiconductor layer; and a second semiconductor layer having a longitudinal direction along the first direction and provided above the first semiconductor layer. The memory insulating layer includes a charge accumulation layer between the second semiconductor layer and the plurality of the conductive layers. The core insulating layer has a longitudinal direction along the first direction, and is provided in the second semiconductor layer. The oxide film layer is provided between the core insulating layer and the second semiconductor layer.

10. 发明申请

US20160190152A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 有权
公开(公告)号：US20160190152A1
公开(公告)日：2016-06-30
申请号：US15064270
申请日：2016-03-08
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yoshiaki FUKUZUMI , Ryota KATSUMATA , Masaru KITO , Masaru KIDOH , Hiroyasu TANAKA , Yosuke KOMORI , Megumi ISHIDUKI , Junya MATSUNAMI , Tomoko FUJIWARA , Hideaki AOCHI , Ryouhei KlRISAWA , Yoshimasa MIKAJIRI , Shigeto OOTA
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L21/223 , H01L21/265 , H01L27/11578 , H01L29/04 , H01L29/1037 , H01L29/16 , H01L29/42344 , H01L29/4916 , H01L29/66666 , H01L29/66833 , H01L29/7827 , H01L29/792 , H01L29/7926
摘要： A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

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