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1. 发明授权

US09280461B2 Memory system with selective access to first and second memories 有权
标题翻译：具有选择性访问第一和第二存储器的存储器系统
公开(公告)号：US09280461B2
公开(公告)日：2016-03-08
申请号：US14335361
申请日：2014-07-18
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yasushi Nagadomi
IPC分类号： G06F12/00 , G06F12/02 , G06F13/16 , G06F13/40
CPC分类号： G06F3/0604 , G06F3/0629 , G06F3/0688 , G06F12/0246 , G06F13/1684 , G06F13/4022 , G06F2212/7202
摘要： A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.
摘要翻译：存储器系统包括：非易失性存储器，其中并入有多个非易失性存储器芯片;控制非易失性存储器的控制电路;控制控制电路的MPU;以及与主机通信的接口电路，所有接口电路都安装在存储器系统的板，并且存储器系统还包括总线开关，其切换控制电路和非易失性存储器芯片之间的信号线的连接。

2. 发明授权

US08947933B2 Nonvolatile semiconductor memory apparatus 有权
标题翻译：非易失性半导体存储装置
公开(公告)号：US08947933B2
公开(公告)日：2015-02-03
申请号：US13913024
申请日：2013-06-07
申请人： Kabushiki Kaisha Toshiba
发明人： Naoya Tokiwa , Yasushi Nagadomi
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/0483 , G11C11/5621 , G11C29/025 , G11C29/04 , G11C29/76 , G11C29/88 , G11C2029/1204 , H01L27/0688 , H01L27/1157 , H01L27/11573 , H01L27/11582
摘要： According to one embodiment, a nonvolatile semiconductor memory apparatus includes a memory cell array, a row decoder, a controller. The memory cell array includes a plurality of memory strings. The memory strings include a first select transistor and a second select transistor, and are connected to each of a plurality of bit lines. The row decoder applies a voltage to the first and second select transistors. The controller detects a defect of the bit lines based on data read from the memory cells.
摘要翻译：根据一个实施例，非易失性半导体存储装置包括存储单元阵列，行解码器，控制器。存储单元阵列包括多个存储器串。存储器串包括第一选择晶体管和第二选择晶体管，并且连接到多个位线中的每一个。行解码器向第一和第二选择晶体管施加电压。控制器基于从存储器单元读取的数据来检测位线的缺陷。

3. 发明授权

US09330772B2 Non-volatile semiconductor memory device and memory system 有权
公开(公告)号：US09330772B2
公开(公告)日：2016-05-03
申请号：US14748351
申请日：2015-06-24
申请人： Kabushiki Kaisha Toshiba
发明人： Yasushi Nagadomi
IPC分类号： G11C16/04 , G11C16/14 , G11C11/56 , G11C16/06 , G11C16/10
CPC分类号： G11C16/14 , G11C11/5628 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/3459
摘要： A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations.

4. 发明授权

US08832362B2 Memory system controlling load capacity 有权
标题翻译：内存系统控制负载能力
公开(公告)号：US08832362B2
公开(公告)日：2014-09-09
申请号：US14063278
申请日：2013-10-25
申请人： Kabushiki Kaisha Toshiba
发明人： Yasushi Nagadomi
IPC分类号： G06F12/00
CPC分类号： G06F3/0604 , G06F3/0629 , G06F3/0688 , G06F12/0246 , G06F13/1684 , G06F13/4022 , G06F2212/7202
摘要： A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.
摘要翻译：存储器系统包括：非易失性存储器，其中并入有多个非易失性存储器芯片;控制非易失性存储器的控制电路;控制控制电路的MPU;以及与主机通信的接口电路，所有接口电路都安装在存储器系统的板，并且存储器系统还包括总线开关，其切换控制电路和非易失性存储器芯片之间的信号线的连接。

5. 发明授权

US09502116B2 Nonvolatile semiconductor memory apparatus 有权
公开(公告)号：US09502116B2
公开(公告)日：2016-11-22
申请号：US14581420
申请日：2014-12-23
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Naoya Tokiwa , Yasushi Nagadomi
IPC分类号： G11C16/04 , G11C11/56 , G11C29/02 , H01L27/115 , G11C29/04 , G11C29/00 , H01L27/06 , G11C29/12
CPC分类号： G11C16/0483 , G11C11/5621 , G11C29/025 , G11C29/04 , G11C29/76 , G11C29/88 , G11C2029/1204 , H01L27/0688 , H01L27/1157 , H01L27/11573 , H01L27/11582
摘要： According to one embodiment, a nonvolatile semiconductor memory apparatus includes a memory cell array, a row decoder, a controller. The memory cell array includes a plurality of memory strings. The memory strings include a first select transistor and a second select transistor, and are connected to each of a plurality of bit lines. The row decoder applies a voltage to the first and second select transistors. The controller detects a defect of the bit lines based on data read from the memory cells.

6. 发明授权

US09076536B2 Non-volatile semiconductor memory device and memory system 有权
标题翻译：非易失性半导体存储器件和存储器系统
公开(公告)号：US09076536B2
公开(公告)日：2015-07-07
申请号：US14093108
申请日：2013-11-29
申请人： Kabushiki Kaisha Toshiba
发明人： Yasushi Nagadomi
IPC分类号： G11C16/04 , G11C16/14 , G11C11/56 , G11C16/06 , G11C16/10
CPC分类号： G11C16/14 , G11C11/5628 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/3459
摘要： A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations.
摘要翻译：非易失性半导体存储器件包括存储单元阵列和控制电路。控制电路执行擦除操作，为存储单元提供具有用于擦除存储单元的数据的第一阈值电压电平，然后执行提供具有第二阈值电压电平的存储单元的多个第一写入操作，第二阈值电压电平高于第一阈值电压电平并且是正电平。当控制电路在第一写入操作期间从外部接收到第一执行指令时，第一执行指令用于执行除了擦除操作和第一写入操作之外的第一功能操作，该电路在第一写入操作期间执行第一功能操作。

7. 发明授权

US09075740B2 Memory system 有权
标题翻译：内存系统
公开(公告)号：US09075740B2
公开(公告)日：2015-07-07
申请号：US14296001
申请日：2014-06-04
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yasushi Nagadomi , Daisaburo Takashima , Kosuke Hatsuda
IPC分类号： G06F12/00 , G06F11/10 , G06F12/02 , G11C16/10
CPC分类号： G06F11/1016 , G06F12/0246 , G06F2212/7203 , G06F2212/7209 , G11C16/102
摘要： A memory system (10) is disclosed, which comprises a flash-EEPROM nonvolatile memory (11) having a plurality of memory cells that have floating gates and in which data items are electrically erasable and writable, a cache memory (13) that temporarily stores data of the flash-EEPROM nonvolatile memory (11), a control circuit (12, 14) that controls the flash-EEPROM nonvolatile memory (11) and the cache memory (13), and an interface circuit (16) that communicates with a host, in which the control circuit functions to read data from a desired target area to-be-determined of the flash-EEPROM nonvolatile memory and detect an erased area to determine a written area/unwritten area by using as a determination condition whether or not a count number of data “0” of the read data has reached a preset criterion count number.
摘要翻译：一种存储系统（10），其包括具有多个存储单元的闪存EEPROM非易失性存储器（11），所述多个存储器单元具有浮动栅极，并且其中数据项是电可擦除和可写的;高速缓冲存储器（13），其临时存储闪存EEPROM非易失性存储器（11）的数据，控制闪存EEPROM非易失性存储器（11）和高速缓存存储器（13）的控制电路（12,14）以及与主机，其中控制电路用于从要被确定的闪存EEPROM非易失性存储器的期望目标区域读取数据，并且通过使用作为确定条件来检测擦除区域以确定写入区域/未写入区域读取数据的数据“0”的计数数已经达到预设的标准计数。

8. 发明授权

US09583200B2 Non-volatile semiconductor memory device and memory system in which write operation is resumed after being suspended for an interrupt operation 有权
标题翻译：非易失性半导体存储器件和存储器系统，其中在暂停中断操作之后恢复写操作
公开(公告)号：US09583200B2
公开(公告)日：2017-02-28
申请号：US15074190
申请日：2016-03-18
申请人： Kabushiki Kaisha Toshiba
发明人： Yasushi Nagadomi
IPC分类号： G11C16/04 , G11C16/14 , G11C11/56 , G11C16/06 , G11C16/10
CPC分类号： G11C16/14 , G11C11/5628 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/3459
摘要： A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations.
摘要翻译：非易失性半导体存储器件包括存储单元阵列和控制电路。控制电路执行擦除操作，为存储单元提供具有用于擦除存储单元的数据的第一阈值电压电平，然后执行提供具有第二阈值电压电平的存储单元的多个第一写入操作，第二阈值电压电平高于第一阈值电压电平并且是正电平。当控制电路在第一写入操作期间从外部接收到第一执行指令时，第一执行指令用于执行除了擦除操作和第一写入操作之外的第一功能操作，该电路在第一写入操作期间执行第一功能操作。

9. 发明授权

US08885417B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08885417B2
公开(公告)日：2014-11-11
申请号：US14046477
申请日：2013-10-04
申请人： Kabushiki Kaisha Toshiba
发明人： Yasushi Nagadomi , Naoya Tokiwa
IPC分类号： G11C11/34 , G11C16/06 , G11C16/34 , G11C16/10 , G11C16/04
CPC分类号： G11C16/3459 , G11C16/0483 , G11C16/10 , G11C16/3454
摘要： In writing, a first write operation to a first memory cell is executed; and a second write operation for providing a first threshold-voltage distribution to a second memory cell adjacent to the first one, is executed. The first threshold voltage distribution is a lowest threshold-voltage distribution among the positive threshold voltage distributions. It is verified whether a desired threshold voltage distribution has been obtained in the first memory cell or not (first write verify operation), moreover, it is verified whether a first threshold voltage distribution or a threshold voltage distribution having a voltage level larger than the first threshold-voltage distribution has been obtained in the second memory cell or not (second write verify operation). A control circuit outputs results of the first write verify operation and the second write verify operation.
摘要翻译：在写入时，执行对第一存储单元的第一写入操作; 并且执行用于向与第一阈值电压分布相邻的第二存储单元提供第一阈值电压分布的第二写入操作。第一阈值电压分布是正阈值电压分布中的最低阈值电压分布。验证在第一存储器单元中是否已经获得期望的阈值电压分布（第一写入验证操作），此外，验证第一阈值电压分布或具有大于第一存储器单元的电压电平的阈值电压分布在第二存储器单元中已经获得阈值电压分布（第二写入验证操作）。控制电路输出第一写入验证操作和第二写入验证操作的结果。

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