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1. 发明授权

US09607693B2 Semiconductor storage device 有权
公开(公告)号：US09607693B2
公开(公告)日：2017-03-28
申请号：US14880458
申请日：2015-10-12
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G11C5/06 , G11C13/00
CPC分类号： G11C13/004 , G11C13/0004 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C2013/0054 , G11C2013/0066 , G11C2213/79
摘要： A semiconductor storage device according to the present embodiments includes a first bit line and a first word line. A resistance-change memory element is connected to the first bit line and the first word line. A sense node is connected to the first bit line in a data read operation. A first transistor is connected between the sense node and the first bit line. A second transistor connects the first bit line and a power supply to each other in a data write operation. A first operational amplifier has one input connected to the first bit line, other input receiving a reference voltage, and an output connected in common to a gate of the first transistor and a gate of the second transistor. A sense circuit is connected to the sense node.

2. 发明授权

US09240226B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US09240226B2
公开(公告)日：2016-01-19
申请号：US14202630
申请日：2014-03-10
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G11C7/06 , G11C7/00 , G11C7/10 , G11C7/14 , G11C7/12 , G11C7/08 , G11C16/24 , G11C11/4091
CPC分类号： G11C7/065 , G11C7/06 , G11C7/08 , G11C7/12 , G11C11/4091
摘要： A memory includes a first and second cell storing first data and second or reference-data. A first and second bit-lines connected to the first and second cells respectively correspond to a first and second sense-nodes. A first transfer-gate is inserted/connected between the first bit-line and the first sense-node. A second transfer-gate is inserted/connected between the second bit-line and the second sense-node. A sense-amplifier is inserted or connected between the first and second sense-nodes. A preamplifier includes a first and second common-transistors. The first common-transistor applies a first power-supply voltage to either the first or the second sense-node according to the first and second data or according to the first and reference-data during a data-read-operation. The second common-transistor applies a second power-supply voltage to the other sense-node out of the first and second sense-nodes according to the first and second data or according to the first and reference data.
摘要翻译：存储器包括存储第一数据和第二或参考数据的第一和第二单元。连接到第一和第二小区的第一和第二位线分别对应于第一和第二感测节点。第一传输门被插入/连接在第一位线和第一感测节点之间。第二传输门被插入/连接在第二位线和第二感测节点之间。感测放大器插入或连接在第一和第二感测节点之间。前置放大器包括第一和第二共用晶体管。第一公共晶体管在数据读取操作期间根据第一和第二数据或根据第一和参考数据向第一或第二感测节点施加第一电源电压。第二公共晶体管根据第一和第二数据或根据第一和参考数据将第二电源电压施加到第一和第二感测节点中的另一个感测节点。

3. 发明授权

US09209030B2 Nonvolatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：US09209030B2
公开(公告)日：2015-12-08
申请号：US13960396
申请日：2013-08-06
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Daisaburo Takashima
IPC分类号： H01L29/788 , H01L21/28 , H01L29/423 , H01L29/66 , H01L21/764 , H01L27/115
CPC分类号： H01L21/28273 , H01L21/764 , H01L27/11521 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： According to one embodiment, a nonvolatile memory includes the following structure. A first gate insulating film, a first floating gate, a second gate insulating film and a gate electrode are stacked on a semiconductor region between source and drain electrodes. A second floating gate is formed on a first side surface of the first floating gate. A first insulating film is formed between the first and second floating gates and has an air gap. A third floating gate is formed on a second side surface of the first floating gate on the opposite side of the first side surface. A second insulating film is formed between the first and third floating gates.
摘要翻译：根据一个实施例，非易失性存储器包括以下结构。第一栅绝缘膜，第一浮栅，第二栅极绝缘膜和栅电极堆叠在源极和漏极之间的半导体区域上。第二浮栅形成在第一浮栅的第一侧表面上。第一绝缘膜形成在第一和第二浮栅之间并具有气隙。第三浮栅形成在第一浮动栅极的与第一侧面相反的一侧的第二侧面上。在第一和第三浮栅之间形成第二绝缘膜。

4. 发明授权

US09075740B2 Memory system 有权
标题翻译：内存系统
公开(公告)号：US09075740B2
公开(公告)日：2015-07-07
申请号：US14296001
申请日：2014-06-04
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yasushi Nagadomi , Daisaburo Takashima , Kosuke Hatsuda
IPC分类号： G06F12/00 , G06F11/10 , G06F12/02 , G11C16/10
CPC分类号： G06F11/1016 , G06F12/0246 , G06F2212/7203 , G06F2212/7209 , G11C16/102
摘要： A memory system (10) is disclosed, which comprises a flash-EEPROM nonvolatile memory (11) having a plurality of memory cells that have floating gates and in which data items are electrically erasable and writable, a cache memory (13) that temporarily stores data of the flash-EEPROM nonvolatile memory (11), a control circuit (12, 14) that controls the flash-EEPROM nonvolatile memory (11) and the cache memory (13), and an interface circuit (16) that communicates with a host, in which the control circuit functions to read data from a desired target area to-be-determined of the flash-EEPROM nonvolatile memory and detect an erased area to determine a written area/unwritten area by using as a determination condition whether or not a count number of data “0” of the read data has reached a preset criterion count number.
摘要翻译：一种存储系统（10），其包括具有多个存储单元的闪存EEPROM非易失性存储器（11），所述多个存储器单元具有浮动栅极，并且其中数据项是电可擦除和可写的;高速缓冲存储器（13），其临时存储闪存EEPROM非易失性存储器（11）的数据，控制闪存EEPROM非易失性存储器（11）和高速缓存存储器（13）的控制电路（12,14）以及与主机，其中控制电路用于从要被确定的闪存EEPROM非易失性存储器的期望目标区域读取数据，并且通过使用作为确定条件来检测擦除区域以确定写入区域/未写入区域读取数据的数据“0”的计数数已经达到预设的标准计数。

5. 发明授权

US08811079B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08811079B2
公开(公告)日：2014-08-19
申请号：US13752726
申请日：2013-01-29
申请人： Kabushiki Kaisha Toshiba
发明人： Ryo Fukuda , Daisaburo Takashima
IPC分类号： G11C14/00
CPC分类号： G11C14/00 , G11C14/0018 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C2216/14 , H01L27/11582
摘要： A volatile memory area includes a plurality of second memory cells, a third select transistor, and a fourth select transistor. The plurality of second memory cells are electrically connected in series, and stacked above the substrate. The third select transistor is connected to one end of the plurality of second memory cells, and connected to a second bit line. The fourth select transistor is connected to the other end of the plurality of second memory cells, and unconnected to a second source line. A controller is configured to supply a first voltage to all gates of the second memory cells. The first voltage is capable of turning on the plurality of second memory cells.
摘要翻译：易失性存储区包括多个第二存储单元，第三选择晶体管和第四选择晶体管。多个第二存储单元串联电连接并堆叠在基板上。第三选择晶体管连接到多个第二存储单元的一端，并连接到第二位线。第四选择晶体管连接到多个第二存储单元的另一端，并且不连接到第二源极线。控制器被配置为向第二存储器单元的所有门提供第一电压。第一电压能够接通多个第二存储单元。

6. 发明授权

US09330758B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09330758B1
公开(公告)日：2016-05-03
申请号：US14824204
申请日：2015-08-12
申请人： Kabushiki Kaisha Toshiba
发明人： Daisaburo Takashima
IPC分类号： G11C13/00 , G11C5/06 , G11C5/02
CPC分类号： G11C13/0069 , G11C5/06 , G11C11/1659 , G11C11/1673 , G11C13/0002 , G11C13/0021 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C2013/0042 , G11C2213/75 , G11C2213/79 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1226 , H01L45/144
摘要： According to one embodiment, a semiconductor memory device includes a series connection including first to Nth (N being an integer greater than or equal to 2) two-terminal-type resistance change memory elements connected in series with one another, and having first to (N+1)th terminals from one end thereof to the other end thereof, a first, second, third, and fourth bit lines, first transistors connected between the first bit line and odd-numbered terminals of the series connection, one or more second transistors connected between the second bit line and one or more even-numbered terminals of the series connection, a third transistor connected between the third bit line and the first terminal of the series connection, and a fourth transistor connected between the fourth bit line and the (N+1)th terminal of the series connection.
摘要翻译：根据一个实施例，半导体存储器件包括串联连接的第一至第N（N是大于或等于2的整数）的串联连接，并且具有第一至第 N + 1）个端子，第一，第二，第三和第四位线，连接在串联连接的第一位线和奇数端子之间的第一晶体管，一个或多个第二连接在第二位线和串联连接的一个或多个偶数端子之间的晶体管，连接在第三位线和串联连接的第一端子之间的第三晶体管，以及连接在第四位线与第四位线之间的第四晶体管（N + 1）端子。

7. 发明授权

US09311996B2 Semiconductor storage device having resistance-change storage elements 有权
标题翻译：具有电阻变化的存储元件的半导体存储装置
公开(公告)号：US09311996B2
公开(公告)日：2016-04-12
申请号：US14624995
申请日：2015-02-18
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0038 , G11C11/1675 , G11C11/1677 , G11C13/0004 , G11C13/0026 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/0066 , G11C2013/0078 , G11C2013/0092 , G11C2213/79
摘要： A semiconductor storage device according to an embodiment includes a plurality of resistance-change storage elements. A plurality of bit lines are connected to the storage elements, respectively. A voltage control circuit controls a decreasing rate of an absolute value of a voltage of a selected bit line among the bit lines when data is written to one of the storage elements.
摘要翻译：根据实施例的半导体存储装置包括多个电阻变化存储元件。多个位线分别连接到存储元件。当数据被写入存储元件之一时，电压控制电路控制位线之间所选位线的电压的绝对值的降低率。

8. 发明申请

US20160071585A1 SEMICONDUCTOR STORAGE DEVICE HAVING RESISTANCE-CHANGE STORAGE ELEMENTS 有权
标题翻译：具有电阻变化存储元件的半导体存储器件
公开(公告)号：US20160071585A1
公开(公告)日：2016-03-10
申请号：US14624995
申请日：2015-02-18
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Ryu OGIWARA , Daisaburo Takashima
IPC分类号： G11C13/00
CPC分类号： G11C13/0038 , G11C11/1675 , G11C11/1677 , G11C13/0004 , G11C13/0026 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/0066 , G11C2013/0078 , G11C2013/0092 , G11C2213/79
摘要： A semiconductor storage device according to an embodiment includes a plurality of resistance-change storage elements. A plurality of bit lines are connected to the storage elements, respectively. A voltage control circuit controls a decreasing rate of an absolute value of a voltage of a selected bit line among the bit lines when data is written to one of the storage elements.
摘要翻译：根据实施例的半导体存储装置包括多个电阻变化存储元件。多个位线分别连接到存储元件。当数据被写入存储元件之一时，电压控制电路控制位线之间所选位线的电压的绝对值的降低率。

9. 发明授权

US09653681B2 Semiconductor memory device 有权
公开(公告)号：US09653681B2
公开(公告)日：2017-05-16
申请号：US14838535
申请日：2015-08-28
申请人： Kabushiki Kaisha Toshiba
发明人： Daisaburo Takashima
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/1233 , H01L27/24 , H01L27/2409 , H01L27/2427 , H01L27/2472 , H01L27/249 , H01L45/04 , H01L45/065 , H01L45/085 , H01L45/12 , H01L45/122 , H01L45/1253 , H01L45/14 , H01L45/141 , H01L45/144 , H01L45/146
摘要： According to one embodiment, a semiconductor memory device includes a plurality of first resistance-change memory elements of a two-terminal type, a second resistance-change memory element of a two-terminal type, a rectifier element of a two-terminal type, a local bit line connected to ends of the first resistance-change memory elements, an end of the second resistance-change memory element and an end of the rectifier element, and a global bit line connected to the other end of the second resistance-change memory element.

10. 发明授权

US09230618B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US09230618B2
公开(公告)日：2016-01-05
申请号：US14482098
申请日：2014-09-10
申请人： Kabushiki Kaisha Toshiba
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G11C7/06 , G11C5/06 , G11C7/12 , G11C7/10
CPC分类号： G11C7/062 , G11C5/06 , G11C7/1051 , G11C7/1069 , G11C7/12 , G11C7/14 , G11C7/18 , G11C16/28
摘要： A semiconductor storage device according to the present embodiment includes a memory cell array including a plurality of memory cells. First bit lines transmit read signal voltages from the memory cells. A gate of a first transistor is connected to the first bit lines. A second bit line is connected to one of a drain and a source of the first transistor. A step voltage line is connected to the other one of the drain and the source of the first transistor to apply a step voltage changing in a stepwise manner to the first transistor at a time of reading. A reference-voltage generator generates a reference voltage. A sense part is connected to the second bit line to receive the read signal voltages and the reference voltage.
摘要翻译：根据本实施例的半导体存储装置包括包括多个存储单元的存储单元阵列。第一位线从存储器单元发送读取信号电压。第一晶体管的栅极连接到第一位线。第二位线连接到第一晶体管的漏极和源极之一。阶跃电压线连接到第一晶体管的漏极和源极中的另一个，以在读取时将步进电压逐步地改变到第一晶体管。参考电压发生器产生参考电压。感测部分连接到第二位线以接收读取信号电压和参考电压。

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