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1. 发明授权

US09048224B2 Nonvolatile semiconductor memory device and method for manufacturing same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US09048224B2
公开(公告)日：2015-06-02
申请号：US14042030
申请日：2013-09-30
申请人： Kabushiki Kaisha Toshiba
发明人： Tadashi Iguchi , Ryota Katsumata
IPC分类号： H01L23/48 , H01L27/115 , H01L21/28
CPC分类号： H01L23/481 , H01L21/28282 , H01L27/11578 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes: first and second stacked bodies, first and second semiconductor pillars, a connection portion, a memory film, and a partitioning insulating layer. The stacked bodes include electrode films stacked along a first axis and an inter-electrode insulating film provided between the electrode films. Through-holes are provided in the stacked bodies. The semiconductor pillars are filled into the through-holes. The connection portion electrically connects the semiconductor pillars. The memory film is provided between the semiconductor pillars and the electrode films. The partitioning insulating layer partitions the first and second electrode films. A side surface of the first through-hole on the partitioning insulating layer side and a side surface of the second through-hole on the partitioning insulating layer side have a portion parallel to a plane orthogonal to a second axis from the first stacked body to the second stacked body.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括：第一和第二堆叠体，第一和第二半导体柱，连接部分，存储膜和分隔绝缘层。堆叠的栅极包括沿着第一轴线堆叠的电极膜和设置在电极膜之间的电极间绝缘膜。在堆叠体中设置有通孔。半导体柱被填充到通孔中。连接部电连接半导体支柱。存储膜设置在半导体柱和电极膜之间。分隔绝缘层分隔第一和第二电极膜。分隔绝缘层侧的第一通孔的侧面和分隔绝缘层侧的第二贯通孔的侧面具有与从第一层叠体到第二贯通孔的第二轴正交的平面的部分第二堆叠体。

2. 发明申请

US20130234235A1 METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：制造半导体存储器件和半导体存储器件的方法
公开(公告)号：US20130234235A1
公开(公告)日：2013-09-12
申请号：US13788295
申请日：2013-03-07
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Toru MATSUDA , Tadashi Iguchi , Katsunori Yahashi
IPC分类号： H01L29/66 , H01L29/792
CPC分类号： H01L29/66833 , H01L27/11582 , H01L29/7926
摘要： In one embodiment, a manufacturing method of a semiconductor memory device is disclosed. The method can include forming a stacked body on a substrate. The stacked body includes first silicon films containing impurities and having a concentration difference of the impurities provided among different layers, and non-doped second silicon films each provided between the first silicon films. The method can include forming a hole in the stacked body. The method can include removing the second silicon films by etching through the hole and forming an inter-electrode space between the first silicon films. The method can include forming a memory film including a charge storage film on a side wall of the hole and also forming at least a part of the memory film in the inter-electrode space.
摘要翻译：在一个实施例中，公开了半导体存储器件的制造方法。该方法可以包括在基板上形成层叠体。层叠体包括含有杂质的第一硅膜，并且具有不同层之间提供的杂质的浓度差，以及分别设置在第一硅膜之间的非掺杂的第二硅膜。该方法可以包括在层叠体中形成孔。该方法可以包括通过蚀刻穿过孔并在第一硅膜之间形成电极间空间来去除第二硅膜。该方法可以包括在孔的侧壁上形成包括电荷存储膜的记忆膜，并且还在电极间空间中形成记忆膜的至少一部分。

3. 发明申请

US20150372007A1 METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：制造半导体存储器件的方法
公开(公告)号：US20150372007A1
公开(公告)日：2015-12-24
申请号：US14731910
申请日：2015-06-05
申请人： Kabushiki Kaisha Toshiba
发明人： Junichi HASHIMOTO , Katsunori Yahashi , Daigo Ichinose , Tadashi Iguchi
IPC分类号： H01L27/115 , H01L21/02 , H01L21/311
CPC分类号： H01L27/11582 , H01L21/31144 , H01L27/11565 , H01L27/1157
摘要： According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a stacked body including a plurality of first layers and a plurality of second layers on a substrate. The method includes forming a first slit and a second slit simultaneously by dry-etching the stacked body. The first slit causes a part of the stacked body to have a comb-shaped pattern including a plurality of line parts isolated in a first direction and extending in a second direction. The second slit surrounds the comb-shaped pattern with a closed pattern. The method includes forming a hole in the line parts of the stacked body. The method includes forming a charge storage film and a semiconductor body in the hole.
摘要翻译：根据一个实施例，一种用于制造半导体存储器件的方法包括在衬底上形成包括多个第一层和多个第二层的层叠体。该方法包括通过干法蚀刻层叠体同时形成第一狭缝和第二狭缝。第一狭缝使得层叠体的一部分具有包括在第一方向上分离并沿第二方向延伸的多个线部分的梳状图案。第二个狭缝以闭合的图案围绕梳状图案。该方法包括在层叠体的线部上形成孔。该方法包括在孔中形成电荷存储膜和半导体本体。

4. 发明授权

US09159613B2 Non-volatile memory device, method for fabricating pattern on wafer and method for manufacturing non-volatile memory device using same 有权
标题翻译：非易失性存储器件，用于制造晶片上的图案的方法和使用其制造非易失性存储器件的方法
公开(公告)号：US09159613B2
公开(公告)日：2015-10-13
申请号：US14203853
申请日：2014-03-11
申请人： Kabushiki Kaisha Toshiba
发明人： Yoshihiro Akutsu , Masaru Kidoh , Tsuneo Uenaka , Tadashi Iguchi
IPC分类号： H01L21/337 , H01L21/8238 , H01L27/148 , H01L29/94 , H01L21/768 , H01L27/115
CPC分类号： H01L21/76877 , H01L27/11519 , H01L27/11529 , H01L27/11548 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11575 , H01L27/11582
摘要： According to an embodiment, a method for fabricating a pattern includes forming a mask covering a first layer, and a second layer selectively provided on the first layer, and forming a groove dividing the first layer and the second layer using the mask. The mask includes a first portion formed on a region of the first layer on a first side of the second layer, a second portion formed on a region of the first layer on a second side of the second layer opposite to the first side, first extending parts extending over the second layer from the first portion toward the second portion, and second extending parts extending over the second layer from the second portion toward the first portion. Each of the second extending parts is located between the first extending parts adjacent to each other.
摘要翻译：根据实施例，制造图案的方法包括形成覆盖第一层的掩模和选择性地设置在第一层上的第二层，以及使用掩模形成分割第一层和第二层的凹槽。掩模包括形成在第二层的第一侧的第一层的区域上的第一部分，形成在第二层的与第一侧相反的第二侧的第一层的区域上的第二部分，第一部分从第一部分向第二部分延伸到第二层上的部分，以及从第二部分向第一部分延伸到第二层上的第二延伸部分。每个第二延伸部分位于彼此相邻的第一延伸部分之间。

5. 发明授权

US08912089B2 Method for manufacturing a semiconductor device including a stacked body comprising pluralities of first and second metallic conductive layers 有权
标题翻译：一种半导体器件的制造方法，包括具有多个第一和第二金属导电层的层叠体
公开(公告)号：US08912089B2
公开(公告)日：2014-12-16
申请号：US13848294
申请日：2013-03-21
申请人： Kabushiki Kaisha Toshiba
发明人： Seiichi Omoto , Yoshihiro Uozumi , Tadashi Iguchi , Osamu Yamane , Kazuyuki Masukawa , Yoshihiro Yanai
IPC分类号： H01L21/4763 , H01L27/115 , H01L29/792 , H01L29/66 , H01L29/78 , H01L29/788
CPC分类号： H01L29/66666 , H01L27/11565 , H01L27/11575 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7827 , H01L29/7889 , H01L29/7926
摘要： According to one embodiment, a method for manufacturing a semiconductor device includes forming a stacked body on a substrate. The stacked body includes a plurality of first conductive layers including a metallic element as a main component and a plurality of second conductive layers including a metallic element as a main component provided respectively between the first conductive layers. The method includes making a hole to pierce the stacked body. The method includes making a slit to divide the stacked body. The method includes making a gap between the first conductive layers by removing the second conductive layers by etching via the slit or the hole. The method includes forming a memory film including a charge storage film at a side wall of the hole. The method includes forming a channel body on an inner side of the memory film inside the hole.
摘要翻译：根据一个实施例，一种用于制造半导体器件的方法包括在衬底上形成层叠体。所述层叠体包括多个第一导电层，所述第一导电层包含以金属元素为主要成分的多个第二导电层，以及分别设置在所述第一导电层之间的包含金属元素作为主要成分的多个第二导电层。该方法包括形成一个孔以刺穿层叠体。该方法包括制作狭缝以分开堆叠体。该方法包括通过经由狭缝或孔的蚀刻去除第二导电层来在第一导电层之间形成间隙。该方法包括在孔的侧壁形成包括电荷存储膜的记忆膜。该方法包括在孔内的记忆膜的内侧形成通道体。

6. 发明授权

US09570461B2 Method for manufacturing semiconductor memory device 有权
标题翻译：制造半导体存储器件的方法
公开(公告)号：US09570461B2
公开(公告)日：2017-02-14
申请号：US14731910
申请日：2015-06-05
申请人： Kabushiki Kaisha Toshiba
发明人： Junichi Hashimoto , Katsunori Yahashi , Daigo Ichinose , Tadashi Iguchi
IPC分类号： H01L21/336 , H01L27/115 , H01L21/311
CPC分类号： H01L27/11582 , H01L21/31144 , H01L27/11565 , H01L27/1157
摘要： According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a stacked body including a plurality of first layers and a plurality of second layers on a substrate. The method includes forming a first slit and a second slit simultaneously by dry-etching the stacked body. The first slit causes a part of the stacked body to have a comb-shaped pattern including a plurality of line parts isolated in a first direction and extending in a second direction. The second slit surrounds the comb-shaped pattern with a closed pattern. The method includes forming a hole in the line parts of the stacked body. The method includes forming a charge storage film and a semiconductor body in the hole.
摘要翻译：根据一个实施例，一种用于制造半导体存储器件的方法包括在衬底上形成包括多个第一层和多个第二层的层叠体。该方法包括通过干法蚀刻层叠体同时形成第一狭缝和第二狭缝。第一狭缝使得层叠体的一部分具有包括在第一方向上分离并沿第二方向延伸的多个线部分的梳状图案。第二个狭缝以闭合的图案围绕梳状图案。该方法包括在层叠体的线部上形成孔。该方法包括在孔中形成电荷存储膜和半导体本体。

7. 发明授权

US09548315B2 Nonvolatile semiconductor memory device, method of manufacturing the same, and method of measuring the same 有权
标题翻译：非易失性半导体存储器件及其制造方法及其测量方法
公开(公告)号：US09548315B2
公开(公告)日：2017-01-17
申请号：US14850422
申请日：2015-09-10
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Megumi Ishiduki , Murato Kawai , Tadashi Iguchi , Yoshihiro Yanai , Takuya Inatsuka , Yoichi Minemura , Takuya Mizutani
IPC分类号： H01L27/115 , H01L23/528 , H01L23/532 , H01L21/027 , H01L21/311 , H01L21/3213 , H01L21/768 , H01L21/66
CPC分类号： H01L27/11582 , H01L21/0273 , H01L21/0274 , H01L21/31144 , H01L21/32139 , H01L22/12 , H01L22/20 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575
摘要： A nonvolatile semiconductor memory device comprises: a memory cell region having a memory cell disposed therein; a peripheral region including a first stepped structure in which an end of a lower first layer is further from the memory cell region than is an end of an upper first layer; and a second stepped structure disposed on the first stepped structure, in which an end of a lower third layer is disposed further from the memory cell region than is an end of an upper third layer, a length in a second direction being shorter than a length in the second direction of the first layer or the second layer contacted by the second stepped structure, and a length in a third direction of the second stepped structure being shorter than a length in the third direction of the first layer or the second layer contacted by the second stepped structure.
摘要翻译：非易失性半导体存储器件包括：存储单元区域，其中设置有存储单元; 包括第一阶梯结构的周边区域，其中下第一层的一端比上一第一层的端部更远离存储单元区域; 以及设置在所述第一阶梯结构上的第二阶梯结构，其中下部第三层的端部比所述上部第三层的端部更远离所述存储单元区域设置，第二方向上的长度短于所述第三方向的长度在与第二阶梯结构接触的第一层或第二层的第二方向上，第二阶梯结构的第三方向上的长度比第一层或第二层的第三层的第三方向上的长度短第二级结构。

8. 发明申请

US20150243512A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20150243512A1
公开(公告)日：2015-08-27
申请号：US14291209
申请日：2014-05-30
申请人： Kabushiki Kaisha Toshiba
发明人： Kazuki KISHI , Tadashi Iguchi , Nozomi Kido
IPC分类号： H01L21/308 , H01L21/02
CPC分类号： H01L21/31144 , H01L21/308 , H01L21/76232 , H01L27/11582
摘要： In one embodiment, a method of manufacturing a semiconductor device includes forming a first mask layer on a workpiece layer. The method further includes forming a concave portion in the workpiece layer by first etching using the first mask layer. The method further includes forming a second mask layer on the workpiece layer in which the concave portion is formed. The method further includes processing the concave portion of the workpiece layer by second etching using the second mask layer.
摘要翻译：在一个实施例中，制造半导体器件的方法包括在工件层上形成第一掩模层。该方法还包括通过使用第一掩模层的第一蚀刻在工件层中形成凹部。该方法还包括在其上形成有凹部的工件层上形成第二掩模层。该方法还包括通过使用第二掩模层的第二蚀刻来处理工件层的凹部。

9. 发明申请

US20150061068A1 NON-VOLATILE MEMORY DEVICE, METHOD FOR FABRICATING PATTERN ON WAFER AND METHOD FOR MANUFACTURING NON-VOLATILE MEMORY DEVICE USING SAME 有权
标题翻译：非易失性存储器件，用于制造波形图案的方法和使用其制造非易失性存储器件的方法
公开(公告)号：US20150061068A1
公开(公告)日：2015-03-05
申请号：US14203853
申请日：2014-03-11
申请人： Kabushiki Kaisha Toshiba
发明人： Yoshihiro Akutsu , Masaru Kidoh , Tsuneo Uenaka , Tadashi Iguchi
IPC分类号： H01L21/768 , H01L23/535 , H01L27/10 , H01L21/308
CPC分类号： H01L21/76877 , H01L27/11519 , H01L27/11529 , H01L27/11548 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11575 , H01L27/11582
摘要： According to an embodiment, a method for fabricating a pattern includes forming a mask covering a first layer, and a second layer selectively provided on the first layer, and forming a groove dividing the first layer and the second layer using the mask. The mask includes a first portion formed on a region of the first layer on a first side of the second layer, a second portion formed on a region of the first layer on a second side of the second layer opposite to the first side, first extending parts extending over the second layer from the first portion toward the second portion, and second extending parts extending over the second layer from the second portion toward the first portion. Each of the second extending parts is located between the first extending parts adjacent to each other.
摘要翻译：根据实施例，制造图案的方法包括形成覆盖第一层的掩模和选择性地设置在第一层上的第二层，以及使用掩模形成分割第一层和第二层的凹槽。掩模包括形成在第二层的第一侧的第一层的区域上的第一部分，形成在第二层的与第一侧相反的第二侧上的第一层的区域上的第二部分，从第一部分向第二部分延伸到第二层上的部分，以及从第二部分向第一部分延伸到第二层上的第二延伸部分。每个第二延伸部分位于彼此相邻的第一延伸部分之间。

10. 发明申请

US20170213840A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 有权
公开(公告)号：US20170213840A1
公开(公告)日：2017-07-27
申请号：US15258774
申请日：2016-09-07
申请人： Kabushiki Kaisha Toshiba
发明人： Gaku Sudo , Masanobu Baba , Megumi Ishiduki , Tadashi Iguchi , Murato Kawai
IPC分类号： H01L27/115 , H01L21/28
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/11565 , H01L27/1157 , H01L27/11575 , H01L27/11582
摘要： According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a stacked body alternately stacked with a plurality of members and a plurality of intermediate bodies having materials different from materials of the plurality of members, processing an end portion of at least two layers of the plurality of members sequentially in a stacking direction of the stacked body, and forming a step-wise step stacked with the plurality of members and the plurality of intermediate bodies, forming a plurality of side wall films contacting the step and making the end portion of the plurality of members in a step-wise. The making the end portion of the plurality of members in a step-wise includes retreating a portion of the plurality of members, the portion separated from the plurality of side wall films and exposed from the stacked body.

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