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1. 发明授权

US06697553B2 Compact, low insertion loss, high yield arrayed waveguide grating 有权
标题翻译：紧凑，低插入损耗，高产量阵列波导光栅
公开(公告)号：US06697553B2
公开(公告)日：2004-02-24
申请号：US10077581
申请日：2002-02-15
申请人： Jyoti Kiron Bhardwaj , Robert James Brainard , David J. Chapman , Douglas E. Crafts , Zi-Wen Dong , David Dougherty , Erik W. Egan , James F. Farrell , Mark B. Farrelly , Niranjan Gopinathan , Kenzo Ishida , David K. Nakamoto , Thomas Thuan Nguyen , Suresh Ramalingam , Steven M. Swain , Sanjay M. Thekdi , Anantharaman Vaidyanathan , Hiroaki Yamada , Yingchao Yan
发明人： Jyoti Kiron Bhardwaj , Robert James Brainard , David J. Chapman , Douglas E. Crafts , Zi-Wen Dong , David Dougherty , Erik W. Egan , James F. Farrell , Mark B. Farrelly , Niranjan Gopinathan , Kenzo Ishida , David K. Nakamoto , Thomas Thuan Nguyen , Suresh Ramalingam , Steven M. Swain , Sanjay M. Thekdi , Anantharaman Vaidyanathan , Hiroaki Yamada , Yingchao Yan
IPC分类号： G02B634
CPC分类号： G02B6/12011 , G02B6/105 , G02B6/12 , G02B6/12016 , G02B6/12021 , G02B6/12026
摘要： A planar lightwave circuit includes an arrayed waveguide grating (AWG), with input and output waveguides, partially curved array waveguides with respective length differences, and planar waveguide regions for focusing optical energy between the input/output and array waveguides. Optimal waveguide widths and spacing along the planar waveguide region facets are disclosed, which are largely determinative of AWG size and optical performance. Also disclosed are optimal cross-sectional waveguide dimensions (e.g., width and height); modified index of refraction difference between the waveguide core and cladding regions; and optimal array waveguide lengths, path length differences, and free spectral range. These features, especially when combined with advanced fiber attachment, passivation and packaging techniques, result in high-yield, high-performance AWGs (both gaussian and flattop versions).
摘要翻译：平面光波电路包括阵列波导光栅（AWG），其具有输入和输出波导，具有相应长度差的部分弯曲阵列波导和用于在输入/输出和阵列波导之间聚焦光能的平面波导区域。公开了沿着平面波导区域面的最佳波导宽度和间距，其主要决定于AWG尺寸和光学性能。还公开了最佳横截面波导尺寸（例如，宽度和高度）; 波导芯和包层区之间的折射率差异; 和最佳阵列波导长度，路径长度差和自由光谱范围。这些特性，特别是结合先进的光纤附着，钝化和封装技术，可以获得高产出，高性能的AWG（高斯型和平板型）。

2. 发明授权

US06606425B1 Transfer molded packages with embedded thermal insulation 有权
标题翻译：具有嵌入式保温的转移成型包装
公开(公告)号：US06606425B1
公开(公告)日：2003-08-12
申请号：US10100277
申请日：2002-03-18
申请人： Douglas E. Crafts , Kenzo Ishida , David J. Chapman , Duane Cook , James F. Farrell , Suresh Ramalingam , Steven M. Swain
发明人： Douglas E. Crafts , Kenzo Ishida , David J. Chapman , Duane Cook , James F. Farrell , Suresh Ramalingam , Steven M. Swain
IPC分类号： G02B612
CPC分类号： G02B6/12026 , G02B6/4253 , G02B6/4273
摘要： An optical component package, in which a transfer molded layer of material (e.g., syntactic foam in one embodiment) is formed at least partially around, or entirely around, the optical component to provide structural and thermal insulation around the component. The optical component may be a planar lightwave circuit (PLC), with a protective passivation layer formed between the PLC and the layer of syntactic foam, to de-couple stresses and thermal transfer between the PLC and the layer of syntactic foam. Strengthening caps, fiber assemblies, and a heater may be provided with the PLC assembly, around which the layer of syntactic foam can also be formed. The protective passivation layer can also be formed between these structures and the syntactic foam; in one embodiment between at least two strengthening caps formed on opposing edges of the PLC. The disclosed package provides numerous structural, thermal and size benefits.
摘要翻译：一种光学部件封装，其中材料的转移模制层（例如，一个实施例中的复合泡沫）至少部分地围绕或完全围绕光学部件形成，以在部件周围提供结构和隔热。光学部件可以是平面光波电路（PLC），在PLC和复合泡沫层之间形成保护钝化层，以解除PLC和复合泡沫层之间的应力和热传递。可以提供加强盖，纤维组件和加热器，PLC组件也可以形成层压泡沫层。保护钝化层也可以在这些结构和复合泡沫之间形成; 在一个实施例中，在形成在PLC的相对边缘上的至少两个加强盖之间。所公开的封装提供了许多结构，热和尺寸的优点。

3. 发明授权

US06664511B2 Package for optical components 有权
标题翻译：光学元件封装
公开(公告)号：US06664511B2
公开(公告)日：2003-12-16
申请号：US10281876
申请日：2002-10-28
申请人： Douglas E. Crafts , James F. Farrell , Mark B. Farrelly , Suresh Ramalingam , Kenzo Ishida
发明人： Douglas E. Crafts , James F. Farrell , Mark B. Farrelly , Suresh Ramalingam , Kenzo Ishida
IPC分类号： H05B100
CPC分类号： G02B6/30 , G02B6/1203 , G02B6/36
摘要： A package for optical components includes an inner package enclosing the optical component, and an outer package enclosing the inner package. A heater may be disposed in the inner package proximate the optical component to control its temperature, and to maintain this temperature control, the outer package creates an isolated air pocket around the inner package, which thermally insulates the inner package from the outside environment. The outer package is formed of a material having low thermal conductivity, to promote this insulating function. This package is especially useful if the optical component comprises a planar light-wave circuit (PLC), e.g. an arrayed waveguide grating (AWG), which requires tight temperature control and structural integrity to maintain the integrity of the optical paths.
摘要翻译：用于光学部件的封装包括封装光学部件的内部封装以及封装内部封装的外部封装。加热器可以在靠近光学部件的内部包装件中设置以控制其温度，并且为了保持该温度控制，外部包装围绕内部包装形成隔离的空气袋，其将内部包装与外部环境热绝缘。外包装由具有低导热性的材料形成，以促进该绝缘功能。如果光学部件包括平面光波电路（PLC），例如，阵列波导光栅（AWG），其需要严格的温度控制和结构完整性来维持光路的完整性。

4. 发明授权

US06486440B1 Redundant package for optical components 有权
标题翻译：用于光学元件的冗余封装
公开(公告)号：US06486440B1
公开(公告)日：2002-11-26
申请号：US09901474
申请日：2001-07-09
申请人： Douglas E. Crafts , James F. Farrell , Mark B. Farrelly , Suresh Ramalingam
发明人： Douglas E. Crafts , James F. Farrell , Mark B. Farrelly , Suresh Ramalingam
IPC分类号： H05B100
CPC分类号： G02B6/30 , G02B6/1203 , G02B6/36
摘要： A redundant package for optical components includes an inner package enclosing the optical component, and an outer package enclosing the inner package. A heater may be disposed in the inner package proximate the optical component to control its temperature, and to maintain this temperature control, the outer package creates an isolated air pocket around the inner package which thermally insulates the inner package from the outside environment. The outer package is formed of a material having low thermal conductivity, to promote this insulating function. This package is especially useful if the optical component comprises a planar lightwave circuit (PLC), e.g., an arrayed waveguide grating (AWG), which requires tight temperature control and structural integrity to maintain the integrity of the optical paths.
摘要翻译：用于光学部件的冗余封装包括封装光学部件的内部封装以及封装内部封装的外部封装。加热器可以靠近光学部件设置在内部包装件中以控制其温度，并且为了保持该温度控制，外部包装围绕内部包装形成隔离的空气袋，其将内部包装与外部环境绝热。外包装由具有低导热性的材料形成，以促进该绝缘功能。如果光学组件包括平面光波电路（PLC），例如阵列波导光栅（AWG），则该封装是特别有用的，其需要严格的温度控制和结构完整性来维持光路的完整性。

5. 发明授权

US07066657B2 Optical subassembly 有权
标题翻译：光学组件
公开(公告)号：US07066657B2
公开(公告)日：2006-06-27
申请号：US09752881
申请日：2000-12-28
申请人： Venkatesan Murali , Douglas E. Crafts , Suresh Ramalingam , Brett M. Zaborsky , Siegfried B. Fleischer
发明人： Venkatesan Murali , Douglas E. Crafts , Suresh Ramalingam , Brett M. Zaborsky , Siegfried B. Fleischer
IPC分类号： G02B6/42 , G02B6/30
CPC分类号： G02B6/4246 , G02B6/4214 , G02B6/4292
摘要： An apparatus including a base having a first opening of a dimension suitable to pass a light emission therethrough, a first side wall coupled to the base and having a second opening of a dimension suitable to pass a light emission therethrough, a second side wall coupled to the base and having a reflective component thereon, and the base, the first side wall, and the second side wall define an interior chamber with the reflective component disposed in the interior chamber; and a fiber connector extending from an exterior of the first side wall adjacent the second opening. A method including powering a laser disposed in a substrate coupling a fiber optic cable to an optical subassembly; and aligning the optical assembly over the transceiver board to capture the emitted light from the laser in the fiber optic cable.
摘要翻译：一种装置，包括具有第一开口的基座，该第一开口的尺寸适于通过其中的光发射;第一侧壁，其耦合到所述基座并且具有适于使光发射通过的尺寸的第二开口;第二侧壁，所述底座并且在其上具有反射部件，并且所述基座，所述第一侧壁和所述第二侧壁限定内部腔室，所述反射部件设置在所述内部腔室中; 以及从邻近第二开口的第一侧壁的外部延伸的光纤连接器。一种方法，包括为将光纤电缆耦合到光学子组件的基板中的激光器供电; 并且将光学组件对准在收发器板上以捕获来自光纤电缆中的激光器的发射光。

6. 发明授权

US09508563B2 Methods for flip chip stacking 有权
标题翻译：倒装芯片堆叠方法
公开(公告)号：US09508563B2
公开(公告)日：2016-11-29
申请号：US13548029
申请日：2012-07-12
申请人： Woon-Seong Kwon , Suresh Ramalingam
发明人： Woon-Seong Kwon , Suresh Ramalingam
IPC分类号： H01L21/48 , H01L23/14 , H01L23/498 , H01L23/00 , H01L25/065
CPC分类号： H01L21/4853 , H01L23/147 , H01L23/49816 , H01L23/49827 , H01L24/75 , H01L24/81 , H01L24/97 , H01L25/0655 , H01L2224/131 , H01L2224/13147 , H01L2224/16235 , H01L2224/32225 , H01L2224/73204 , H01L2224/75744 , H01L2224/7598 , H01L2224/75983 , H01L2224/75987 , H01L2224/81005 , H01L2224/81191 , H01L2224/81815 , H01L2224/92125 , H01L2224/97 , H01L2924/14 , H01L2924/15311 , H01L2924/157 , H01L2924/3511 , H01L2924/014 , H01L2224/16225 , H01L2924/00012 , H01L2924/00 , H01L2224/81 , H01L2924/00014
摘要： A method for flip chip stacking includes forming a cavity wafer comprising a plurality of cavities and a pair of corner guides, placing a through-silicon-via (TSV) interposer with solder bumps coupled to a surface of the TSV interposer on the cavity wafer, such that the solder bumps are situated in the plurality of cavities and the TSV interposer is situated between the pair of corner guides, placing an integrated circuit (IC) die on another surface of the TSV interposer, such that the IC die, the TSV interposer, and the solder bumps form a stacked interposer unit, removing the stacked interposer unit from the cavity wafer, and bonding the solder bumps of the stacked interposer unit to an organic substrate such that the stacked interposer unit and the organic substrate form a flip chip.
摘要翻译：一种用于倒装芯片堆叠的方法包括：形成包括多个空腔的空腔晶片和一对角引导件，将具有耦合到腔晶片上的TSV插入器表面的焊料凸块放置穿通硅通孔（TSV）插入器，使得焊料凸块位于多个空腔中，并且TSV插入件位于一对拐角引导件之间，将集成电路（IC）管芯放置在TSV插入器的另一表面上，使得IC管芯，TSV插入器并且焊料凸起形成堆叠的插入单元，从空腔晶片去除堆叠的中介层单元，并且将堆叠的插入单元的焊料凸块接合到有机基板，使得堆叠的插入单元和有机基板形成倒装芯片。

7. 发明授权

US09236341B1 Through-silicon vias with metal system fill 有权
标题翻译：带有金属系统填充的硅通孔
公开(公告)号：US09236341B1
公开(公告)日：2016-01-12
申请号：US12868529
申请日：2010-08-25
申请人： Dong W. Kim , Myung-June Lee , Suresh Ramalingam
发明人： Dong W. Kim , Myung-June Lee , Suresh Ramalingam
IPC分类号： H01L23/58 , H01L23/522
CPC分类号： H01L23/5226 , H01L21/486 , H01L21/76898 , H01L23/147 , H01L23/49827 , H01L2224/16225 , H01L2924/15311
摘要： A silicon interposer includes a plurality of patterned metal layers formed on a silicon wafer portion and a plurality of through-silicon vias extending through the silicon wafer portion. The through-silicon vias have an interdiffusion conductive element.
摘要翻译：硅插入件包括形成在硅晶片部分上的多个图案化金属层和延伸穿过硅晶片部分的多个穿硅通孔。穿硅通孔具有相互扩散的导电元件。

8. 再颁专利

USRE44629E1 Process for assembling an integrated circuit package having a substrate vent hole 有权
标题翻译：用于组装具有基板通气孔的集成电路封装的工艺
公开(公告)号：USRE44629E1
公开(公告)日：2013-12-10
申请号：US11001714
申请日：2004-11-30
申请人： Suresh Ramalingam , Nagesh Vodrahalli , Michael J. Costello , Mun Leong Loke , Ravi V. Mahajan
发明人： Suresh Ramalingam , Nagesh Vodrahalli , Michael J. Costello , Mun Leong Loke , Ravi V. Mahajan
IPC分类号： H01K3/10
CPC分类号： H01L21/563 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/00014 , H01L2924/01077 , H01L2924/15151 , H01L2924/15311 , Y10T29/4913 , Y10T29/49146 , Y10T29/49163 , Y10T29/49165 , H01L2924/00 , H01L2224/0401
摘要： The present invention involves a method of providing an integrated circuit package having a substrate with a vent opening. The integrated circuit package includes a substrate having an opening and an integrated circuit mounted to the substrate. An underfill material is dispensed between the substrate and the integrated circuit.
摘要翻译：本发明涉及一种提供集成电路封装的方法，所述集成电路封装具有带通气孔的基板。集成电路封装包括具有开口的基板和安装到基板的集成电路。在基板和集成电路之间分配底部填充材料。

9. 发明授权

US06490166B1 Integrated circuit package having a substrate vent hole 有权
标题翻译：具有基板通气孔的集成电路封装
公开(公告)号：US06490166B1
公开(公告)日：2002-12-03
申请号：US09330373
申请日：1999-06-11
申请人： Suresh Ramalingam , Nagesh Vodrahalli , Michael J. Costello , Mun Leong Loke , Ravi V. Mahajan
发明人： Suresh Ramalingam , Nagesh Vodrahalli , Michael J. Costello , Mun Leong Loke , Ravi V. Mahajan
IPC分类号： H01L2100
CPC分类号： H01L21/563 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/00014 , H01L2924/01077 , H01L2924/15151 , H01L2924/15311 , Y10T29/4913 , Y10T29/49146 , Y10T29/49163 , Y10T29/49165 , H01L2924/00 , H01L2224/0401
摘要： The present invention involves a method of providing an integrated circuit package having a substrate with a vent opening. The integrated circuit package includes a substrate having an opening and an integrated circuit mounted to the substrate. An underfill material is dispensed between the substrate and the integrated circuit.
摘要翻译：本发明涉及一种提供集成电路封装的方法，所述集成电路封装具有带通气孔的基板。集成电路封装包括具有开口的基板和安装到基板的集成电路。在基板和集成电路之间分配底部填充材料。

10. 发明授权

US08618648B1 Methods for flip chip stacking 有权
标题翻译：倒装芯片堆叠方法
公开(公告)号：US08618648B1
公开(公告)日：2013-12-31
申请号：US13548041
申请日：2012-07-12
申请人： Woon-Seong Kwon , Suresh Ramalingam
发明人： Woon-Seong Kwon , Suresh Ramalingam
IPC分类号： H01L23/02 , H01L23/48 , H01L23/52 , H01L29/40 , H01L21/00
CPC分类号： H01L24/75 , H01L23/147 , H01L23/49827 , H01L24/81 , H01L24/97 , H01L2224/131 , H01L2224/13147 , H01L2224/16235 , H01L2224/75724 , H01L2224/75983 , H01L2224/81815 , H01L2224/95 , H01L2924/3511 , H01L2924/00014 , H01L2224/81 , H01L2924/014
摘要： A cavity wafer for flip chip stacking includes an electrostatic (ESC) chuck wafer with a plurality of cavities, and a bonding layer on a surface of the ESC chuck wafer. The bonding layer is configured to receive a through-silicon-via (TSV) interposer with solder bumps. The plurality of cavities are configured to receive the solder bumps at the TSV interposer. The bonding layer is configured to receive an electrostatic bias for bonding the ESC chuck wafer to the TSV interposer with the solder bumps.
摘要翻译：用于倒装芯片堆叠的空腔晶片包括具有多个空腔的静电（ESC）卡盘晶片和ESC卡盘晶片的表面上的结合层。接合层被配置为接收具有焊料凸块的穿硅通孔（TSV）插入器。多个空腔被配置为在TSV插入器处接收焊料凸块。接合层被配置为接收用于将ESC卡盘晶片与焊料凸块接合到TSV插入件的静电偏压。

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