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1. 发明申请

US20140035702A1 HYBRID FILTER INCLUDING LC- AND MEMS-BASED RESONATORS 审中-公开
标题翻译：混合滤波器，包括基于LC和MEMS的谐振器
公开(公告)号：US20140035702A1
公开(公告)日：2014-02-06
申请号：US13563252
申请日：2012-07-31
申请人： Justin Phelps Black , Philip Jason Stephanou , Jonghae Kim , Je-Hsiung Jeffrey Lan , Sang-June Park , Changhan Hobie Yun , Chi Shun Lo , Chengjie Zuo
发明人： Justin Phelps Black , Philip Jason Stephanou , Jonghae Kim , Je-Hsiung Jeffrey Lan , Sang-June Park , Changhan Hobie Yun , Chi Shun Lo , Chengjie Zuo
IPC分类号： H03H9/00 , H03H7/01
CPC分类号： H03H7/075 , H03H9/465 , H03H2007/006
摘要： This disclosure provides implementations of filters and filter topologies, circuits, structures, devices, apparatus, systems, and related processes. In one aspect, a device includes one or more LC resonant circuit stages. In some implementations, each LC stage includes an inductor and a capacitor. Each LC stage also has a corresponding resonant frequency. The one or more LC stages are arranged to produce an unmodified passband over a range of frequencies having a corresponding bandwidth. One or more microelectromechanical systems (MEMS) resonators are arranged with the one or more LC stages. The one or more MEMS resonators are arranged with the one or more LC stages so as to modify characteristics of the unmodified passband such that the hybrid filter produces a modified passband having a modified bandwidth and one or more other modified band characteristics.
摘要翻译：本公开提供了滤波器和滤波器拓扑，电路，结构，设备，装置，系统和相关过程的实现。在一个方面，器件包括一个或多个LC谐振电路级。在一些实现中，每个LC级包括电感器和电容器。每个LC级还具有相应的谐振频率。一个或多个LC级布置成在具有相应带宽的频率范围上产生未修改的通带。一个或多个微机电系统（MEMS）谐振器与一个或多个LC级布置。一个或多个MEMS谐振器被布置成具有一个或多个LC级，以便修改未修改的通带的特性，使得混合滤波器产生具有修改的带宽和一个或多个其它修改的频带特性的修改的通带。

2. 发明申请

US20130293337A1 HIGH QUALITY FACTOR PLANAR INDUCTORS 审中-公开
标题翻译：高质量因子平面电感器
公开(公告)号：US20130293337A1
公开(公告)日：2013-11-07
申请号：US13463583
申请日：2012-05-03
申请人： Chi Shun Lo , Wesley Nathaniel Allen , Jonghae Kim , Je-Hsiung Jeffrey Lan , Ravindra V. Shenoy , Justin Phelps Black , Chengjie Zuo , Changhan Hobie Yun
发明人： Chi Shun Lo , Wesley Nathaniel Allen , Jonghae Kim , Je-Hsiung Jeffrey Lan , Ravindra V. Shenoy , Justin Phelps Black , Chengjie Zuo , Changhan Hobie Yun
IPC分类号： H01F5/00 , H01F41/04
CPC分类号： H01F5/003 , H01F41/041 , Y10T29/4902
摘要： This disclosure provides systems, methods, and apparatus related to inductors. In one aspect, a planar inductor may include a substrate with a spacer in the shape of a planar spiral coil on a surface of the substrate. Disposed on the spacer may be a line of metal formed as a planar inductor in the shape of the planar spiral coil. The spacer may be between the line of metal and the surface of the substrate. The spacer may elevate the line of metal above the surface of the substrate.
摘要翻译：本公开提供了与电感器相关的系统，方法和装置。一方面，平面电感器可以包括在衬底的表面上具有平面螺旋线圈形状的间隔物的衬底。设置在间隔件上的金属线可以是形成为平面螺旋线圈形状的平面电感器的金属线。间隔物可以在金属线和基底的表面之间。间隔物可以将衬底上的金属线提升。

3. 发明申请

US20140028543A1 COMPLEX PASSIVE DESIGN WITH SPECIAL VIA IMPLEMENTATION 有权
标题翻译：复杂的被动设计，特别是通过实施
公开(公告)号：US20140028543A1
公开(公告)日：2014-01-30
申请号：US13562168
申请日：2012-07-30
申请人： Chi Shun Lo , Je-Hsiung Jeffrey Lan , Mario Francisco Velez , Robert Paul Mikulka , Chengjie Zuo , Changhan Hobie Yun , Jonghae Kim
发明人： Chi Shun Lo , Je-Hsiung Jeffrey Lan , Mario Francisco Velez , Robert Paul Mikulka , Chengjie Zuo , Changhan Hobie Yun , Jonghae Kim
IPC分类号： H01F5/00 , B05D5/12 , C25D5/02 , G06T1/00 , G06F3/01 , G06F1/16 , B05D3/10
CPC分类号： H01F17/0006 , G02B26/001 , H01F27/2804 , H01L23/5227 , H01L28/10 , H01L2924/00 , H01L2924/0002
摘要： This disclosure provides systems, methods and apparatus for vias in an integrated circuit structure such as a passive device. In one aspect, an integrated passive device includes a first conductive trace and a second conductive trace over the first conductive trace with an interlayer dielectric between a portion of the first conductive trace and the second conductive trace. One or more vias are provided within the interlayer dielectric to provide electrical connection between the first conductive trace and the second conductive trace. A width of the vias is greater than a width of at least one of the conductive traces.
摘要翻译：本公开提供了诸如无源器件的集成电路结构中的通孔的系统，方法和装置。一方面，集成无源器件包括在第一导电迹线上的第一导电迹线和第二导电迹线，在第一导电迹线的一部分和第二导电迹线之间具有层间电介质。在层间电介质中提供一个或多个通孔以提供第一导电迹线和第二导电迹线之间的电连接。通孔的宽度大于至少一个导电迹线的宽度。

4. 发明授权

US09001031B2 Complex passive design with special via implementation 有权
标题翻译：复杂的被动设计与特殊的通过实现
公开(公告)号：US09001031B2
公开(公告)日：2015-04-07
申请号：US13562168
申请日：2012-07-30
申请人： Chi Shun Lo , Je-Hsiung Jeffrey Lan , Mario Francisco Velez , Robert Paul Mikulka , Chengjie Zuo , Changhan Hobie Yun , Jonghae Kim
发明人： Chi Shun Lo , Je-Hsiung Jeffrey Lan , Mario Francisco Velez , Robert Paul Mikulka , Chengjie Zuo , Changhan Hobie Yun , Jonghae Kim
IPC分类号： G09G5/00 , H01B13/00 , H01F17/00 , H01F27/28 , H01L23/522 , H01L49/02 , G02B26/00
CPC分类号： H01F17/0006 , G02B26/001 , H01F27/2804 , H01L23/5227 , H01L28/10 , H01L2924/00 , H01L2924/0002
摘要： This disclosure provides systems, methods and apparatus for vias in an integrated circuit structure such as a passive device. In one aspect, an integrated passive device includes a first conductive trace and a second conductive trace over the first conductive trace with an interlayer dielectric between a portion of the first conductive trace and the second conductive trace. One or more vias are provided within the interlayer dielectric to provide electrical connection between the first conductive trace and the second conductive trace. A width of the vias is greater than a width of at least one of the conductive traces.
摘要翻译：本公开提供了诸如无源器件的集成电路结构中的通孔的系统，方法和装置。一方面，集成无源器件包括在第一导电迹线上的第一导电迹线和第二导电迹线，在第一导电迹线的一部分和第二导电迹线之间具有层间电介质。在层间电介质中提供一个或多个通孔以提供第一导电迹线和第二导电迹线之间的电连接。通孔的宽度大于至少一个导电迹线的宽度。

5. 发明授权

US08803648B2 Three-dimensional multilayer solenoid transformer 有权
标题翻译：三维多层螺线管变压器
公开(公告)号：US08803648B2
公开(公告)日：2014-08-12
申请号：US13463257
申请日：2012-05-03
申请人： Chi Shun Lo , Jonghae Kim , Chengjie Zuo , Changhan Hobie Yun
发明人： Chi Shun Lo , Jonghae Kim , Chengjie Zuo , Changhan Hobie Yun
IPC分类号： H01F5/00 , H01F27/28 , H01F27/29
CPC分类号： H05K3/465 , H01F27/2804 , H01F2017/002 , H01F2017/004
摘要： This disclosure provides implementations of inductors, transformers, and related processes. In one aspect, a device includes a substrate having first and second surfaces. A first inducting arrangement includes a first set of vias, a second set of vias, a first set of traces arranged over the first surface connecting the first and second vias, and a second set of traces arranged over the second surface connecting the first and second vias. A second inducting arrangement is inductively-coupled and interleaved with the first inducting arrangement and includes a third set of vias, a fourth set of vias, a third set of traces arranged over the first surface connecting the third and fourth vias, and a fourth set of traces arranged over the second surface connecting the third and fourth vias. One or more sets of dielectric layers insulate portions of the traces from one another.
摘要翻译：本公开提供了电感器，变压器和相关过程的实现。一方面，一种装置包括具有第一表面和第二表面的基底。第一感应装置包括第一组通孔，第二组通孔，布置在连接第一和第二通孔的第一表面上的第一组迹线，以及布置在第二表面上的第二组迹线，该第二组迹线连接第一和第二通孔通孔第二感应装置与第一感应装置电感耦合和交错，并且包括第三组通孔，第四组通孔，布置在连接第三和第四通孔的第一表面上的第三组迹线和第四组布置在连接第三和第四通孔的第二表面上的迹线。一组或多组电介质层将迹线的一部分彼此绝缘。

6. 发明授权

US08704428B2 Widening resonator bandwidth using mechanical loading 失效
标题翻译：使用机械负载扩大谐振器带宽
公开(公告)号：US08704428B2
公开(公告)日：2014-04-22
申请号：US13090790
申请日：2011-04-20
申请人： Changhan Hobie Yun , Chengjie Zuo , Chi Shun Lo , Sanghoon Joo , Jonghae Kim
发明人： Changhan Hobie Yun , Chengjie Zuo , Chi Shun Lo , Sanghoon Joo , Jonghae Kim
IPC分类号： H03H9/17
CPC分类号： H03H9/172 , G02B26/001 , H03H9/02062 , H03H9/02228 , H03H9/02338
摘要： This disclosure provides systems, apparatus and techniques by which electromechanical resonators are implemented. In one aspect, by mechanically loading the resonator body in specific ways, multiple resonance modes are created within the resonator body resulting in wider bandwidths.
摘要翻译：本公开提供了实现机电谐振器的系统，装置和技术。在一个方面，通过以特定方式机械负载谐振器本体，在谐振器本体内产生多个谐振模式，从而产生更宽的带宽。

7. 发明申请

US20130134838A1 PIEZOELECTRIC MEMS TRANSFORMER 审中-公开
标题翻译：压电MEMS变压器
公开(公告)号：US20130134838A1
公开(公告)日：2013-05-30
申请号：US13305293
申请日：2011-11-28
申请人： Changhan Hobie Yun , Chi Shun Lo , Chengjie Zuo , Jonghae Kim
发明人： Changhan Hobie Yun , Chi Shun Lo , Chengjie Zuo , Jonghae Kim
IPC分类号： H01L41/107 , H01L41/22
CPC分类号： H01L41/107 , H01L41/047 , H03H9/02228 , Y10T29/42
摘要： This disclosure provides implementations of electromechanical systems piezoelectric resonator transformers, devices, apparatus, systems, and related processes. In one aspect, a transformer includes a piezoelectric layer; a first conductive layer arranged over a first surface of the piezoelectric layer including a first set of electrodes and a second set of electrodes interdigitated with the first set. The transformer includes a second conductive layer arranged over a second surface including at least a third set of electrodes. In some implementations, the transformer includes a first port capable of receiving an input signal and to which the first set of electrodes are coupled, and a second port capable of being coupled to a load and of outputting an output signal, the second set of electrodes being coupled to the second port. Generally, a ratio of the number of electrodes of the second set to the first set characterizes a transformation ratio.
摘要翻译：本公开提供了机电系统压电谐振器变压器，装置，装置，系统和相关过程的实现。一方面，变压器包括压电层; 布置在压电层的第一表面上的第一导电层，包括第一组电极和与第一组交叉的第二组电极。变压器包括布置在包括至少第三组电极的第二表面上的第二导电层。在一些实施方式中，变压器包括能够接收输入信号并且第一组电极被耦合的第一端口和能够耦合到负载并输出输出信号的第二端口，第二组电极耦合到第二端口。通常，第二组的电极数与第一组的比例表示变换比。

8. 发明申请

US20130293336A1 THREE-DIMENSIONAL MULTILAYER SOLENOID TRANSFORMER 有权
标题翻译：三维多层电磁变压器
公开(公告)号：US20130293336A1
公开(公告)日：2013-11-07
申请号：US13463257
申请日：2012-05-03
申请人： Chi Shun Lo , Jonghae Kim , Chengjie Zuo , Changhan Hobie Yun
发明人： Chi Shun Lo , Jonghae Kim , Chengjie Zuo , Changhan Hobie Yun
IPC分类号： H01F5/00 , H01F41/00
CPC分类号： H05K3/465 , H01F27/2804 , H01F2017/002 , H01F2017/004
摘要： This disclosure provides implementations of inductors, transformers, and related processes. In one aspect, a device includes a substrate having first and second surfaces. A first inducting arrangement includes a first set of vias, a second set of vias, a first set of traces arranged over the first surface connecting the first and second vias, and a second set of traces arranged over the second surface connecting the first and second vias. A second inducting arrangement is inductively-coupled and interleaved with the first inducting arrangement and includes a third set of vias, a fourth set of vias, a third set of traces arranged over the first surface connecting the third and fourth vias, and a fourth set of traces arranged over the second surface connecting the third and fourth vias. One or more sets of dielectric layers insulate portions of the traces from one another.
摘要翻译：本公开提供了电感器，变压器和相关过程的实现。一方面，一种装置包括具有第一表面和第二表面的基底。第一感应装置包括第一组通孔，第二组通孔，布置在连接第一和第二通孔的第一表面上的第一组迹线，以及布置在第二表面上的第二组迹线，该第二组迹线连接第一和第二通孔通孔第二感应装置与第一感应装置电感耦合和交错，并且包括第三组通孔，第四组通孔，布置在连接第三和第四通孔的第一表面上的第三组迹线和第四组布置在连接第三和第四通孔的第二表面上的迹线。一组或多组电介质层将迹线的一部分彼此绝缘。

9. 发明申请

US20120268440A1 WIDENING RESONATOR BANDWIDTH USING MECHANICAL LOADING 失效
标题翻译：使用机械装载的宽带谐振器带宽
公开(公告)号：US20120268440A1
公开(公告)日：2012-10-25
申请号：US13090790
申请日：2011-04-20
申请人： Changhan Hobie Yun , Chengjie Zuo , Chi Shun Lo , Sanghoon Joo , Jonghae Kim
发明人： Changhan Hobie Yun , Chengjie Zuo , Chi Shun Lo , Sanghoon Joo , Jonghae Kim
IPC分类号： H03H9/17 , G09G3/00 , G06F3/038
CPC分类号： H03H9/172 , G02B26/001 , H03H9/02062 , H03H9/02228 , H03H9/02338
摘要： This disclosure provides systems, apparatus and techniques by which electromechanical resonators are implemented. In one aspect, by mechanically loading the resonator body in specific ways, multiple resonance modes are created within the resonator body resulting in wider bandwidths.
摘要翻译：本公开提供了实现机电谐振器的系统，装置和技术。在一个方面，通过以特定方式机械负载谐振器本体，在谐振器本体内产生多个谐振模式，从而产生更宽的带宽。

10. 发明申请

US20130120951A1 STACKED CMOS CHIPSET HAVING AN INSULATING LAYER AND A SECONDARY LAYER AND METHOD OF FORMING SAME 有权
标题翻译：具有绝缘层和二次层的堆叠CMOS芯片及其形成方法
公开(公告)号：US20130120951A1
公开(公告)日：2013-05-16
申请号：US13356717
申请日：2012-01-24
申请人： Chengjie Zuo , Changhan Yun , Sang-June Park , Chi Shun Lo , Mario F. Velez , Jonghae Kim
发明人： Chengjie Zuo , Changhan Yun , Sang-June Park , Chi Shun Lo , Mario F. Velez , Jonghae Kim
IPC分类号： H05K1/03 , H01L21/60 , H05K7/06 , H01L21/58
CPC分类号： H01L27/0688 , H01L2224/18
摘要： A chipset includes a sheet of glass, quartz or sapphire and a first wafer having at least one first circuit layer on a first side of a first substrate layer. The first wafer is connected to the sheet such that the at least one first circuit layer is located between the first substrate layer and the sheet. A second wafer having at least one second circuit layer on a first side of a second substrate layer is connected to the first substrate layer such that the at least one second circuit layer is located between the second substrate layer and the first substrate layer. Also a method of forming a chipset.
摘要翻译：芯片组包括玻璃板，石英或蓝宝石片，以及在第一基底层的第一面上具有至少一个第一电路层的第一晶片。第一晶片连接到片材，使得至少一个第一电路层位于第一基片层和片之间。具有在第二衬底层的第一侧上的至少一个第二电路层的第二晶片连接到第一衬底层，使得至少一个第二电路层位于第二衬底层和第一衬底层之间。还有一种形成芯片组的方法。

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