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    • 1. 发明授权
    • Dual function array feature for CMP process control and inspection
    • 用于CMP过程控制和检查的双功能阵列功能
    • US06929961B2
    • 2005-08-16
    • US10733980
    • 2003-12-10
    • Justin Jia-Jen HwuThomas L. Leong
    • Justin Jia-Jen HwuThomas L. Leong
    • H01L21/00H01L23/544
    • H01L22/34
    • CMP process control array groups are fabricated upon the surface of the wafer for viewing through an optical microscope. The array groups include a plurality of test arrays, where each array includes a plurality of projecting test features. Each of the projecting test features are formed with the same projecting height and have a hard upper surface layer, such as diamond-like-carbon (DLC). All of the projecting test features within an array are formed with the same diameter, and the diameter of projecting test features of a particular array differs from the diameter of projecting test features in another array. The diameters are chosen such that the DLC surface is removed in specifically designed time increments, such as 5 seconds, from array to array, where projecting test features with the DLC surface removed appear as bright white, while the arrays with test features that retain some DLC surface are significantly darker.
    • CMP工艺控制阵列组被制造在晶片的表面上,以通过光学显微镜观察。 阵列组包括多个测试阵列,其中每个阵列包括多个突出的测试特征。 每个突出的测试特征形成具有相同的突出高度并且具有硬的上表面层,例如类金刚石(DLC)。 阵列中的所有突出的测试特征形成为具有相同的直径,并且特定阵列的突出测试特征的直径与另一阵列中的突出测试特征的直径不同。 选择直径使得DLC表面以特定设计的时间增量(例如从阵列到阵列的5秒)去除,其中去除DLC表面的突出的测试特征显示为亮白色,而具有测试特征的阵列保留一些 DLC表面明显较暗。
    • 7. 发明授权
    • Method of fabricating thin film calibration features for electron/ion beam image based metrology
    • 制造电子/离子束图像测量的薄膜校准特征的方法
    • US07323350B2
    • 2008-01-29
    • US10957097
    • 2004-09-30
    • Sukhbir Singh DulayJustin Jia-Jen HwuThao John Pham
    • Sukhbir Singh DulayJustin Jia-Jen HwuThao John Pham
    • H01L21/00H01L23/58
    • G11B5/3173G11B5/3163
    • A method of making and using thin film calibration features is described. To fabricate a calibration standard according to the invention raised features are first formed from an electrically conductive material with a selected atomic number. A conformal thin film layer is deposited over the exposed sidewalls of the raised features. The sidewall material is selected to have a different atomic number and is preferably an nonconductive such as silicon dioxide or alumina. After the nonconductive material deposition, a controlled directional RIE process is used to remove the insulator layer deposited on the top and bottom surface of the lines and trenches. The remaining voids between the sidewalls of the raised features are filled with a conductive material. The wafer is then planarized with chemical mechanical planarization (CMP) to expose the nonconductive sidewall material on the surface. The nonconductive sidewall material will be fine lines embedded in conductive material.
    • 描述制造和使用薄膜校准特征的方法。 为了制造根据本发明的校准标准,首先由具有所选原子序数的导电材料形成凸起特征。 在凸起特征的暴露的侧壁上沉积保形薄膜层。 侧壁材料选择为具有不同的原子序数,并且优选为非导电性,例如二氧化硅或氧化铝。 在非导电材料沉积之后,使用受控的定向RIE工艺来去除沉积在线和沟槽的顶表面和底表面上的绝缘体层。 凸起特征的侧壁之间的剩余空隙填充有导电材料。 然后用化学机械平面化(CMP)对晶片进行平面化,以暴露表面上的非导电侧壁材料。 非导电侧壁材料将是嵌入导电材料中的细线。