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1. 发明申请

US20070123041A1 Apparatus and method for surface processing such as plasma processing 审中-公开
标题翻译：等离子体处理等表面处理装置及方法
公开(公告)号：US20070123041A1
公开(公告)日：2007-05-31
申请号：US10561243
申请日：2004-06-24
申请人： Junichiro Anzai , Yoshinori Nakano , Shinichi Kawasaki , Sumio Nakatake , Satoshi Mayumi , Eiji Miyamoto , Toshimasa Takeuchi
发明人： Junichiro Anzai , Yoshinori Nakano , Shinichi Kawasaki , Sumio Nakatake , Satoshi Mayumi , Eiji Miyamoto , Toshimasa Takeuchi
IPC分类号： H01L21/336 , H01L21/44 , C23C16/00
CPC分类号： H01L21/67069 , H01J37/32752
摘要： [PROBLEM TO BE SOLVED]In a surface processing apparatus for spraying a processing gas onto the surface of an object to be processed through a hole-row such as a slit, the surface of the object having a large area can effectively be processed even if the hole-row is short. [MEANS FOR SOLVING]A plurality of electrode plates 11, 12 are arranged, in side-by-side relation, on a processor 1 of a plasma surface processing apparatus M. A slit-like hole-row 10a is formed between the adjacent electrode plates, and a hole-row group 100 is constituted by the side-by-side arranged hole-rows 10a. The object W is moved along the extending direction of each slit 10a by a moving mechanism 4.
摘要翻译： [待解决的问题]在通过诸如狭缝的孔列将处理气体喷射到待处理物体的表面的表面处理设备中，具有大面积的物体的表面即使可以被有效地处理孔排很短。 [装置手段]多个电极板11,12并排设置在等离子体表面处理装置M的处理器1上。狭缝状的孔列10a形成在相邻的电极板和孔列组100由并排布置的孔排10a构成。物体W通过移动机构4沿着每个狭缝10a的延伸方向移动。

2. 发明申请

US20070242535A1 Semiconductor memory device and defect remedying method thereof 失效
标题翻译：半导体存储器件及其缺陷补救方法
公开(公告)号：US20070242535A1
公开(公告)日：2007-10-18
申请号：US11714867
申请日：2007-03-07
申请人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
发明人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
IPC分类号： G11C7/10
CPC分类号： H01L24/06 , G11C5/025 , G11C5/04 , G11C5/063 , G11C11/406 , G11C29/06 , G11C29/12005 , G11C29/12015 , G11C29/24 , G11C29/34 , G11C29/50 , G11C29/50012 , G11C29/70 , G11C29/80 , G11C29/804 , G11C29/832 , G11C29/844 , G11C2029/2602 , H01L24/05 , H01L24/45 , H01L24/48 , H01L27/0207 , H01L27/105 , H01L27/10897 , H01L27/11898 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/05624 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48624 , H01L2224/73215 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01021 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01037 , H01L2924/01038 , H01L2924/01039 , H01L2924/01041 , H01L2924/01043 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01054 , H01L2924/01055 , H01L2924/01058 , H01L2924/01059 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01083 , H01L2924/01084 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.
摘要翻译：形成在半导体芯片上的半导体存储器件包括第一存储器阵列，多个第二存储器阵列，第一电压发生器和第一焊盘。半导体芯片被分为第一，第二和第三矩形区域，第三矩形区域布置在第一矩形区域和第二矩形区域之间。第一存储器阵列形成在第一矩形区域中。第二存储器阵列形成在第二矩形区域中。电压发生器和第一接合焊盘布置在第三矩形区域中。第一接合焊盘布置在第一矩形区域和电压发生器之间，并且在电压发生器和第二存储器阵列之间没有布置接合焊盘。

3. 发明申请

US20060284497A1 DISK DRIVING APPARATUS 失效
标题翻译：磁盘驱动器
公开(公告)号：US20060284497A1
公开(公告)日：2006-12-21
申请号：US11425174
申请日：2006-06-20
申请人： Hitoshi Takaki , Hisakazu Motomochi , Eiji Miyamoto , Takuya Yamane
发明人： Hitoshi Takaki , Hisakazu Motomochi , Eiji Miyamoto , Takuya Yamane
IPC分类号： H02K5/24 , H02K7/00 , G11B17/04
CPC分类号： G11B17/028 , G11B19/2009 , H02K7/09
摘要： A magnet disposed on the top face of an extended part of a bearing holding member has a semicircle shape as the maximum shaper and is disposed in the same direction as the movement direction of a disk dray in the circumferential direction. By the pulling force in the axial direction between the magnet and a rotor holder, the shaft tilts at an angle different from the gravity direction or a direction opposite to the gravity direction.
摘要翻译：设置在轴承保持构件的延伸部的上表面上的磁体具有作为最大整形器的半圆形状，并且沿与圆周方向的圆盘方向相同的方向设置。通过磁体和转子保持架之间的轴向拉力，轴以与重力方向或与重力方向相反的方向不同的角度倾斜。

4. 发明申请

US20060022621A1 Brushless motor and disk drive device using the same 失效
标题翻译：无刷电机和磁盘驱动器使用相同
公开(公告)号：US20060022621A1
公开(公告)日：2006-02-02
申请号：US11194742
申请日：2005-08-02
申请人： Naoki Mine , Eiji Miyamoto
发明人： Naoki Mine , Eiji Miyamoto
IPC分类号： H02P7/08
CPC分类号： H02K29/08 , G11B19/26 , G11B19/28 , H02K29/10
摘要： A brushless motor according to the present invention provided with a recording disk in a rotational member and serving to rotate the recording disk together with the rotational member comprises a first position detecting means for detecting a rotational position of the rotational member, a second position detecting means for detecting a rotational position of the recording disk, wherein a mode for rotating the rotational member at a high speed by a detection signal of the first position detecting means and a mode for rotating the rotational member at a low speed by a detection signal of the second position detecting means are generated. Thereby, the two rotation states whose rotation speeds are different can be obtained in a simplified constitution.
摘要翻译：根据本发明的无刷电动机设置有旋转构件中的记录盘并用于使记录盘与旋转构件一起旋转包括用于检测旋转构件的旋转位置的第一位置检测装置，第二位置检测装置用于检测记录盘的旋转位置，其中通过第一位置检测装置的检测信号高速旋转旋转构件的模式以及通过第一位置检测装置的检测信号以低速旋转旋转构件的模式产生第二位置检测装置。由此，可以以简化的结构获得转速不同的两个旋转状态。

5. 发明授权

US06710013B1 Exhaust emission control catalyst structure 失效
标题翻译：废气排放控制催化剂结构
公开(公告)号：US06710013B1
公开(公告)日：2004-03-23
申请号：US09763779
申请日：2001-04-20
申请人： Yasuyoshi Kato , Kouichi Yokoyama , Eiji Miyamoto , Masatoshi Fujisawa
发明人： Yasuyoshi Kato , Kouichi Yokoyama , Eiji Miyamoto , Masatoshi Fujisawa
IPC分类号： B01J2300
CPC分类号： B01J21/063 , B01D53/8628 , B01D53/8631 , B01D53/8678 , B01D53/885 , B01D53/9413 , B01D53/9431 , B01D2255/20707 , B01D2255/20723 , B01D2255/20769 , B01D2255/20776 , B01D2255/9207 , B01J19/32 , B01J23/22 , B01J23/24 , B01J35/02 , B01J35/04 , B01J2219/3221 , B01J2219/32213 , B01J2219/32237 , B01J2219/32262 , B01J2219/32286 , B01J2219/32408 , B01J2219/32425 , B01J2219/32441 , B01J2219/32466 , B01J2219/326 , F01N3/281 , F01N3/2814 , F01N3/2821 , F01N2330/02 , F01N2330/06 , F01N2330/12 , F01N2330/321 , F01N2330/323 , F01N2330/324 , F01N2330/38
摘要： Provided is a catalyst structure used for purifying an exhaust gas; to be disposed in an exhaust gas flow passage; preferable for obtaining a highly efficient and compact exhaust gas purifying apparatus; and produced by alternately stacking platelike catalysts 1, and gas dispersing members composed of netlike products 7 having many holes passing from the front surface to the back surface thereof, or linear, belt-shaped, or rodlike materials of a metal, ceramic, or glass to disturb the flow of an exhaust gas in a flow passage of the gas thereby to promote contact of the gas to be treated with the catalyst.
摘要翻译：提供了用于净化废气的催化剂结构; 设置在排气流路中; 优选用于获得高效且紧凑的废气净化装置; 并且通过交替层叠的催化剂1和由具有从其前表面延伸到其后表面的许多孔的网状产品7或由金属，陶瓷或玻璃的直线形，带状或棒状材料组成的气体分散构件来产生干扰气体的流路中的排气的流动，从而促进被处理气体与催化剂的接触。

6. 发明授权

US6160744A Semiconductor memory device and defect remedying method thereof 有权
公开(公告)号：US6160744A
公开(公告)日：2000-12-12
申请号：US361203
申请日：1999-07-27
申请人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
发明人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
IPC分类号： G11C5/00 , G11C5/02 , G11C5/06 , G11C11/34 , G11C11/406 , H01L23/485 , G11C13/00
CPC分类号： G11C5/025 , G11C5/063 , G11C11/406 , H01L24/05 , H01L24/06 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48599 , H01L2224/73215 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/0101 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01021 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01037 , H01L2924/01038 , H01L2924/01039 , H01L2924/01041 , H01L2924/01043 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01054 , H01L2924/01055 , H01L2924/01058 , H01L2924/01059 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01083 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/85399 , H01L2224/05599
摘要： Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

7. 发明授权

US5602771A Semiconductor memory device and defect remedying method thereof 失效
标题翻译：半导体存储器件及其缺陷补救方法
公开(公告)号：US5602771A
公开(公告)日：1997-02-11
申请号：US159621
申请日：1993-12-01
申请人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
发明人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
IPC分类号： G11C5/00 , G11C5/02 , G11C5/06 , G11C11/34 , G11C11/406 , H01L23/485
CPC分类号： G11C5/025 , G11C11/406 , G11C5/063 , H01L24/05 , H01L24/06 , H01L24/48 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48599 , H01L2224/73215 , H01L24/45 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/0101 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01021 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01033 , H01L2924/01037 , H01L2924/01038 , H01L2924/01039 , H01L2924/01041 , H01L2924/01043 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01054 , H01L2924/01055 , H01L2924/01058 , H01L2924/01059 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/01087 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025
摘要： Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.
摘要翻译：这里公开了一种半导体存储器件，其中外围电路布置在由纵向中心部分和横向中心部分组成的半导体芯片的交叉区域中，并且其中存储器阵列布置在由交叉区域。由于外围电路布置在芯片的中心部分的这种结构，最长的信号传输路径可以缩短到芯片尺寸的大约一半，以加快DRAM的大容量。

8. 发明授权

US5332922A Multi-chip semiconductor package 失效
标题翻译：多芯片半导体封装
公开(公告)号：US5332922A
公开(公告)日：1994-07-26
申请号：US691985
申请日：1991-04-26
申请人： Satoshi Oguchi , Masamichi Ishihara , Kazuya Ito , Gen Murakami , Ichiro Anjoh , Toshiyuki Sakuta , Yasunori Yamaguchi , Yasuhiro Kasama , Tetsu Udagawa , Eiji Miyamoto , Youichi Matsuno , Hiroshi Satoh , Atsusi Nozoe
发明人： Satoshi Oguchi , Masamichi Ishihara , Kazuya Ito , Gen Murakami , Ichiro Anjoh , Toshiyuki Sakuta , Yasunori Yamaguchi , Yasuhiro Kasama , Tetsu Udagawa , Eiji Miyamoto , Youichi Matsuno , Hiroshi Satoh , Atsusi Nozoe
IPC分类号： G11C5/00 , H01L23/495 , H01L25/065 , H01L23/16 , H01L23/48
CPC分类号： H01L24/06 , G11C5/00 , G11C5/02 , G11C5/06 , H01L23/4951 , H01L23/49537 , H01L23/49575 , H01L25/0652 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4554 , H01L2224/4569 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L2224/49175 , H01L2224/73215 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01043 , H01L2924/01047 , H01L2924/01055 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181
摘要： A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Each chip is bonded with an associated lead frame and each lead frame is disposed as plural lead frame conductors contacting mutually lead frame conductors associated with similarly function bonding pads, i.e. external terminals of the chips, of the other one of the pair of chips. Ones or plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.
摘要翻译：一对DRAM芯片1A和1B通过诸如引线框架之间的布线装置彼此相对地安装，引线框架与外部端子3B基本上成一体。然后，这些DRAM芯片和引线框架通过常规的引线键合方法连接在一起。每个芯片与相关联的引线框架结合，并且每个引线框架被设置为与所述一对芯片中的另一个芯片的类似功能键合焊盘（即，芯片的外部端子）相关联的互相引线框架导体的多个引线框架导体。堆叠这些连接的DRAM芯片和引线框架的一对或多对，并且引线框架的相应引线共同连接以形成层叠体。这样安装的多个DRAM芯片根据预定的芯片选择信号选择性地被激活。此外，通过利用上述芯片安装方法，能够正常部分正常工作的部分DRAM芯片组合在一起，以构成单个DRAM封装。

9. 发明授权

US4985869A Semiconductor memory device with an improved substrate back-bias arrangement 失效
标题翻译：具有改进的衬底背偏置布置的半导体存储器件
公开(公告)号：US4985869A
公开(公告)日：1991-01-15
申请号：US375492
申请日：1989-07-05
申请人： Eiji Miyamoto
发明人： Eiji Miyamoto
IPC分类号： G05F3/20 , G11C11/4074
CPC分类号： G11C11/4074 , G05F3/205
摘要： A substrate back bias voltage generator of a dynamic type RAM is provided with a first voltage generator having a relatively large current supply capacity, a second voltage generator having a relatively small current supply capacity, and a substrate back bias voltage detecting circuit for controlling operation of the first voltage generator. For example, when the dynamic type RAM is in a CAS before RAS refresh mode, the operation of the first voltage generator is limited selectively, and the operation of the second voltage generator and the substrate back bias voltage detecting circuit is stopped selectively.
摘要翻译：具有动态型RAM的基板背偏置电压发生器具有：具有较大的电流供应能力的第一电压发生器，具有相对小的电流供应能力的第二电压发生器，以及用于控制运行的基板背偏置电压检测电路第一电压发生器。例如，当动态型RAM处于＆upbar＆C before＆upbar＆R refresh模式时，选择性地限制第一电压发生器的操作，并且选择性地停止第二电压发生器和衬底背偏置电压检测电路的操作。

10. 发明申请

US20130152782A1 METHOD AND DEVICE FOR TREATING EXHAUST GAS CONTAINING CARBON DIOXIDE 有权
标题翻译：用于处理含二氧化碳的排气的方法和装置
公开(公告)号：US20130152782A1
公开(公告)日：2013-06-20
申请号：US13819888
申请日：2011-08-29
申请人： Koichi Yokoyama , Shigehito Takamoto , Eiji Miyamoto , Naoki Oda
发明人： Koichi Yokoyama , Shigehito Takamoto , Eiji Miyamoto , Naoki Oda
IPC分类号： B01D53/14
CPC分类号： B01D53/1412 , B01D53/1475 , B01D53/1493 , B01D2252/20405 , B01D2252/20426 , B01D2252/20484 , B01D2252/60 , B01D2252/604 , Y02A50/2342 , Y02C10/06
摘要： An object of the present invention is to provide a method for treating an exhaust gas containing CO2, that can adjust the concentration of an oxidation inhibitor in an absorbent to the concentration enough to inhibit oxidation, without measuring the concentration of the oxidation inhibitor in an alkanolamine contained in a CO2 absorbent. Disclosed are a method and a device for adjusting the compositional ratio of an absorbent, in which absorption and release of carbon dioxide are performed by adding an oxidation inhibitor to an alkanolamine absorbent when the sum of the concentrations of ammonia and an alkylamine in an absorber column outlet gas of a CO2 absorption equipment.
摘要翻译：本发明的目的是提供一种处理含有CO 2的废气的方法，其可以将吸收剂中的氧化抑制剂的浓度调节至足以抑制氧化的浓度，而不测量烷醇胺中的氧化抑制剂的浓度包含在二氧化碳吸收剂中。公开了一种用于调节吸收剂的组成比的方法和装置，其中当吸收塔中的氨和烷基胺的浓度之和时，通过向烷醇胺吸收剂中加入氧化抑制剂来进行二氧化碳的吸收和释放二氧化碳吸收设备的出气。

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