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1. 发明授权

US08569252B2 Nucleolin specific aptamer and use thereof 有权
标题翻译：核仁特异性适体及其用途
公开(公告)号：US08569252B2
公开(公告)日：2013-10-29
申请号：US12759813
申请日：2010-04-14
申请人： Jung-Hwan Lee , Soon-Hag Kim , Mi-Jin Kwon , Hyun-Gu Kang , Sung-Ho Ryu , Jong-In Kim , Youn-Dong Kim , Young-Chan Chae , Sung-Key Jang , Jong-Hun Im , Sun-Hak Lee , Hye-Jung Lee , Eun-Jung Jang , Ki-Seok Kim
发明人： Jung-Hwan Lee , Soon-Hag Kim , Mi-Jin Kwon , Hyun-Gu Kang , Sung-Ho Ryu , Jong-In Kim , Youn-Dong Kim , Young-Chan Chae , Sung-Key Jang , Jong-Hun Im , Sun-Hak Lee , Hye-Jung Lee , Eun-Jung Jang , Ki-Seok Kim
IPC分类号： C12N15/11
CPC分类号： G01N33/57496 , C12N15/115 , C12N2310/16 , C12N2310/335
摘要： Improved G-rich oligonucleotide (GRO) aptamers specific to nucleolin, a method of preparing the aptamers, and a use of the aptamers for diagnosing and/or treating a nucleolin-associated disease, are provided.
摘要翻译：提供了改进的对核仁林特异性的富G寡核苷酸（GRO）适配体，制备适体的方法，以及适配体用于诊断和/或治疗核仁素相关疾病的用途。

2. 发明授权

US08124756B2 Method of preparing 5′-amino-linker oligonucleotides derivatives and analogous 5′-labeled-linker oligonucleotides therefrom 有权
标题翻译：从其中制备5'-氨基 - 连接寡核苷酸衍生物和类似的5'-标记 - 接头寡核苷酸的方法
公开(公告)号：US08124756B2
公开(公告)日：2012-02-28
申请号：US12559666
申请日：2009-09-15
申请人： Jung-Hwan Lee , Hyun-Gu Kang , Sung-Ho Ryu , Jong-In Kim , Sun-Hak Lee , Hye-Jung Lee , Eun-Jung Jang
发明人： Jung-Hwan Lee , Hyun-Gu Kang , Sung-Ho Ryu , Jong-In Kim , Sun-Hak Lee , Hye-Jung Lee , Eun-Jung Jang
IPC分类号： C07H21/00
CPC分类号： C07H21/04 , Y02P20/55
摘要： A method for preparing amino linker oligonucleotides is provided. More specifically, a method of preparing 5′-amino-linker oligonucleotides comprising the steps of: introducing an amino linker having a protecting group into the 5′ terminus of an oligonucleotide; and removing the protecting group from the amino linker oligonucleotide by contacting with acetic acid and 2,2,2-trifluoroethanol is provided. The amino protecting group is efficiently removed from the amino linker oligonucleotides, and thereby achieving a high yield of the amino linker oligonucleotides.
摘要翻译：提供了制备氨基接头寡核苷酸的方法。更具体地说，制备5'-氨基连接寡核苷酸的方法包括以下步骤：将具有保护基的氨基接头引入寡核苷酸的5'末端; 并通过与乙酸和2,2,2-三氟乙醇接触，从氨基接头寡核苷酸中除去保护基。从氨基接头寡核苷酸有效地除去氨基保护基，从而达到高产量的氨基接头寡核苷酸。

3. 发明申请

US20100093994A1 REPARATION METHOD OF AN AMINO LINKER OLIGONUCLEOTIDES AND LABELED-LINKER OLIGONUCLEOTIDE THEREFROM 有权
标题翻译：氨基连接子寡核苷酸和标记的寡核苷酸寡核苷酸的重复方法
公开(公告)号：US20100093994A1
公开(公告)日：2010-04-15
申请号：US12559666
申请日：2009-09-15
申请人： Jung-Hwan LEE , Hyun-Gu Kang , Sung-Ho Ryu , Jong-In Kim , Sun-Hak Lee , Hye-Jung Lee , Eun-Jung Jang
发明人： Jung-Hwan LEE , Hyun-Gu Kang , Sung-Ho Ryu , Jong-In Kim , Sun-Hak Lee , Hye-Jung Lee , Eun-Jung Jang
IPC分类号： C08B37/00
CPC分类号： C07H21/04 , Y02P20/55
摘要： A method for preparing amino linker oligonucleotides is provided, wherein an amino protecting group is efficiently removed from the amino linker oligonucleotides protected by the protecting group, and thereby achieving a high yield of the amino linker oligonucleotides.
摘要翻译：提供了制备氨基接头寡核苷酸的方法，其中氨基保护基被有效地从保护基保护的氨基接头寡核苷酸中除去，从而达到高产量的氨基接头寡核苷酸。

4. 发明授权

US06853040B2 MOS transistor and fabrication method thereof 失效
标题翻译： MOS晶体管及其制造方法
公开(公告)号：US06853040B2
公开(公告)日：2005-02-08
申请号：US10300293
申请日：2002-11-20
申请人： Kyung-Oun Jang , Sun-Hak Lee
发明人： Kyung-Oun Jang , Sun-Hak Lee
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/78 , H01L29/76
CPC分类号： H01L29/7816 , H01L21/8238 , H01L27/092 , H01L29/0847 , H01L29/0878 , H01L29/1045 , H01L29/1083 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7801 , H01L29/7835
摘要： A CMOS transistor is provided having a relatively high breakdown voltage. The CMOS transistor includes an N-type epitaxial layer on a P-type substrate. Between the substrate and epitaxial layer are a heavily doped N-type buried layer and a heavily doped P-type base layer. An N-type sink region is proximate the edge of the NMOS region, and twin wells are in the area surrounded with the sink region. N+ source and drain regions are formed in respective wells. As the sink region is interposed between the drain and isolation regions, a breakdown occurs between the sink and isolation regions when a high voltage is applied. Twin wells are also formed in the PMOS region. P+ source and drain regions are formed in respective wells. As the N-type well surrounds the source and bulk regions, a breakdown occurs between a buried region and the isolation region when a high voltage is applied.
摘要翻译：提供具有相对高的击穿电压的CMOS晶体管。 CMOS晶体管包括在P型衬底上的N型外延层。在衬底和外延层之间是重掺杂的N型掩埋层和重掺杂的P型基极层。 N型接收区域靠近NMOS区域的边缘，并且在阱区域包围的区域中是双阱。在各孔中形成N +源极和漏极区。当漏极区域插入在漏极和隔离区域之间时，当施加高电压时，在漏极和隔离区域之间发生击穿。在PMOS区域也形成双阱。在各个孔中形成P +源极和漏极区。当N型阱围绕源区和体区时，当施加高电压时，在掩埋区和隔离区之间发生击穿。

5. 发明申请

US20100207204A1 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20100207204A1
公开(公告)日：2010-08-19
申请号：US12656671
申请日：2010-02-12
申请人： Young-Mok Kim , Sun-Hak Lee , Tae-Cheol Lee , Yong-Sang Jeong
发明人： Young-Mok Kim , Sun-Hak Lee , Tae-Cheol Lee , Yong-Sang Jeong
IPC分类号： H01L29/78
CPC分类号： H01L29/4236 , H01L21/823456 , H01L21/823462 , H01L29/1037 , H01L29/7834
摘要： A semiconductor device comprises a recessed trench in a substrate, a gate insulating layer including a first portion and a second portion, the first portion having a first thickness and covering lower portions of sidewalls of the recessed trench and a bottom surface of the recessed trench, and the second portion having a second thickness and covering upper portions of the sidewalls of the recessed trench, the second thickness being greater than the first thickness, a gate electrode filling the recessed trench, a first impurity region having a first concentration and disposed at opposing sides of the gate electrode, and a second impurity region having a second concentration greater than the first concentration and disposed on the first impurity region to correspond to the second portion of the gate insulating layer.
摘要翻译：半导体器件包括衬底中的凹槽，栅极绝缘层包括第一部分和第二部分，第一部分具有第一厚度并覆盖凹槽的侧壁的下部和凹槽的底表面，并且所述第二部分具有第二厚度并且覆盖所述凹槽的侧壁的上部，所述第二厚度大于所述第一厚度，填充所述凹陷沟槽的栅电极，具有第一浓度的第一杂质区域并且设置在相对的位置栅极电极的侧面，以及具有大于第一浓度的第二浓度的第二杂质区域，并且设置在第一杂质区域上以对应于栅极绝缘层的第二部分。

6. 发明授权

US07618854B2 High frequency MOS transistor, method of forming the same, and method of manufacturing a semiconductor device including the same 有权
标题翻译：高频MOS晶体管，其形成方法以及制造其的半导体器件的制造方法
公开(公告)号：US07618854B2
公开(公告)日：2009-11-17
申请号：US12032377
申请日：2008-02-15
申请人： Sun-Hak Lee
发明人： Sun-Hak Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L21/823807 , H01L21/823814 , H01L27/0922 , H01L29/66659 , H01L29/7835
摘要： In a high frequency LDMOS transistor, a gate structure is formed on a substrate. A drain, doped with first type impurities at a first concentration, is formed on the substrate spaced apart from the gate structure. A buffer well, doped with the first type impurities at a second concentration lower than the first concentration, surrounds side and lower portions of the drain. A lightly doped drain, doped with the first type impurities at a third concentration lower than the second concentration, is formed between the buffer well and the gate structure. A source, doped with the first type impurities at the first concentration, is formed on the substrate adjacent to the gate structure and opposite to the drain with respect to the gate structure. Accordingly, an on-resistance decreases while a breakdown voltage increases in the LDMOS transistor without increasing a capacitance between the gate structure and the drain.
摘要翻译：在高频LDMOS晶体管中，在衬底上形成栅极结构。在与栅极结构间隔开的衬底上形成以第一浓度掺杂第一类型杂质的漏极。掺杂有低于第一浓度的第二浓度的第一种杂质的缓冲阱包围漏极的侧部和下部。在缓冲阱和栅极结构之间形成掺杂有低于第二浓度的第三浓度的第一种杂质的轻掺杂漏极。掺杂有第一浓度的第一类型杂质的源极相对于栅极结构形成在与栅极结构相邻并且与漏极相对的衬底上。因此，在不增加栅极结构和漏极之间的电容的情况下，导通电阻随着LDMOS晶体管中的击穿电压增加而减小。

7. 发明授权

US5913114A Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US5913114A
公开(公告)日：1999-06-15
申请号：US7534
申请日：1998-01-15
申请人： Sun-Hak Lee , Chang-Ki Jeon , Cheol-Joong Kim
发明人： Sun-Hak Lee , Chang-Ki Jeon , Cheol-Joong Kim
IPC分类号： H01L27/06 , H01L21/8249 , H01L21/8238
CPC分类号： H01L29/66712 , H01L21/8249 , H01L29/7809 , H01L29/42368
摘要： A semiconductor device, and a method of manufacturing the same, containing a high voltage DMOS transistor, a low voltage CMOS transistor, and a bipolar transistor in a single substrate. The steps include forming an isolation layer within the substrate in an isolation region between each of a DMOS region, a CMOS region, or a bipolar region. A first oxide layer of variable thickness is formed on the substrate, a thick second oxide layer is formed on the isolation layer, and a polysilicon layer is formed on both oxide layers. The polysilicon layer is patterned to form gate patterns on the first oxide layer and resistive patterns on the second oxide layer. The gate pattern is then doped but the resistive pattern is undoped. The thickness of the first oxide layer in the DMOS region is greater than the thickness of the first oxide layer in the CMOS region.
摘要翻译：在单个基板中包含高电压DMOS晶体管，低电压CMOS晶体管和双极晶体管的半导体器件及其制造方法。这些步骤包括在DMOS区域，CMOS区域或双极区域中的每一个之间的隔离区域内在衬底内形成隔离层。在衬底上形成可变厚度的第一氧化物层，在隔离层上形成厚的第二氧化物层，并且在两个氧化物层上形成多晶硅层。图案化多晶硅层以在第一氧化物层上形成栅极图案，并在第二氧化物层上形成电阻图案。然后掺杂栅极图案，但是电阻图案是未掺杂的。 DMOS区域中的第一氧化物层的厚度大于CMOS区域中第一氧化物层的厚度。

8. 发明申请

US20060011981A1 High frequency MOS transistor, method of forming the same, and method of manufacturing a semiconductor device including the same 审中-公开
公开(公告)号：US20060011981A1
公开(公告)日：2006-01-19
申请号：US11181395
申请日：2005-07-14
申请人： Sun-Hak Lee
发明人： Sun-Hak Lee
IPC分类号： H01L29/78 , H01L21/8238 , H01L21/336
CPC分类号： H01L29/0847 , H01L21/823807 , H01L21/823814 , H01L27/0922 , H01L29/66659 , H01L29/7835
摘要： In a high frequency LDMOS transistor, a gate structure is formed on a substrate. A drain, doped with first type impurities at a first concentration, is formed on the substrate spaced apart from the gate structure. A buffer well, doped with the first type impurities at a second concentration lower than the first concentration, surrounds side and lower portions of the drain. A lightly doped drain, doped with the first type impurities at a third concentration lower than the second concentration, is formed between the buffer well and the gate structure. A source, doped with the first type impurities at the first concentration, is formed on the substrate adjacent to the gate structure and opposite to the drain with respect to the gate structure. Accordingly, an on-resistance decreases while a breakdown voltage increases in the LDMOS transistor without increasing a capacitance between the gate structure and the drain.

9. 发明授权

US06507080B2 MOS transistor and fabrication method thereof 有权
标题翻译： MOS晶体管及其制造方法
公开(公告)号：US06507080B2
公开(公告)日：2003-01-14
申请号：US09761902
申请日：2001-01-17
申请人： Kyung-Oun Jang , Sun-Hak Lee
发明人： Kyung-Oun Jang , Sun-Hak Lee
IPC分类号： H01L2972
CPC分类号： H01L29/7816 , H01L21/8238 , H01L27/092 , H01L29/0847 , H01L29/0878 , H01L29/1045 , H01L29/1083 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7801 , H01L29/7835
摘要： A CMOS transistor is provided having a relatively high breakdown voltage. The CMOS transistor includes an N-type epitaxial layer on a P-type substrate. Between the substrate and epitaxial layer are a heavily doped N-type buried layer and a heavily doped P-type base layer. An N-type sink region is proximatethe edge of the NMOS region, and twin wells are in the area surrounded with the sink region. N+ source and drain regions are formed in respective wells. As the sink region is interposed between the drain and isolation regions, a breakdown occurs between the sink and isolation regions when a high voltage is applied. Twin wells are also formed in the PMOS region P+ source and drain regions are formed in respective wells. As the N-type well surrounds the source and bulk regions, a breakdown occurs between a buried region and the isolation region when a high voltage is applied.
摘要翻译：提供具有相对高的击穿电压的CMOS晶体管。 CMOS晶体管包括在P型衬底上的N型外延层。在衬底和外延层之间是重掺杂的N型掩埋层和重掺杂的P型基极层。 N型接收区靠近NMOS区域的边缘，并且双阱位于被宿区域包围的区域中。在各孔中形成N +源极和漏极区。当漏极区域插入在漏极和隔离区域之间时，当施加高电压时，在漏极和隔离区域之间发生击穿。双阱也形成在PMOS区P +源极和漏极区形成在相应的阱中。当N型阱围绕源区和体区时，当施加高电压时，在掩埋区和隔离区之间发生击穿。

10. 发明授权

US06194760B1 Double-diffused MOS transistor and method of fabricating the same 有权
标题翻译：双扩散MOS晶体管及其制造方法
公开(公告)号：US06194760B1
公开(公告)日：2001-02-27
申请号：US09215372
申请日：1998-12-18
申请人： Sun-Hak Lee
发明人： Sun-Hak Lee
IPC分类号： H01L2972
CPC分类号： H01L29/7802 , H01L29/1095 , H01L29/41766 , H01L29/42368 , H01L29/7809
摘要： There are provided a double-diffused MOS (Metal Oxide Semiconductor) transistor and a fabricating method thereof. In the double-diffused MOS transistor, a buried layer of a first conductive type and an epitaxial layer of the first conductive type are sequentially formed on a semiconductor substrate, and a gate electrode is formed on the epitaxial layer of the first conductive type with interposition of a gate insulating film. Source and drain regions of the first conductive type are formed in the surface of the epitaxial layer of the first conductive type in self-alignment and non-self-alignment with the gate electrode, respectively. A body region of a second conductive type is formed in the surface of the epitaxial layer of the first conductive type to be surrounded by the source region of the first conductive type, and a bulk bias region of the second conductive type is formed in the body region of the second conductive type under the source region of the first conductive type.
摘要翻译：提供双扩散MOS（金属氧化物半导体）晶体管及其制造方法。在双扩散MOS晶体管中，在半导体衬底上依次形成第一导电类型和第一导电类型的外延层的掩埋层，并且在具有插入的第一导电类型的外延层上形成栅电极的栅极绝缘膜。第一导电类型的源极和漏极区分别以与栅电极自对准和非自对准的方式形成在第一导电类型的外延层的表面中。第二导电类型的体区形成在第一导电类型的外延层的表面中，以被第一导电类型的源极区围绕，并且第二导电类型的体偏压区域形成在主体中在第一导电类型的源极区域下的第二导电类型的区域。

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