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1. 发明授权

US06540866B1 Method for lamination of fluoropolymer to metal and printed circuit board (PCB) substrate 失效
标题翻译：含氟聚合物层压到金属和印刷电路板（PCB）基板的方法
公开(公告)号：US06540866B1
公开(公告)日：2003-04-01
申请号：US09604959
申请日：2000-06-28
申请人： Junfeng Zhang , Cheng Qiang Cui , Thiam Beng Lim , En-Tang Kang
发明人： Junfeng Zhang , Cheng Qiang Cui , Thiam Beng Lim , En-Tang Kang
IPC分类号： B32B3112
CPC分类号： C08J7/18 , B32B7/12 , B32B27/06 , B32B38/162 , B32B2311/00 , B32B2327/12 , B32B2457/08 , C08J2327/12 , H05K3/386 , H05K2201/015 , H05K2201/0179 , H05K2201/0355 , H05K2203/095 , H05K2203/1168
摘要： The present invention is directed to a method for the lamination of fluoropolymers to the surfaces of metals, and especially to copper, gold, and platinum, and to printed circuit board (PCB) substrate at temperatures substantially below the sintering temperatures or melting temperatures of the fluoropolymers. More specifically, the invention is directed to a method for surface modification of fluoropolymers by thermal graft copolymerization with concurrent lamination of metals in the presence of a functional monomer and an adhesive such as an epoxy resin. The process can be carried out under atmospheric conditions and in the complete absence of an added polymerization initiator. The laminated fluoropolymer-metal or fluoropolymer-PCB substrate interfaces exhibit T-peel strengths of no less than 8 N/cm. This invention can also be applied to substantially improve the adhesion between PCB substrates and metals.
摘要翻译：本发明涉及一种用于将氟聚合物层压到金属表面，特别是铜，金和铂表面的方法，以及在基本上低于烧结温度或熔融温度的温度下的印刷电路板（PCB）含氟聚合物。更具体地，本发明涉及一种通过在功能性单体和诸如环氧树脂的粘合剂存在下金属的同时层压的热接枝共聚来进行含氟聚合物的表面改性的方法。该方法可以在大气条件下和完全不加入聚合引发剂的情况下进行。层压氟聚合物 - 金属或含氟聚合物 - PCB基板界面表现出不小于8N / cm的T-剥离强度。本发明也可以应用于基本上改善PCB衬底和金属之间的粘合性。

2. 发明授权

US06537411B1 Method for low temperature lamination of metals to polyimides 失效
标题翻译：金属与聚酰亚胺的低温层压方法
公开(公告)号：US06537411B1
公开(公告)日：2003-03-25
申请号：US09604960
申请日：2000-06-28
申请人： En-Tang Kang , Arthur Khoon Siah Ang , Koon Gee Neoh , Cheng Qiang Cui , Thiam Beng Lim
发明人： En-Tang Kang , Arthur Khoon Siah Ang , Koon Gee Neoh , Cheng Qiang Cui , Thiam Beng Lim
IPC分类号： B32B3112
CPC分类号： C08J7/16 , B32B15/08 , B32B38/0008 , B32B2310/0481 , B32B2310/0887 , B32B2310/14 , B32B2311/12 , B32B2379/08 , C08J5/124 , C08J2379/08 , H05K1/0346 , H05K3/38 , H05K3/381 , H05K3/386 , H05K2203/1168
摘要： The present invention is directed to a method for the lamination of metals, and especially copper, to the surface of polyimides and derivatives of polyimides at temperatures substantially below the curing temperature of the imide polymers. More specifically, the invention is directed to a method for surface modification of polyimides and derivatives of polyimides by thermal graft copolymerization and interfacial polymerization with concurrent lamination of the metal of interest in the presence of an appropriate functional monomer. The process can be carried out under atmospheric conditions and either in the presence or the complete absence of an added polymerization initiator. The so laminated polyimide-metal interfaces exhibit T-peel adhesion strengths in excess of 16 N/cm. The adhesion strength also exceeds the fracture strength of polyimide films with a thickness of 75 &mgr;m.
摘要翻译：本发明涉及一种用于在基本上低于酰亚胺聚合物的固化温度的温度下将金属，特别是铜层压到聚酰亚胺和聚酰亚胺衍生物的表面的方法。更具体地，本发明涉及通过热接枝共聚和界面聚合以及在合适的官能单体的存在下同时层压感兴趣的金属的聚酰亚胺和聚酰亚胺衍生物进行表面改性的方法。该方法可以在大气条件下进行，或者在存在或完全不存在加入的聚合引发剂的情况下进行。如此层压的聚酰亚胺 - 金属界面表现出超过16N / cm的T-剥离粘合强度。粘合强度也超过厚度为75μm的聚酰亚胺膜的断裂强度。

3. 发明授权

US06334926B1 Method for low temperature lamination of metals to fluoropolymers 失效
标题翻译：金属与含氟聚合物的低温层压方法
公开(公告)号：US06334926B1
公开(公告)日：2002-01-01
申请号：US09327959
申请日：1999-06-08
申请人： En Tang Kang , Jian-Li Shi , Koon Gee Neoh , Kuang Lee Tan , Cheng Qiang Cui , Thiam Beng Lim
发明人： En Tang Kang , Jian-Li Shi , Koon Gee Neoh , Kuang Lee Tan , Cheng Qiang Cui , Thiam Beng Lim
IPC分类号： B32B3112
CPC分类号： C08J5/124 , B32B15/08 , B32B38/0008 , B32B2037/0092 , B32B2310/14 , B32B2311/12 , B32B2327/12 , C08J7/123 , C08J2327/12 , H01L21/32051 , H01L21/76826
摘要： The present invention is directed to a method for the lamination of metals, and especially copper, to the surfaces of fluoropolymers at temperatures substantially below the sintering temperatures or melting temperatures of the fluoropolymers. More specifically, the invention is directed to a method for surface modification of fluoropolymers by thermal graft copolymerization with concurrent lamination of a metal (e.g. copper) in the presence of a functional monomer. The process can be carried out under atmospheric conditions and in the complete absence of an added polymerization initiator. The so-laminated fluoropolymer-metal interfaces exhibit T-peel strengths of no less than 8 N/cm and delaminate via cohesive failure inside the fluoropolymer.
摘要翻译：本发明涉及一种用于在基本上低于含氟聚合物的烧结温度或熔融温度的温度下将金属尤其是铜层压到含氟聚合物表面的方法。更具体地，本发明涉及一种通过在功能性单体存在下同时层压金属（例如铜）的热接枝共聚来表面改性含氟聚合物的方法。该方法可以在大气条件下和完全不加入聚合引发剂的情况下进行。如此层压的含氟聚合物 - 金属界面表现出不低于8N / cm的T剥离强度，并且通过含氟聚合物内部的内聚破坏而脱层。

4. 发明授权

US5893724A Method for forming a highly reliable and planar ball grid array package 失效
标题翻译：用于形成高可靠性和平面的球栅阵列封装的方法
公开(公告)号：US5893724A
公开(公告)日：1999-04-13
申请号：US582745
申请日：1996-01-04
申请人： Kishore Kumar Chakravorty , Thiam Beng Lim
发明人： Kishore Kumar Chakravorty , Thiam Beng Lim
IPC分类号： H01L21/56 , H01L23/31 , H01L23/495 , H01L21/60
CPC分类号： H01L23/3121 , H01L21/56 , H01L23/49503 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01039 , H01L2924/01079 , H01L2924/01087 , H01L2924/14 , H01L2924/15311 , H01L2924/15312 , H01L2924/181 , H01L2924/1815 , H01L2924/3511
摘要： The invention is directed to a BGA package and method for making a BGA package in which warpage, delamination and package cracking are reduced. The inventive BGA package has a die attached to one surface of a substrate. The substrate may terminate at its opposite surface in an array of connection ports which is an integral part of the substrate. Alternatively, the array of connection ports is attached to the opposite surface of the substrate. The connection ports may be attach pads attached to the opposite surface of the substrate and solder balls or metal bumps attached to the attach pads. A matrix of molding compound fully encapsulates the substrate, die and the array of connection ports. The matrix molding compound is then ground to provide a flat surface and to expose portions of the connection ports. Another array of connection ports, such as an array of solder balls or metal bumps, may be attached to the existing array of connection ports. In another embodiment, retracting pins are positioned over the solder attach pads. The mold compound fully encapsulates the substrate, die, solder attach pads and portions of the retracting pins. Removing the retracting pins, after the encapsulation, exposes portions of the solder attach pads so that solder balls or metal bumps are attached to the exposed portions of the solder attach pads.
摘要翻译：本发明涉及一种用于制造其中翘曲，分层和包装开裂的BGA封装的BGA封装和方法。本发明的BGA封装具有附接到衬底的一个表面的裸片。衬底可以在作为衬底的组成部分的连接端口阵列中的其相对表面处终止。或者，连接端口阵列附接到基板的相对表面。连接端口可以是附接到衬底的相对表面的附接焊盘和附接到附接焊盘的焊球或金属凸块。模塑料的基体完全封装基板，管芯和连接端口阵列。然后将基质模塑料研磨以提供平坦表面并暴露连接端口的部分。连接端口的另一阵列，例如焊球或金属凸块的阵列，可附接到现有的连接端口阵列。在另一个实施例中，缩回销定位在焊料附着焊盘上方。模具化合物完全封装基板，模具，焊料附着垫和缩回销的部分。在封装之后，移除回缩销以暴露焊料附着焊盘的部分，使得焊球或金属凸块附着到焊料附着焊盘的暴露部分。

5. 发明授权

US06621151B1 Lead frame for an integrated circuit chip 失效
标题翻译：集成电路芯片的引线框架
公开(公告)号：US06621151B1
公开(公告)日：2003-09-16
申请号：US09497421
申请日：2000-02-07
申请人： Tai Chong Chai , Thiam Beng Lim , Yong Chua Teo , James Tan , Raymundo Camenforte , Eric Neo , Daniel Yap
发明人： Tai Chong Chai , Thiam Beng Lim , Yong Chua Teo , James Tan , Raymundo Camenforte , Eric Neo , Daniel Yap
IPC分类号： H01L2348
CPC分类号： H01L23/49503 , H01L24/32 , H01L24/48 , H01L24/73 , H01L2224/05599 , H01L2224/29007 , H01L2224/32014 , H01L2224/32055 , H01L2224/32245 , H01L2224/45099 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/10158 , H01L2924/14 , H01L2924/181 , H01L2924/00012 , H01L2924/3512 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A lead-frame for connecting and supporting an integrated circuit having an apertured frame with dimensions smaller than the corresponding dimensions of the chip so that chip-pad shoulder can be eliminated and the chip attach fillet is made remote from the chip corner.
摘要翻译：一种用于连接和支撑集成电路的引线框架，该集成电路具有尺寸小于芯片的相应尺寸的有孔框架，使得可以消除芯片焊盘肩部并且芯片附接圆角远离芯片角落。

6. 发明授权

US5892290A Highly reliable and planar ball grid array package 失效
标题翻译：高度可靠和平面的球栅阵列封装
公开(公告)号：US5892290A
公开(公告)日：1999-04-06
申请号：US735791
申请日：1996-10-21
申请人： Kishore Kumar Chakravorty , Thiam Beng Lim
发明人： Kishore Kumar Chakravorty , Thiam Beng Lim
IPC分类号： H01L23/31 , H01L23/498 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/49816 , H01L23/3107 , H01L23/3128 , H01L2224/32225 , H01L2224/32245 , H01L2224/48227 , H01L2224/48247 , H01L2224/73265 , H01L2924/15311 , H01L2924/181 , H01L2924/1815
摘要： The invention is directed to a BGA package and method for making a BGA package in which warpage, delamination and package cracking are reduced. The inventive BGA package has a die attached to one surface of a substrate. The substrate may terminate at its opposite surface in an array of connection ports which is an integral part of the substrate. Alternatively, the array of connection ports is attached to the opposite surface of the substrate. The connection ports may be attach pads attached to the opposite surface of the substrate and solder balls or metal bumps attached to the attach pads. A matrix of molding compound fully encapsulates the substrate, die and the array of connection ports. The matrix molding compound is then ground to provide a flat surface and to expose portions of the connection ports. Another array of connection ports, such as an array of solder balls or metal bumps, may be attached to the existing array of connection ports. In another embodiment, retracting pins are positioned over the solder attach pads. The mold compound fully encapsulates the substrate, die, solder attach pads and portions of the retracting pins. Removing the retracting pins, after the encapsulation, exposes portions of the solder attach pads so that solder balls or metal bumps are attached to the exposed portions of the solder attach pads.
摘要翻译：本发明涉及一种用于制造其中翘曲，分层和包装开裂的BGA封装的BGA封装和方法。本发明的BGA封装具有附接到衬底的一个表面的裸片。衬底可以在作为衬底的组成部分的连接端口阵列中的其相对表面处终止。或者，连接端口阵列附接到基板的相对表面。连接端口可以是附接到衬底的相对表面的附接焊盘和附接到附接焊盘的焊球或金属凸块。模塑料的基体完全封装基板，管芯和连接端口阵列。然后将基质模塑料研磨以提供平坦表面并暴露连接端口的部分。连接端口的另一阵列，例如焊球或金属凸块的阵列，可附接到现有的连接端口阵列。在另一个实施例中，缩回销定位在焊料附着焊盘上方。模具化合物完全封装基板，模具，焊料附着垫和缩回销的部分。在封装之后，移除回缩销以暴露焊料附着焊盘的部分，使得焊球或金属凸块附着到焊料附着焊盘的暴露部分。

7. 发明授权

US5773878A IC packaging lead frame for reducing chip stress and deformation 失效
标题翻译： IC封装引线框架，用于减少芯片的应力和变形
公开(公告)号：US5773878A
公开(公告)日：1998-06-30
申请号：US582643
申请日：1996-01-04
申请人： Thiam Beng Lim , Sarvotham M. Bhandarkar
发明人： Thiam Beng Lim , Sarvotham M. Bhandarkar
IPC分类号： H01L21/56 , H01L23/31 , H01L23/495
CPC分类号： H01L23/3121 , H01L21/56 , H01L23/49503 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01039 , H01L2924/01079 , H01L2924/01087 , H01L2924/14 , H01L2924/15311 , H01L2924/15312 , H01L2924/181 , H01L2924/1815 , H01L2924/3511
摘要： The present invention relates to a lead frame design for IC packaging to reduce chip stress and deformation and to improve mold filling. The die-pad is split into several sections which are jointed together by flexible expansion joints. The split die-pad allows relative motion between the pad and the chip during die attach cure. It also breaks down the total die pad area (and length) that is rigidly attached to the chip into smaller sections. These two factors reduce the magnitude of coefficient-of-thermal expansion (CTE) mismatch and out of plane deformation of the assembly, resulting in lower chip stress and deformation and improved package moldability.
摘要翻译：本发明涉及一种用于IC封装的引线框架设计，以减少芯片的应力和变形并改善模具填充。模片分为几段，通过柔性膨胀节接合在一起。分开的模片垫允许在芯片附着固化期间焊盘和芯片之间的相对运动。它还将刚性连接到芯片的总芯片焊盘面积（和长度）分解成更小的部分。这两个因素降低了组件的热膨胀系数（CTE）失配和平面外变形的大小，从而降低了芯片的应力和变形，提高了封装成型性。

8. 发明授权

US06583501B2 Lead frame for an integrated circuit chip (integrated circuit peripheral support) 失效
公开(公告)号：US06583501B2
公开(公告)日：2003-06-24
申请号：US09499021
申请日：2000-02-07
申请人： Tai Chong Chai , Thiam Beng Lim , Yong Chua Teo , James Tan , Ray Camenforte , Eric Neo , Daniel Yap
发明人： Tai Chong Chai , Thiam Beng Lim , Yong Chua Teo , James Tan , Ray Camenforte , Eric Neo , Daniel Yap
IPC分类号： H01L23495
CPC分类号： H01L23/49503 , H01L23/3107 , H01L24/32 , H01L24/48 , H01L24/73 , H01L2224/05599 , H01L2224/32245 , H01L2224/45099 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , H01L2924/00012 , H01L2924/3512 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A lead-frame for connecting and supporting an integrated circuit chip with a chip accommodating zone with inwardly extending ears for supporting the chip including minimum shoulder area, and having open crack and delamination stopping regions.

9. 发明授权

US5925934A Low cost and highly reliable chip-sized package 失效
标题翻译：低成本和高可靠性的芯片尺寸封装
公开(公告)号：US5925934A
公开(公告)日：1999-07-20
申请号：US582744
申请日：1996-01-04
申请人： Thiam Beng Lim
发明人： Thiam Beng Lim
IPC分类号： H01L21/56 , H01L23/31 , H01L23/48 , H01L23/28 , H01L23/50
CPC分类号： H01L23/3114 , H01L21/565 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/83104 , H01L24/48 , H01L2924/00014 , H01L2924/00015 , H01L2924/01039 , H01L2924/01079 , H01L2924/10253 , H01L2924/12041 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181
摘要： The invention is directed to a chip-sized package (CSP) and method for making a CSP which is simple to manufacture, less costly and more compact, thus being truly a chip-sized package. The inventive CSP has a chip that has an array of chip ports on an active surface, such as an array of solder or metal bumps or any other conductive material. The chip may be held in a cavity of a frame by a pair of frame tie-bars. An encapsulant encapsulates the chip and portions of the chip ports located near the active surface, leaving portions of the chip ports located away from the active surface exposed. Package ports, such as solder balls may be attached to the portions of the chip ports located away from the active surface and used to attach the CSP to a printed circuit board. Various methods are used to leave portions of the chip ports located away from the active surface exposed from the encapsulant. The encapsulant may be removed by laser or grinding to expose portions of the chip ports. Alternatively, prior to encapsulation, the chip ports are positioned to sit on a mold, so that removing the mold leaves exposed the portions of the chip ports that were in contact with the mold. The mold may have an array of mold bumps or mold pockets upon which the chip ports sit. Removing the mold, exposes portions of the chip ports and leaves an array of openings in the encapsulant. Another method to form the array of openings in the encapsulant and expose portions of the chip ports uses an array of pins that are inserted in the encapsulant before it cures. The pins are inserted to contact the chip ports. Retracting the array of pins forms the array of openings in the encapsulant and exposes portions of the chip ports that were in contact with the pins.
摘要翻译：本发明涉及一种用于制造CSP的芯片尺寸封装（CSP）和方法，其制造简单，成本更低且更紧凑，因此是真正的芯片尺寸封装。本发明的CSP具有在有源表面上具有芯片端口阵列的芯片，例如焊料或金属凸块阵列或任何其它导电材料。芯片可以通过一对框架连接杆保持在框架的空腔中。密封剂封装芯片和位于有源表面附近的芯片端口的部分，使得远离有源表面的部分芯片端口露出。诸如焊球的封装端口可以附接到位于远离有源表面的芯片端口的部分，并用于将CSP连接到印刷电路板。使用各种方法来使位于远离密封剂暴露的活性表面的芯片端口部分。密封剂可以通过激光或研磨去除以暴露芯片端口的部分。或者，在封装之前，芯片端口定位成坐在模具上，使得移除模具离开露出与模具接触的芯片端口的部分。模具可以具有芯片端口位于其上的模具凸起或模具袋的阵列。去除模具，暴露芯片端口的一部分并在密封剂中留下一列开口。在密封剂中形成开口阵列并暴露芯片端口部分的另一种方法是使用在其固化之前插入密封剂中的引脚阵列。引脚插入以接触芯片端口。缩回销的阵列形成密封剂中的开口阵列，并露出与销接触的芯片端口部分。

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