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1. 发明申请

US20110235423A1 VERIFICATION PROCESS FOR NON-VOLATILE STORAGE 有权
标题翻译：非易失性存储的验证过程
公开(公告)号：US20110235423A1
公开(公告)日：2011-09-29
申请号：US13154810
申请日：2011-06-07
申请人： Gerrit Jan Hemink , Shih-Chung Lee , Toru Miwa , Yupin Fong , Jun Wan , Ken Oowada
发明人： Gerrit Jan Hemink , Shih-Chung Lee , Toru Miwa , Yupin Fong , Jun Wan , Ken Oowada
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3418
摘要： When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non-volatile storage elements.
摘要翻译：当擦除非易失性存储时，在擦除操作之间使用验证过程来确定非易失性存储器是否已被成功擦除。验证过程包括对非易失性存储元件的不同子集进行单独执行验证。

2. 发明授权

US07978527B2 Verification process for non-volatile storage 有权
标题翻译：非易失性存储的验证过程
公开(公告)号：US07978527B2
公开(公告)日：2011-07-12
申请号：US12132452
申请日：2008-06-03
申请人： Gerrit Jan Hemink , Shih-Chung Lee , Toru Miwa , Yupin Fong , Jun Wan , Ken Oowada
发明人： Gerrit Jan Hemink , Shih-Chung Lee , Toru Miwa , Yupin Fong , Jun Wan , Ken Oowada
IPC分类号： G11C16/06
CPC分类号： G11C16/3418
摘要： When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non-volatile storage elements.
摘要翻译：当擦除非易失性存储时，在擦除操作之间使用验证过程来确定非易失性存储器是否已被成功擦除。验证过程包括对非易失性存储元件的不同子集进行单独执行验证。

3. 发明申请

US20090296475A1 VERIFICATION PROCESS FOR NON-VOLATILE STORAGE 有权
标题翻译：非易失性存储的验证过程
公开(公告)号：US20090296475A1
公开(公告)日：2009-12-03
申请号：US12132452
申请日：2008-06-03
申请人： Gerrit Jan Hemink , Shih-Chung Lee , Toru Miwa , Yupin Fong , Jun Wan , Ken Oowada
发明人： Gerrit Jan Hemink , Shih-Chung Lee , Toru Miwa , Yupin Fong , Jun Wan , Ken Oowada
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C16/3418
摘要： When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non-volatile storage elements.
摘要翻译：当擦除非易失性存储时，在擦除操作之间使用验证过程来确定非易失性存储器是否已被成功擦除。验证过程包括对非易失性存储元件的不同子集进行单独执行验证。

4. 发明授权

US08218367B2 Verification process for non-volatile storage 有权
标题翻译：非易失性存储的验证过程
公开(公告)号：US08218367B2
公开(公告)日：2012-07-10
申请号：US13154810
申请日：2011-06-07
申请人： Gerrit Jan Hemink , Shih-Chung Lee , Toru Miwa , Yupin Fong , Jun Wan , Ken Oowada
发明人： Gerrit Jan Hemink , Shih-Chung Lee , Toru Miwa , Yupin Fong , Jun Wan , Ken Oowada
IPC分类号： G11C16/06
CPC分类号： G11C16/3418
摘要： When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non-volatile storage elements.
摘要翻译：当擦除非易失性存储时，在擦除操作之间使用验证过程来确定非易失性存储器是否已被成功擦除。验证过程包括对非易失性存储元件的不同子集进行单独执行验证。

5. 发明申请

US20120166913A1 Non-Volatile Memory And Methods With Asymmetric Soft Read Points Around Hard Read Points 有权
标题翻译：非易失性存储器和方法在硬读取点周围的不对称软读点
公开(公告)号：US20120166913A1
公开(公告)日：2012-06-28
申请号：US12978348
申请日：2010-12-23
申请人： Idan Alrod , Eran Sharon , Toru Miwa , Gerrit Jan Hemink , Yee Lih Koh
发明人： Idan Alrod , Eran Sharon , Toru Miwa , Gerrit Jan Hemink , Yee Lih Koh
IPC分类号： H03M13/05 , G06F11/10 , G11C16/04
CPC分类号： G11C11/5642 , G06F11/1072 , G11C16/26 , G11C29/00
摘要： A non-volatile memory has its cells' thresholds programmed within any one of a first set of voltage bands partitioned by a first set of reference thresholds across a threshold window. The cells are read at a higher resolution relative to a second set of reference thresholds so as to provide additional soft bits for error correction. The reference thresholds of the second set are set up to be non-uniformly distributed on the threshold window so as to provide higher resolution at designated regions. At the same time they are conducive to be read in groups for soft bits to be read bit-by-bit systematically with a simple algorithm and read circuit and using a minimum of data latches. This is accomplished by relaxing the requirement that the first set of reference threshold is a subset of the second set and that the resulting soft bits are symmetrically distributed about the hard bits.
摘要翻译：非易失性存储器的单元的阈值被编程在跨越阈值窗口的第一组参考阈值划分的第一组电压带的任一个中。相对于第二组参考阈值以更高的分辨率读取单元，以便提供用于纠错的附加软比特。第二组的参考阈值被设置为在阈值窗口上不均匀地分布，以便在指定区域提供更高的分辨率。同时，它们有助于读取组中的软位，通过简单的算法和读取电路并使用最少的数据锁存器逐位读取。这是通过放宽第一组参考阈值是第二组的子集并且所得到的软比特关于硬比特对称分布的要求来实现的。

6. 发明申请

US20100061151A1 MULTI-PASS PROGRAMMING FOR MEMORY WITH REDUCED DATA STORAGE REQUIREMENT 有权
标题翻译：具有减少数据存储要求的存储器的多级编程
公开(公告)号：US20100061151A1
公开(公告)日：2010-03-11
申请号：US12344763
申请日：2008-12-29
申请人： Toru Miwa , Gerrit Jan Hemink
发明人： Toru Miwa , Gerrit Jan Hemink
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/3418 , G11C2211/5621
摘要： Coupling effects between adjacent floating gates in a non-volatile storage device are reduced in a multi-pass programming operation, while reducing program data storage requirements. In one approach, storage elements are programmed in an out of sequence or zigzag word line order. A particular word line is programmed with a coarse program pass, after which another word line is programmed with a fine program pass, after which the particular word line is read. The particular word line is read before another word line is programmed with a coarse program pass which causes coupling interference to storage elements of the particular word line. The read data is subsequently used to perform a fine program pass for the particular word line. This avoids the need to store program data of multiple word lines concurrently, so that storage hardware can be reduced in size along with power consumption.
摘要翻译：在多通道编程操作中减少非易失性存储设备中的相邻浮动栅极之间的耦合效应，同时减少程序数据存储要求。在一种方法中，存储元件被编程为不按顺序或之字形字线顺序。一个特定的字线用一个粗略的程序通道进行编程，之后用一个精细的程序通道对另一个字线进行编程，然后读取特定的字线。在另一个字线被粗略编程通道编程之前读取特定字线，其导致对特定字线的存储元件的耦合干扰。读取的数据随后用于执行特定字线的精细节目通行。这避免了同时存储多个字线的程序数据的需要，使得存储硬件可以与功耗一起减小。

7. 发明授权

US08498152B2 Non-volatile memory and methods with soft-bit reads while reading hard bits with compensation for coupling 有权
标题翻译：非易失性存储器和具有软位读取的方法，同时读取具有补偿补偿的硬比特
公开(公告)号：US08498152B2
公开(公告)日：2013-07-30
申请号：US12978368
申请日：2010-12-23
申请人： Idan Alrod , Eran Sharon , Toru Miwa , Gerrit Jan Hemink , Nima Mokhlesi
发明人： Idan Alrod , Eran Sharon , Toru Miwa , Gerrit Jan Hemink , Nima Mokhlesi
IPC分类号： G11C11/34
CPC分类号： G11C16/34 , G06F11/1072 , G11C11/5642 , G11C16/26 , G11C16/3422 , G11C16/3427 , G11C29/00
摘要： A non-volatile memory has its cells' thresholds programmed within any one of a first set of voltage bands partitioned by a first set of reference thresholds across a threshold window. Hard bits are obtained when read relative to the first set of reference thresholds. The cells are read at a higher resolution relative to a second set of reference thresholds so as to provide additional soft bits for error correction. The soft bits are generated by a combination of a first modulation of voltage on a current word line WLn and a second modulation of voltage on an adjacent word line WLn+1, as in a reading scheme known as “Direct-Lookahead (DLA)”.
摘要翻译：非易失性存储器的单元的阈值被编程在跨越阈值窗口的第一组参考阈值划分的第一组电压带的任一个中。当读取相对于第一组参考阈值时，获得硬比特。相对于第二组参考阈值以更高的分辨率读取单元，以便提供用于纠错的附加软比特。软位是通过对当前字线WLn上的电压的第一次调制和相邻字线WLn + 1上的电压的第二调制的组合产生的，如在称为“直读先锋（DLA）”的读取方案中。

8. 发明申请

US20120163085A1 Non-Volatile Memory And Methods With Soft-Bit Reads While Reading Hard Bits With Compensation For Coupling 有权
标题翻译：非易失性存储器和方法在读取带有补偿补偿的硬位读取软位
公开(公告)号：US20120163085A1
公开(公告)日：2012-06-28
申请号：US12978368
申请日：2010-12-23
申请人： Idan Alrod , Eran Sharon , Toru Miwa , Gerrit Jan Hemink , Nima Mokhlesi
发明人： Idan Alrod , Eran Sharon , Toru Miwa , Gerrit Jan Hemink , Nima Mokhlesi
IPC分类号： G11C16/26
CPC分类号： G11C16/34 , G06F11/1072 , G11C11/5642 , G11C16/26 , G11C16/3422 , G11C16/3427 , G11C29/00
摘要： A non-volatile memory has its cells' thresholds programmed within any one of a first set of voltage bands partitioned by a first set of reference thresholds across a threshold window. Hard bits are obtained when read relative to the first set of reference thresholds. The cells are read at a higher resolution relative to a second set of reference thresholds so as to provide additional soft bits for error correction. The soft bits are generated by a combination of a first modulation of voltage on a current word line WLn and a second modulation of voltage on an adjacent word line WLn+1, as in a reading scheme known as “Direct-Lookahead (DLA)”.
摘要翻译：非易失性存储器的单元的阈值被编程在跨越阈值窗口的第一组参考阈值划分的第一组电压带的任一个中。当读取相对于第一组参考阈值时，获得硬比特。相对于第二组参考阈值以更高的分辨率读取单元，以便提供用于纠错的附加软比特。软位是通过对当前字线WLn上的电压的第一次调制和相邻字线WLn + 1上的电压的第二调制的组合产生的，如在称为“直读先锋（DLA）”的读取方案中。

9. 发明授权

US08130552B2 Multi-pass programming for memory with reduced data storage requirement 有权
标题翻译：用于存储器的多通程序编程，减少了数据存储要求
公开(公告)号：US08130552B2
公开(公告)日：2012-03-06
申请号：US12344763
申请日：2008-12-29
申请人： Toru Miwa , Gerrit Jan Hemink
发明人： Toru Miwa , Gerrit Jan Hemink
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C16/3418 , G11C2211/5621
摘要： Coupling effects between adjacent floating gates in a non-volatile storage device are reduced in a multi-pass programming operation, while reducing program data storage requirements. In one approach, storage elements are programmed in an out of sequence or zigzag word line order. A particular word line is programmed with a coarse program pass, after which another word line is programmed with a fine program pass, after which the particular word line is read. The particular word line is read before another word line is programmed with a coarse program pass which causes coupling interference to storage elements of the particular word line. The read data is subsequently used to perform a fine program pass for the particular word line. This avoids the need to store program data of multiple word lines concurrently, so that storage hardware can be reduced in size along with power consumption.
摘要翻译：在多通道编程操作中减少非易失性存储设备中的相邻浮动栅极之间的耦合效应，同时减少程序数据存储要求。在一种方法中，存储元件被编程为不按顺序或之字形字线顺序。一个特定的字线用一个粗略的程序通道进行编程，之后用一个精细的程序通道对另一个字线进行编程，然后读取特定的字线。在另一个字线被粗略编程通道编程之前读取特定字线，其导致对特定字线的存储元件的耦合干扰。读取的数据随后用于执行特定字线的精细节目通行。这避免了同时存储多个字线的程序数据的需要，使得存储硬件可以与功耗一起减小。

10. 发明授权

US08099652B1 Non-volatile memory and methods with reading soft bits in non uniform schemes 有权
标题翻译：非易失性存储器和在非均匀方案中读取软位的方法
公开(公告)号：US08099652B1
公开(公告)日：2012-01-17
申请号：US12978322
申请日：2010-12-23
申请人： Idan Alrod , Eran Sharon , Toru Miwa , Gerrit Jan Hemink , Yee Lih Koh
发明人： Idan Alrod , Eran Sharon , Toru Miwa , Gerrit Jan Hemink , Yee Lih Koh
IPC分类号： G11C29/00
CPC分类号： G11C16/26 , G06F11/1072 , G11C11/5642 , G11C29/00 , G11C2029/0411
摘要： A non-volatile memory has its cells' thresholds programmed within any one of a first set of voltage bands partitioned by a first set of reference thresholds across a threshold window. The cells are read at a higher resolution relative to a second set of reference thresholds so as to provide additional soft bits for error correction. The reference thresholds of the second set are set up to be non-uniformly distributed on the threshold window so as to provide higher resolution at designated regions. At the same time they are conducive to be read in groups for soft bits to be read bit-by-bit systematically with a simple algorithm and read circuit and using a minimum of data latches. This is accomplished by relaxing the requirement that the first set of reference threshold is a subset of the second set and that the resulting soft bits are symmetrically distributed about the hard bits.
摘要翻译：非易失性存储器的单元的阈值被编程在跨越阈值窗口的第一组参考阈值划分的第一组电压带的任一个中。相对于第二组参考阈值以更高的分辨率读取单元，以便提供用于纠错的附加软比特。第二组的参考阈值被设置为在阈值窗口上不均匀地分布，以便在指定区域提供更高的分辨率。同时，它们有助于读取组中的软位，通过简单的算法和读取电路并使用最少的数据锁存器逐位读取。这是通过放宽第一组参考阈值是第二组的子集并且所得到的软比特关于硬比特对称分布的要求来实现的。

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