专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07454586B2 Memory device commands 有权
标题翻译：内存设备命令
公开(公告)号：US07454586B2
公开(公告)日：2008-11-18
申请号：US11093705
申请日：2005-03-30
申请人： Jun Shi , Sandeep Jain , Animesh Mishra , Kuljit Bains , David Wyatt , Thomas D. Skelton , Bill H. Nale
发明人： Jun Shi , Sandeep Jain , Animesh Mishra , Kuljit Bains , David Wyatt , Thomas D. Skelton , Bill H. Nale
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G11C7/04 , G11C7/1045 , G11C11/4076
摘要： Data regarding physical parameters and security and commands to send such data can be communicated between a memory device and a memory controller using a memory bus connected between the two. In one embodiment, the invention includes receiving a first command at a memory device on a memory bus, the first command being other than a read or write command, and receiving a second command together with the first command, the second command to be initiated using lines that are not used by the first command.
摘要翻译：关于物理参数和安全性的数据以及发送这样的数据的命令可以使用连接在两者之间的存储器总线在存储器件和存储器控制器之间传送。在一个实施例中，本发明包括在存储器总线上的存储器件处接收第一命令，第一命令不同于读取或写入命令，并且与第一命令一起接收第二命令，使用第一个命令未使用的行。

2. 发明申请

US20060239095A1 Memory device communication using system memory bus 有权
标题翻译：使用系统内存总线的内存设备通讯
公开(公告)号：US20060239095A1
公开(公告)日：2006-10-26
申请号：US11093705
申请日：2005-03-30
申请人： Jun Shi , Sandeep Jain , Animesh Mishra , Kuljit Bains , David Wyatt , Thomas Skelton , Bill Nale
发明人： Jun Shi , Sandeep Jain , Animesh Mishra , Kuljit Bains , David Wyatt , Thomas Skelton , Bill Nale
IPC分类号： G11C7/00
CPC分类号： G11C7/04 , G11C7/1045 , G11C11/4076
摘要： Data regarding physical parameters and security and commands to send such data can be communicated between a memory device and a memory controller using a memory bus connected between the two. In one embodiment, the invention includes receiving a first command at a memory device on a memory bus, the first command being other than a read or write command, and receiving a second command together with the first command, the second command to be initiated using lines that are not used by the first command.
摘要翻译：关于物理参数和安全性的数据以及发送这样的数据的命令可以使用连接在两者之间的存储器总线在存储器件和存储器控制器之间传送。在一个实施例中，本发明包括在存储器总线上的存储器件处接收第一命令，第一命令不同于读取或写入命令，并且与第一命令一起接收第二命令，使用第一个命令未使用的行。

3. 发明授权

US08458507B2 Bus frequency adjustment circuitry for use in a dynamic random access memory device 有权
标题翻译：用于动态随机存取存储器件的总线频率调节电路
公开(公告)号：US08458507B2
公开(公告)日：2013-06-04
申请号：US12163663
申请日：2008-06-27
申请人： Joe Salmon , Kuljit Bains
发明人： Joe Salmon , Kuljit Bains
IPC分类号： G06F1/04 , G06F1/10 , G06F13/16
CPC分类号： G06F1/10 , G06F1/06
摘要： A clock divider circuitry and method for use in a dynamic random access memory device. The method may include receiving a clock input signal having a first frequency from a clock input receiver at clock divider circuitry, the clock divider circuitry including a flip-flop configured to generate an output signal, based at least in part, on an inverted output signal and the clock input signal. The output signal may have a second frequency that is a fraction of the first frequency. The method may further include receiving the clock input signal and the output signal at a multiplexer and generating a multiplexed output. The method may additionally include receiving the multiplexed output at a first bus configured to receive the multiplexed output and to reduce an operational frequency of the first bus in response to an increase in an operational frequency of a second bus associated with the memory device.
摘要翻译：一种用于动态随机存取存储器件的时钟分频器电路和方法。该方法可以包括：在时钟分频器电路处从时钟输入接收器接收具有第一频率的时钟输入信号，时钟分频器电路包括配置成产生输出信号的触发器，该触发器至少部分地基于反相输出信号和时钟输入信号。输出信号可以具有第二频率，其是第一频率的一部分。该方法还可以包括在多路复用器处接收时钟输入信号和输出信号，并产生多路输出。该方法可以另外包括：在被配置为接收多路复用输出的第一总线处接收多路复用输出并且响应于与存储器件相关联的第二总线的工作频率的增加而减小第一总线的工作频率。

4. 发明申请

US20070244948A1 Memory transfer with early access to critical portion 有权
标题翻译：具有早期访问关键部分的内存传输
公开(公告)号：US20070244948A1
公开(公告)日：2007-10-18
申请号：US11392471
申请日：2006-03-28
申请人： Kuljit Bains , John Halbert , Greg Lemos , Randy Osborne
发明人： Kuljit Bains , John Halbert , Greg Lemos , Randy Osborne
IPC分类号： G06F7/78
CPC分类号： G06F13/1678
摘要： In some embodiments, data may be transferred from a first memory agent to a second memory agent in a first format having a first width, and at least a critical portion of the data maybe transferred from the second memory agent back to the first memory agent in a second format having a second width, where the critical portion is included in a first frame. The critical portion may include a cacheline mapped over a memory device rank. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，数据可以以具有第一宽度的第一格式从第一存储器传送到第二存储器代理，并且数据的至少关键部分可以从第二存储器代理返回到第一存储器具有第二宽度的第二格式，其中临界部分包括在第一帧中。关键部分可以包括在存储器设备等级上映射的高速缓存线。描述和要求保护其他实施例。

5. 发明申请

US20050195629A1 Interchangeable connection arrays for double-sided memory module placement 审中-公开
标题翻译：用于双面内存模块放置的可互换连接阵列
公开(公告)号：US20050195629A1
公开(公告)日：2005-09-08
申请号：US10792350
申请日：2004-03-02
申请人： Michael Leddige , Kuljit Bains , John Sprietsma
发明人： Michael Leddige , Kuljit Bains , John Sprietsma
IPC分类号： G11C5/00 , G11C5/02 , H05K1/18
CPC分类号： H01L23/49816 , G11C5/02 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H05K1/181 , H05K2201/10159 , H05K2201/10734 , H05K2203/1572 , Y02P70/611
摘要： A memory module has an array of connections. The array of connections is arranged in rows and columns such that there are first and second outer columns. Connections in the first and second outer columns can be interchanged to optimize double-side module placement on a substrate.
摘要翻译：存储器模块具有连接阵列。连接阵列以行和列排列，使得存在第一和第二外部列。可以互换第一和第二外柱中的连接，以优化在基板上的双面模块放置。

6. 发明申请

US20050138267A1 Integral memory buffer and serial presence detect capability for fully-buffered memory modules 审中-公开
标题翻译：集成内存缓冲区和全缓存内存模块的串行存在检测功能
公开(公告)号：US20050138267A1
公开(公告)日：2005-06-23
申请号：US10746948
申请日：2003-12-23
申请人： Kuljit Bains , Robert Ellis , Chris Freeman , John Halbert , Michael Williams
发明人： Kuljit Bains , Robert Ellis , Chris Freeman , John Halbert , Michael Williams
IPC分类号： G11C5/00 , G11C7/10 , G11C7/20 , G06F12/16
CPC分类号： G11C7/1051 , G06F13/1673 , G06F13/1684 , G11C7/1078 , G11C7/20
摘要： Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, a serial presence detect function is included within a memory module buffer instead of being provided by a separate EEPROM device mounted on the memory module. Various embodiments thus can provide cost savings, chip placement and signal routing simplification, and can in some circumstances save pins on the module. Other embodiments are described and claimed.
摘要翻译：在实施例中包括用于缓冲存储器模块的方法和装置。在示例性系统中，串行存在检测功能被包括在存储器模块缓冲器内，而不是由安装在存储器模块上的单独的EEPROM器件提供。因此，各种实施例可以提供成本节省，芯片放置和信号路由简化，并且在某些情况下可以在模块上保存引脚。描述和要求保护其他实施例。

7. 发明申请

US20050071543A1 Memory buffer device integrating refresh 有权
标题翻译：内存缓冲设备集成刷新
公开(公告)号：US20050071543A1
公开(公告)日：2005-03-31
申请号：US10674981
申请日：2003-09-29
申请人： Robert Ellis , Kuljit Bains , Chris Freeman , John Halbert , Narendra Khandekar , Michael Williams
发明人： Robert Ellis , Kuljit Bains , Chris Freeman , John Halbert , Narendra Khandekar , Michael Williams
IPC分类号： G06F13/16 , G11C5/00 , G11C11/406 , G06F12/00
CPC分类号： G11C11/406 , G06F13/1636 , G11C2211/4061
摘要： Apparatus and method to carry out refresh operations on rows of memory cells within a memory device independently of a memory controller during times when there is no activity on a memory bus coupling the memory device to the memory controller that involves the memory device.
摘要翻译：在存储器总线上没有活动的情况下，独立于存储器控制器，在与存储器件相关联的存储器控制器的存储器总线的时间内，独立于存储器控制器，在存储器件中的行存储器单元上执行刷新操作的装置和方法。

8. 发明申请

US20130346684A1 METHOD, APPARATUS AND SYSTEM FOR A PER-DRAM ADDRESSABILITY MODE 审中-公开
标题翻译：方法，设备和系统，用于存储器可寻址模式
公开(公告)号：US20130346684A1
公开(公告)日：2013-12-26
申请号：US13531368
申请日：2012-06-22
申请人： Kuljit Bains
发明人： Kuljit Bains
IPC分类号： G06F12/00
CPC分类号： G11C7/1045 , G11C7/109 , G11C11/4096
摘要： Techniques and mechanisms for programming an operation mode of a dynamic random access memory (DRAM) device. In an embodiment, a memory controller stores a value in a mode register of a DRAM device, the value specifying whether a per-DRAM addressability (PDA) mode of the DRAM device is enabled. An external contact of the DRAM device is coupled to the memory controller device via a signal line of a data bus. In another embodiment, the memory controller sends a signal to the external contact while the PDA mode of the DRAM device is enabled, the signal to specify whether one or more features of the DRAM device are programmable.
摘要翻译：用于编程动态随机存取存储器（DRAM）设备的操作模式的技术和机制。在一个实施例中，存储器控制器将值存储在DRAM器件的模式寄存器中，该值指定DRAM器件的每DRAM可寻址（PDA）模式是否被使能。 DRAM器件的外部触点经由数据总线的信号线耦合到存储器控制器装置。在另一个实施例中，存储器控制器在DRAM器件的PDA模式被使能的同时向外部触点发送信号，该信号指定DRAM器件的一个或多个特征是否可编程。

9. 发明授权

US07404055B2 Memory transfer with early access to critical portion 有权
标题翻译：具有早期访问关键部分的内存传输
公开(公告)号：US07404055B2
公开(公告)日：2008-07-22
申请号：US11392471
申请日：2006-03-28
申请人： Kuljit Bains , John Halbert , Greg Lemos , Randy Osborne
发明人： Kuljit Bains , John Halbert , Greg Lemos , Randy Osborne
IPC分类号： G06F12/00
CPC分类号： G06F13/1678
摘要： In some embodiments, data may be transferred from a first memory agent to a second memory agent in a first format having a first width, and at least a critical portion of the data maybe transferred from the second memory agent back to the first memory agent in a second format having a second width, where the critical portion is included in a first frame. The critical portion may include a cacheline mapped over a memory device rank. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，数据可以以具有第一宽度的第一格式从第一存储器传送到第二存储器代理，并且数据的至少关键部分可以从第二存储器代理返回到第一存储器具有第二宽度的第二格式，其中临界部分包括在第一帧中。关键部分可以包括在存储器设备等级上映射的高速缓存线。描述和要求保护其他实施例。

10. 发明申请

US20070130374A1 Multiported memory with configurable ports 审中-公开
标题翻译：具有可配置端口的多端口存储器
公开(公告)号：US20070130374A1
公开(公告)日：2007-06-07
申请号：US11280837
申请日：2005-11-15
申请人： Kuljit Bains , John Halbert , Randy Osborne
发明人： Kuljit Bains , John Halbert , Randy Osborne
IPC分类号： G06F3/00
CPC分类号： G06F13/1694
摘要： In some embodiments, a chip includes memory banks and data ports, including at least first and second data ports, coupled to the memory banks. The chip also includes control circuitry to control a configuration of the first data port to be in one of multiple configurations in response to a configuration command, wherein the available configurations for the first data port include at least two of the following: whether the first data port (1) may only be used for read transactions, (2) may only be used for write transactions, or (3) may be used for either read or write transactions while in the configuration. Other embodiments are described.
摘要翻译：在一些实施例中，芯片包括耦合到存储体的存储器组和数据端口，包括至少第一和第二数据端口。该芯片还包括控制电路，用于响应于配置命令将第一数据端口的配置控制为多个配置之一，其中第一数据端口的可用配置包括以下中的至少两个：第一数据端口（1）只能用于读取事务，（2）只能用于写入事务，或者（3）可以在配置中用于读取或写入事务。描述其他实施例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式